Initial commit
This commit is contained in:
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module project_reti_logiche
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INFO: [VRFC 10-311] analyzing module glbl
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INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'project_tb_edge'
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#!/bin/bash -f
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# ****************************************************************************
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# Vivado (TM) v2025.2 (64-bit)
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#
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# Filename : compile.sh
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# Simulator : AMD Vivado Simulator
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# Description : Script for compiling the simulation design source files
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#
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# Generated by Vivado on Thu Jun 11 14:51:00 CEST 2026
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# usage: compile.sh
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#
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# ****************************************************************************
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export SIM_VER_XSIM=2025.2
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export GCC_VER_XSIM=9.3.0
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# catch pipeline exit status
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set -Eeuo pipefail
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# compile Verilog/System Verilog design sources
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echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj"
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xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log
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# compile VHDL design sources
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echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj"
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xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log
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echo "Waiting for jobs to finish..."
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echo "No pending jobs, compilation finished."
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Vivado Simulator v2025.2
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log
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Using 8 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT".
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INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT".
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.numeric_std
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Compiling package vl.vl_types
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Compiling module xil_defaultlib.glbl
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Compiling module simprims_ver.x_lut2_mux4
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Compiling module simprims_ver.LUT2
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Compiling module simprims_ver.LUT5
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Compiling module simprims_ver.LUT4
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Compiling module simprims_ver.x_lut1_mux2
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Compiling module simprims_ver.LUT1
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Compiling module simprims_ver.x_lut3_mux8
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Compiling module simprims_ver.LUT3
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Compiling module simprims_ver.LUT6
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Compiling module simprims_ver.FDPE_default
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Compiling module simprims_ver.FDCE_default
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Compiling module simprims_ver.CARRY4
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Compiling module simprims_ver.FDRE_default
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Compiling module simprims_ver.BUFG
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Compiling module simprims_ver.IBUF
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Compiling module simprims_ver.OBUF
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Compiling module xil_defaultlib.project_reti_logiche
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Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
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Built simulation snapshot project_tb_edge_time_synth
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#!/bin/bash -f
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# ****************************************************************************
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# Vivado (TM) v2025.2 (64-bit)
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#
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# Filename : elaborate.sh
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# Simulator : AMD Vivado Simulator
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# Description : Script for elaborating the compiled design
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#
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# Generated by Vivado on Thu Jun 11 14:51:01 CEST 2026
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# usage: elaborate.sh
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#
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# ****************************************************************************
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export SIM_VER_XSIM=2025.2
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export GCC_VER_XSIM=9.3.0
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# catch pipeline exit status
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set -Eeuo pipefail
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# elaborate design
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echo "xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log"
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xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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Load Diff
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Load Diff
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# compile vhdl design source files
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vhdl xil_defaultlib \
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"../../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \
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# Do not sort compile order
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nosort
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# compile verilog/system verilog design source files
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verilog xil_defaultlib --include "../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \
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"project_tb_edge_time_synth.v" \
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# Do not sort compile order
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nosort
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Time resolution is 1 ps
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Note: === GRUPPO 0: Reset ===
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Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.0 OK: reset base
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Time: 180 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.1 OK: reset asincrono durante operazione
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Time: 1860 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 1: Inserimento ===
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Time: 1860 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.0 OK: insert in lista vuota
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Time: 3613737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Failure: FAIL [1.1 count] addr=0 expected=0x3 actual=0x4
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Time: 6013737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 465
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Failure: FAIL [1.1 pos1] addr=1 expected=0x4 actual=0x0
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Time: 6013737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 466
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INFO: xsimkernel Simulation Memory Usage: 296232 KB (Peak: 342096 KB), Simulation CPU Usage: 820 ms
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#!/bin/bash -f
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# ****************************************************************************
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# Vivado (TM) v2025.2 (64-bit)
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#
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# Filename : simulate.sh
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# Simulator : AMD Vivado Simulator
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# Description : Script for simulating the design by launching the simulator
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#
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# Generated by Vivado on Thu Jun 11 14:51:06 CEST 2026
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# usage: simulate.sh
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#
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# ****************************************************************************
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export SIM_VER_XSIM=2025.2
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export GCC_VER_XSIM=9.3.0
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# catch pipeline exit status
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set -Eeuo pipefail
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# simulate design
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echo "xsim project_tb_edge_time_synth -key {Post-Synthesis:sim_1:Timing:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log"
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xsim project_tb_edge_time_synth -key {Post-Synthesis:sim_1:Timing:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log
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+1
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--incr --debug "typical" --relax --mt "8" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "project_tb_edge_time_synth" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log"
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+1
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Breakpoint File Version 1.0
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+12
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{
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crc : 10190631582523672948 ,
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ccp_crc : 0 ,
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cmdline : " --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl" ,
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buildDate : "Nov 14 2025" ,
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buildTime : "12:36:23" ,
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linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_time_synth/xsimk\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
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aggregate_nets :
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[
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]
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}
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+1
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hjhoth
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+50
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[General]
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ARRAY_DISPLAY_LIMIT=1024
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RADIX=hex
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TIME_UNIT=ns
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TRACE_LIMIT=65536
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VHDL_ENTITY_SCOPE_FILTER=true
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VHDL_PACKAGE_SCOPE_FILTER=false
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VHDL_BLOCK_SCOPE_FILTER=true
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VHDL_PROCESS_SCOPE_FILTER=false
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VHDL_PROCEDURE_SCOPE_FILTER=false
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VERILOG_MODULE_SCOPE_FILTER=true
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VERILOG_PACKAGE_SCOPE_FILTER=false
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VERILOG_BLOCK_SCOPE_FILTER=false
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VERILOG_TASK_SCOPE_FILTER=false
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VERILOG_PROCESS_SCOPE_FILTER=false
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INPUT_OBJECT_FILTER=true
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OUTPUT_OBJECT_FILTER=true
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INOUT_OBJECT_FILTER=true
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INTERNAL_OBJECT_FILTER=true
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CONSTANT_OBJECT_FILTER=true
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VARIABLE_OBJECT_FILTER=true
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INPUT_PROTOINST_FILTER=true
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OUTPUT_PROTOINST_FILTER=true
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INOUT_PROTOINST_FILTER=true
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INTERNAL_PROTOINST_FILTER=true
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CONSTANT_PROTOINST_FILTER=true
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VARIABLE_PROTOINST_FILTER=true
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SCOPE_NAME_COLUMN_WIDTH=150
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SCOPE_DESIGN_UNIT_COLUMN_WIDTH=233
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SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
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OBJECT_NAME_COLUMN_WIDTH=75
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OBJECT_VALUE_COLUMN_WIDTH=75
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OBJECT_DATA_TYPE_COLUMN_WIDTH=75
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PROCESS_NAME_COLUMN_WIDTH=75
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PROCESS_TYPE_COLUMN_WIDTH=75
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FRAME_INDEX_COLUMN_WIDTH=75
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FRAME_NAME_COLUMN_WIDTH=75
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FRAME_FILE_NAME_COLUMN_WIDTH=75
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FRAME_LINE_NUM_COLUMN_WIDTH=75
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LOCAL_NAME_COLUMN_WIDTH=75
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LOCAL_VALUE_COLUMN_WIDTH=75
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LOCAL_DATA_TYPE_COLUMN_WIDTH=0
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PROTO_NAME_COLUMN_WIDTH=0
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PROTO_VALUE_COLUMN_WIDTH=0
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INPUT_LOCAL_FILTER=1
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OUTPUT_LOCAL_FILTER=1
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INOUT_LOCAL_FILTER=1
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INTERNAL_LOCAL_FILTER=1
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CONSTANT_LOCAL_FILTER=1
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VARIABLE_LOCAL_FILTER=1
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Executable
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Running: xsim.dir/project_tb_edge_time_synth/xsimk -simmode gui -wdb project_tb_edge_time_synth.wdb -simrunnum 0 -socket 39331
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Design successfully loaded
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Design Loading Memory Usage: 202828 KB (Peak: 202828 KB)
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Design Loading CPU Usage: 730 ms
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Simulation completed
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Simulation Memory Usage: 296232 KB (Peak: 342096 KB)
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Simulation CPU Usage: 820 ms
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0.7
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2020.2
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Nov 14 2025
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12:36:23
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/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v,1781182260,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
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/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
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hjhoth
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xil_defaultlib=xsim.dir/xil_defaultlib
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INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" into library xil_defaultlib
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INFO: [VRFC 10-3107] analyzing entity 'project_tb_edge'
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module project_reti_logiche
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INFO: [VRFC 10-311] analyzing module glbl
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