Aleandro 259f6d5803 Initial commit

2026-06-12 20:37:03 +02:00

INFO

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.cache

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.hw

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.ip_user_files

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.runs

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.sim/sim_1

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.srcs

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.xpr

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_behav.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_behav1.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_behav.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_func_synth.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

S

Description

No description provided

99 MiB

Languages

Verilog 46.2%

C 35.7%

VHDL 9.6%

PureBasic 3%

TeX 2.8%

Other 2.6%