Aleandro 259f6d5803 Initial commit

2026-06-12 20:37:03 +02:00

INFO

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.cache

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progetto_reti_logiche.hw

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progetto_reti_logiche.ip_user_files

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progetto_reti_logiche.runs

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progetto_reti_logiche.sim/sim_1

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progetto_reti_logiche.srcs

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progetto_reti_logiche.xpr

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project_tb_behav.wcfg

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project_tb_edge_behav1.wcfg

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project_tb_edge_behav.wcfg

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project_tb_edge_func_synth.wcfg

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S

Description

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105 MiB

Languages

Verilog 45.1%

C 34.8%

VHDL 11.2%

TeX 3.3%

PureBasic 2.9%

Other 2.6%