commit 259f6d5803718e7a068c32b9d56d560df50ca398 Author: aleandro Date: Fri Jun 12 20:37:03 2026 +0200 Initial commit diff --git a/INFO/PFRL_Regole_2526.md b/INFO/PFRL_Regole_2526.md new file mode 100644 index 0000000..03ba76d --- /dev/null +++ b/INFO/PFRL_Regole_2526.md @@ -0,0 +1,229 @@ +Progetto di Reti Logiche + +Prof. Fornaciari, Prof. Palermo e Prof. Salice +Anno Accademico 2025 - 2026 + +REGOLE per lo svolgimento del progetto +(Aggiornamento del 27 Novembre 2025) + +Compito dello studente è quello di descrivere in VHDL e sintetizzare il componente HW che +implementa la specifica richiesta, interfacciandosi con una memoria dove sono memorizzati i +dati e dove andrà scritto il risultato finale. Allo studente verrà fornito un Test Bench di +esempio (che include la memoria) per validare il corretto funzionamento del modulo +implementato. + +● + +● + +Il progetto può essere svolto in gruppi composti da un massimo di 2 studenti che +debbono avere il medesimo docente di riferimento. +Il progetto è una attività autonoma che non coinvolge in nessun modo il corpo +docente a meno di chiarimenti sulla specifica di progetto. + +● Nel caso il testo di specifica risulti incompleto, è compito del gruppo di lavoro + +contattare i docenti motivando accuratamente la ragione della incompletezza. + +● Strumento di sintesi da usare è XILINX VIVADO WEBPACK e la FPGA target può +essere qualunque perchè il progetto è talmente piccolo che non ha problemi. +(Esempio: Artix-7 FPGA xc7a200tfbg484-1) + +Il progetto deve funzionare con un periodo di clock di almeno 20 ns; + +Criteri di valutazione + +● Un componente descritto e simulabile correttamente in pre-sintesi viene valutato fino + +ad un massimo di 24. + +● Un componente sintetizzabile e correttamente simulabile in post-sintesi può ottenere +una valutazione superiore a 24: fino a 30 per un progetto fatto in coppia, fino a 30L +per un progetto svolto da un singolo studente. + +● Lo studente deve allegare al progetto come documentazione una relazione. +Quest’ultima deve includere: 1) specifiche di progetto 2) scelte progettuali 3) risultati +dei test fatti e le ragioni di tali test (motivare le scelte) 4) risultati della sintesi. Nel +caso di un componente descritto e simulabile correttamente in pre-sintesi questo +deve essere chiaramente segnalato anche nella relazione. La qualità della relazione +concorre alla definizione del voto complessivo. +Il voto finale, in entrambi i casi, terrà conto dei test superati dal componente, dalla +qualità del codice VHDL e della relazione presentata (incluse le scelte progettuali). +Un progetto fatto in coppia può comunque raggiungere la lode grazie alla valutazione +complessiva dell’implementazione e della relazione. + +● + +● ATTENZIONE: non è possibile rifiutare il voto finale. Questo è dovuto alla +tipologia del progetto che è considerato, da regolamento didattico, una “PROVA +FINALE”. + +● E’ facoltà dei docenti richiedere un'integrazione mediante una discussione orale o +una prova pratica relativamente allo sviluppo del progetto nell'ambiente suggerito, in +aggiunta alla valutazione basata sulla prova di funzionamento del codice e della +relazione. + + Criteri di Consegna + +● La specifica del progetto resta invariata per tutto l’anno accademico. La consegna +del progetto può essere fatta solo una volta nell’arco dell’anno accademico con la +possibilità di una ed unica risottomissione in caso di insufficienza (si legga la nota +successiva). + +● + +● NOTA: nel caso che la prima consegna risulti insufficiente (9 0), esso +deve comportarsi come segue: + +● Dopo un reset, la lista deve essere considerata vuota. Il modulo deve quindi scrivere + +il valore zero all’indirizzo 0 della memoria. + +● Durante questa fase di inizializzazione, il segnale DONE deve essere mantenuto a 1, +indicando che il modulo non è ancora pronto a ricevere operazioni, e solo dopo che +l’azzeramento è stato effettuato, il modulo può riportare DONE a 0 e rendersi +disponibile a nuove operazioni. + +Il modulo deve garantire: + +Il corretto aggiornamento della memoria in seguito a ogni operazione. +Il mantenimento dell’ordine dei task nella lista. + +● +● +● La gestione appropriata dei casi limite, ad esempio lista vuota. +● + +Il rispetto del protocollo START-DONE come descritto. + +Si precisa che +la presente specifica descrive un comportamento completamente +deterministico: a parità di sequenze di ingresso, le uscite generate e il contenuto della +memoria nella parte valida (lista dei task) risultano invariati. Qualsiasi eventuale scenario +che presenti ambiguità o comportamenti non univocamente determinati dovrà essere +identificato e prontamente segnalato. + + Interfaccia del Componente +Il modulo da implementare ha 4 ingressi primari, uno ad 1 bit (i_start), uno a 6 bit (i_task_id), +uno a 2 bit (i_task_priority) e uno da 2 bit (i_op), e due uscite primarie, una da 1 bit (o_done) +e una da 6 bit (o_task_id). Inoltre, il modulo ha un segnale di clock CLK, unico per tutto il +sistema e un segnale di reset RESET anch’esso unico per tutto il sistema. Tutti i segnali +sono sincroni e devono essere interpretati sul fronte di salita del clock. L’unica eccezione è +RESET che, invece, è asincrono. RESET può essere generato in qualsiasi momento +dell’esecuzione. + +Il componente da descrivere deve avere la seguente interfaccia. + +entity project_reti_logiche is + +port ( + +i_clk : in std_logic; + +i_rst : in std_logic; + +i_start + +: in std_logic; + +i_task_id + +: in std_logic_vector(5 downto 0); + +i_task_priority : in std_logic_vector(1 downto 0); + +i_op : in std_logic_vector(1 downto 0); + +o_done : out std_logic; + +o_task_id : out std_logic_vector(5 downto 0); + +o_mem_addr : out std_logic_vector(15 downto 0); + +i_mem_data : in std_logic_vector(7 downto 0); + +o_mem_data : out std_logic_vector(7 downto 0); + +o_mem_we : out std_logic; + +o_mem_en : out std_logic + +); + +end project_reti_logiche; + +In particolare: + +● + +● +● + +● +● + +il nome del modulo deve essere project_reti_logiche e deve essere +presente una sola architettura per ogni entità; la violazione di queste +indicazioni comporta +il Test Bench e una +l’impossibilità di eseguire +conseguente valutazione di zero; +i_clk è il segnale di CLOCK in ingresso generato dal Test Bench; +i_rst è il segnale di RESET che inizializza la macchina pronta per ricevere il +primo segnale di START; +i_start è il segnale di START generato dal Test Bench; +i_task_id è il vettore di bit rappresentante il ID_TASK generato dal Test +Bench; + + ● + +● + +i_task_priority è il vettore di bit rappresentante il PRIORITY generato dal Test +Bench; +i_op è il vettore di 2 bit rappresentante l’operazione da dover effettuare sulla +lista di task; + +● o_done è il segnale DONE di uscita che comunica la fine dell’elaborazione; +● o_task_id è il vettore di bit rappresentante il ID_TASK del task a priorità più + +alta estratto dalla memoria; + +● o_mem_addr è il segnale (vettore) di uscita che manda l’indirizzo alla + +● + +memoria; +i_mem_data è il segnale (vettore) che arriva dalla memoria e contiene il dato +in seguito ad una richiesta di lettura; + +● o_mem_data è il segnale (vettore) che va verso la memoria e contiene il dato + +che verrà successivamente scritto; + +● o_mem_en è il segnale di ENABLE da dover mandare alla memoria per poter + +comunicare (sia in lettura che in scrittura); + +● o_mem_we è il segnale di WRITE ENABLE da dover mandare alla memoria + +(=1) per poter scriverci. Per leggere da memoria, esso deve essere 0. + + APPENDICE: Descrizione Memoria +NOTA: La memoria è già istanziata all’interno del Test Bench e non va sintetizzata + +La memoria e il suo protocollo può essere estratto dalla seguente descrizione VHDL che fa +parte del test bench e che è derivata dalla User guide di VIVADO disponibile al seguente +link: +https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug901-vivado-synth +esis.pdf + +-- Single-Port Block RAM Write-First Mode (recommended template) +-- +-- File: rams_02.vhd +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +entity rams_sp_wf is +port( + clk : in std_logic; + we : in std_logic; + en : in std_logic; + addr : in std_logic_vector(15 downto 0); + di : in std_logic_vector(7 downto 0); + do : out std_logic_vector(7 downto 0) +); +end rams_sp_wf; + +architecture syn of rams_sp_wf is +type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); +signal RAM : ram_type; +begin + process(clk) + +begin +if clk'event and clk = '1' then +if en = '1' then + if we = '1' then + +RAM(conv_integer(addr)) <= di; +do + +<= di after 2 ns; + + else + +do <= RAM(conv_integer(addr)) after 2 ns; + + end if; +end if; +end if; + end process; +end syn; + + ESEMPIO +L’esempio qui di seguito mostra il comportamento a seguito dei segnali di ingresso. Qui di +seguito è presente la situazione della memoria a seguito dell’inserimento di diversi task (fase +non mostrata nell’esempio). I valori non espliciti sono valori di memoria che non vengono +considerati per il normale funzionamento. + +SITUAZIONE INIZIALE (6 task già in tabella) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01000000 + +0x01011000 + +0x01011100 + +0x01010101 + +0x01110010 + +0x00010011 + +16 + +22 + +23 + +21 + +28 + +4 + +0 + +0 + +0 + +1 + +2 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +OPERAZIONE: 00 (incremento valore di priorità) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01000001 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01110011 + +0x00010011 + +16 + +22 + +23 + +21 + +28 + +4 + +1 + +1 + +1 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + + OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 19 - PRIORITY: 2 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000111 + +0x01000001 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01001110 + +0x01110011 + +0x00010011 + +16 + +22 + +23 + +21 + +19 + +28 + +4 + +1 + +1 + +1 + +2 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +8 + +OPERAZIONE: 01 (rimuove il primo task) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01001110 + +0x01110011 + +0x00010011 + +22 + +23 + +21 + +19 + +28 + +4 + +1 + +1 + +2 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + + OPERAZIONE: 11 (svuota la lista) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000000 + +0 + +1 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 31 - PRIORITY: 3 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000001 + +0x01111111 + +0 + +1 + +2 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 15 - PRIORITY: 0 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000010 + +0x00111100 + +0x01111111 + +15 + +31 + +0 + +3 + +0 + +1 + +2 + +3 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 20 - PRIORITY: 0 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0 + +1 + +2 + +3 + +0x000000011 + +0x00111100 + +0x01010000 + +0x01111111 + +15 + +20 + +31 + +0 + +0 + +3 + + Progetto di Reti Logiche + +Prof. Fornaciari, Prof. Palermo e Prof. Salice +Anno Accademico 2025 - 2026 + +NOTE DI AGGIORNAMENTO DELLA SPECIFICA + +In questa pagina potete trovare le modifiche fatte alla specifica del progetto dal suo primo rilascio. +Tutti i cambiamenti con data annessa saranno riportati qui sotto e sono mantenuti in rosso nel testo. + +Errata Corrige: + +- Aggiornamento 24.02.2026: + +- + +Il numero massimo di task nella lista non è 31 come nella versione originale ma 63. +Questo è derivato dal fatto che il numero di bit per il task_id è 6. + diff --git a/INFO/Relazione.tex b/INFO/Relazione.tex new file mode 100644 index 0000000..84ea047 --- /dev/null +++ b/INFO/Relazione.tex @@ -0,0 +1,793 @@ +\documentclass[12pt,a4paper]{article} + +% --- Preambolo --- +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage[italian]{babel} +\usepackage{amsmath, amsfonts, amssymb} +\usepackage{geometry} +\usepackage{graphicx} +\usepackage{listings} +\usepackage{xcolor} +\usepackage{lstautogobble} + +\usepackage{booktabs} +\usepackage{xcolor} +\usepackage{colortbl} +\usepackage{float} + +\usepackage{caption} + +\usepackage{hyperref} +\hypersetup{ + colorlinks=false, + pdfborder={0 0 0} +} + + +\geometry{a4paper, margin=3cm} + +% Configurazione professionale per il codice VHDL +\lstset{ + language=VHDL, + basicstyle=\ttfamily\small, % Font monospaziato piccolo + keywordstyle=\color{blue}, % Parole chiave in blu + commentstyle=\color{gray}, % Commenti in grigio + breaklines=true, % VA A CAPO AUTOMATICAMENTE + frame=single, % Bordo attorno al codice + numbers=left, % Numeri di riga a sinistra + numberstyle=\tiny\color{gray}, + xleftmargin=10pt, % Margine per far rientrare i numeri di riga + showstringspaces=false, + autogobble=true, + tabsize=2, +} + +\begin{document} + + \begin{titlepage} + \centering + {\large \textbf{POLITECNICO DI MILANO 1863}} \\ + \vspace{1cm} + \includegraphics[width=0.4\textwidth]{logo_polimi.jpg} \\ + \vspace{2cm} + + {\Large \textbf{Relazione Progetto Reti Logiche}} \\ + \vspace{1cm} + + {\large Aleandro Pagani} \\ + \vspace{0.5cm} + {\large Giugno 2026} \\ + + \vfill + + {\large Matricola: 236992} \\ + {\large Codice persona: 10893566} \\ + \vspace{1cm} + {\large Professore: Fabio Salice} + \end{titlepage} + + \newpage + + \pagenumbering{roman} + \tableofcontents + \newpage + + + + \pagenumbering{arabic} + \section{Introduzione} + \subsection{Specifiche generali} + \subsubsection{Descrizione} + + Il progetto consiste nel descrivere un modulo hardware che si interfaccia con una memoria in cui la prima cella contiene il contatore dei task e le celle successive la lista ordinata. Il modulo deve supportare quattro tipi di operazioni il cui codice identificativo è fornito in ingresso: + \begin{itemize} + \item \textbf{00}: Decrementa la priorità di tutti i task + \item \textbf{01}: Rimuove il primo task della lista + \item \textbf{10}: Aggiunge un nuovo task in lista + \item \textbf{11}: Svuota completamente la lista + \end{itemize} + +\begin{figure}[H] + \centering + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_00.png} + \caption*{OP 00.} + \label{fig:00} + \end{minipage} + \hfill + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_01.png} + \caption*{OP 01.} + \label{fig:01} + \end{minipage} +\end{figure} + +\begin{figure}[H] + \centering + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_10.png} + \caption*{OP 10 (inserisco task 000000 01).} + \label{fig:10} + \end{minipage} + \hfill + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_11.png} + \caption*{OP 11.} + \label{fig:11} + \end{minipage} + \end{figure} + + \newpage + + + + + + + + \subsubsection{Funzionamento} + La sincronizzazione tra la logica esterna e il modulo hardware avviene tramite un protocollo di handshake \textbf{START-DONE}. + Il funzionamento del modulo è scandito attraverso 5 fasi: + \begin{itemize} + \item \textbf{Inizializzazione:} Vengono forniti i dati e posto il segnale \textbf{START} a 1. + \item \textbf{Elaborazione:} Il modulo avvia le operazioni e interagisce con la memoria. + \item \textbf{Completamento:} Terminate le operazioni, il modulo imposta il segnale \textbf{DONE} a 1. + \item \textbf{Riconoscimento:} La logica esterna pone il segnale \textbf{START} a 0. + \item \textbf{Ripristino:} Il modulo riporta il segnale \textbf{DONE} a 0 e torna in attesa di nuove direttive. + \end{itemize} + + \vspace{0.5cm} + \centerline{\includegraphics[width=0.6\textwidth]{START-DONE handshake.png}} + \newpage + + + + + + + + + + + + + + \subsection{Descrizione modulo} + + \begin{lstlisting} + entity project_reti_logiche is + port ( + i_clk: in std_logic; + i_rst: in std_logic; + + i_start: in std_logic; + i_task_id: in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op: in std_logic_vector(1 downto 0); + + o_done: out std_logic; + o_task_id: out std_logic_vector(5 downto 0); + + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we: out std_logic; + o_mem_en: out std_logic + ); + end project_reti_logiche; + \end{lstlisting} + + \begin{itemize} + \item \textbf{i\_clk:} Segnale di clock + \item \textbf{i\_rst:} Segnale di reset + \vspace{0.5cm} + \item \textbf{i\_start:} Segnale \textbf{START} di handshake + \item \textbf{i\_task\_id:} Codice del task da inserire + \item \textbf{i\_task\_priority:} Priorità del task da inserire + \item \textbf{i\_op:} ID dell'operazione da eseguire + \vspace{0.5cm} + \item \textbf{o\_done:} Segnale \textbf{DONE} di handshake + \item \textbf{o\_task\_id:} Codice del task restituito dall'eliminazione + \vspace{0.5cm} + \item \textbf{o\_mem\_addr:} Indirizzo di memoria con cui interagire + \item \textbf{i\_mem\_data:} Informazioni lette dalla memoria + \item \textbf{o\_mem\_data:} Informazioni da scrivere in memoria + \item \textbf{o\_mem\_we:} Flag per abilitare la scrittura in memoria + \item \textbf{o\_mem\_en:} Flag per abilitare la lettura in memoria + \end{itemize} + \newpage + + + + + + \subsection{Descrizione memoria} + \subsubsection{Implementazione fornita} + \begin{lstlisting} + library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + + entity rams_sp_wf is + port( + clk : in std_logic; + we : in std_logic; + en : in std_logic; + addr : in std_logic_vector(15 downto 0); + di : in std_logic_vector(7 downto 0); + do : out std_logic_vector(7 downto 0) + ); + end rams_sp_wf; + + architecture syn of rams_sp_wf is + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type; + begin + process(clk) + begin + if clk'event and clk = '1' then + if en = '1' then + if we = '1' then + RAM(conv_integer(addr)) <= di; + do <= di; -- Write-First + else + do <= RAM(conv_integer(addr)); + end if; + end if; + end if; + end process; + end syn; + \end{lstlisting} + + \begin{itemize} + \item \textbf{clk:} Segnale di clock + \item \textbf{we:} Flag di scrittura + \item \textbf{en:} Flag di lettura + \item \textbf{addr:} Indirizzo con cui interagire + \item \textbf{di:} Dati in ingresso + \item \textbf{do:} Dati in uscita + \end{itemize} + \newpage + + \subsubsection{Layout di memoria} + La RAM indirizza 65536 celle da un byte (indirizzi a 16 bit); la lista ne utilizza al più 64: la prima (\textbf{0}) rappresenta il numero di task presenti, le successive contengono i task (al massimo 63, dato che gli ID sono a 6 bit e l'ID 0 è riservato).\\ + Per ogni task, i primi 6 bit ne identificano il codice, mentre gli ultimi 2 la priorità. + \vspace{0.7cm} + + + \begin{minipage}[c]{0.30\textwidth} + \centering + \includegraphics[width=\textwidth]{MemoryDiagram.png} + \end{minipage} + \hfill + \begin{minipage}[c]{0.60\textwidth} + + In questo esempio abbiamo 3 task: + \begin{itemize} + \item \textbf{001111 00:} Task con codice 15 e priorità 0 + \item \textbf{010100 00:} Task con codice 20 e priorità 0 + \item \textbf{011011 11:} Task con codice 27 e priorità 3 + \end{itemize} + Tutti gli altri elementi in memoria non vengono considerati validi. + \end{minipage} + \newpage + + + + + + + + + + + + + + + + + \section{Architettura} + Data la dimensione ridotta del progetto, il componente è composto da un unico modulo con due processi: uno sincrono e uno combinatorio. + + Nell'implementazione presentata è stata privilegiata la leggibilità rispetto all'efficienza e alla minimizzazione del numero di segnali. + + \subsection{Segnali interni} + \begin{lstlisting} + signal state : state_type; + signal next_state : state_type; + + signal current_mem_addr : std_logic_vector(15 downto 0); + signal next_mem_addr : std_logic_vector(15 downto 0); + + signal current_task_count : std_logic_vector(7 downto 0); + signal next_task_count : std_logic_vector(7 downto 0); + + signal current_popped_id : std_logic_vector(5 downto 0); + signal next_popped_id : std_logic_vector(5 downto 0); + + signal ctrl_done : std_logic; + signal ctrl_mem_en : std_logic; + signal ctrl_mem_we : std_logic; + signal ctrl_mem_data : std_logic_vector(7 downto 0); + signal ctrl_task_id : std_logic_vector(5 downto 0); + \end{lstlisting} + + I registri interni sono organizzati in coppie \textbf{current\_*}/\textbf{next\_*}: il processo combinatorio calcola il valore \textbf{next\_*}, il processo sincrono lo registra in \textbf{current\_*} sul fronte di clock. + + \begin{itemize} + \item \textbf{state:} Stato attuale dell'FSM + \item \textbf{next\_state:} Prossimo stato dell'FSM + \vspace{0.5cm} + \item \textbf{current\_mem\_addr / next\_mem\_addr:} Indirizzo di memoria su cui la FSM sta lavorando (0 = contatore, 1..N = task) + \item \textbf{current\_task\_count / next\_task\_count:} Copia locale del numero di task presenti in lista (cella 0 della memoria) + \item \textbf{current\_popped\_id / next\_popped\_id:} ID estratto dall'ultima rimozione, presentato su \textbf{o\_task\_id} quando \textbf{DONE} viene alzato + \vspace{0.5cm} + \item \textbf{ctrl\_done:} Segnale di controllo di \textbf{DONE} + \item \textbf{ctrl\_mem\_en:} Segnale per abilitare la lettura in memoria + \item \textbf{ctrl\_mem\_we:} Segnale per abilitare la scrittura in memoria + \item \textbf{ctrl\_mem\_data:} Dati da scrivere in memoria + \item \textbf{ctrl\_task\_id:} Valore da presentare sull'uscita \textbf{o\_task\_id} + \end{itemize} + + \subsection{Processo sincrono} + Questo processo registra sul fronte di salita del clock lo stato, i registri e tutte le uscite del modulo. + \begin{lstlisting} + process(i_clk, i_rst) + begin + if i_rst = '1' then + state <= S_RESET; + o_done <= '1'; + o_mem_en <= '0'; + o_mem_we <= '0'; + elsif rising_edge(i_clk) then + state <= next_state; + current_mem_addr <= next_mem_addr; + current_task_count <= next_task_count; + current_popped_id <= next_popped_id; + + o_done <= ctrl_done; + o_mem_en <= ctrl_mem_en; + o_mem_we <= ctrl_mem_we; + o_mem_addr <= next_mem_addr; + o_mem_data <= ctrl_mem_data; + o_task_id <= ctrl_task_id; + end if; + end process; + \end{lstlisting} + Sul fronte di salita del clock i registri \textbf{current\_*} vengono aggiornati con i corrispettivi valori \textbf{next\_*} e, contemporaneamente, vengono scritti sui bus di uscita \textbf{o\_*} i valori calcolati dal processo combinatorio. + + Il reset, asincrono, porta la FSM in \textbf{S\_RESET} con \textbf{DONE} a 1 (come richiesto dalla specifica) e disabilita l'interfaccia verso la memoria: in questo modo il modulo non può produrre scritture involontarie mentre il reset è attivo, indipendentemente dall'istante in cui arriva. + + \vspace{0.5cm} + Due scelte progettuali meritano attenzione: + \begin{itemize} + \item \textbf{Uscite registrate:} I segnali interni \textbf{ctrl\_*} vengono assegnati alle uscite \textbf{o\_*} solo nel processo sincrono: oltre a separare la logica di controllo dall'aggiornamento delle uscite, questo garantisce che i segnali verso la memoria siano privi di glitch. + \item \textbf{Indirizzo anticipato:} \textbf{o\_mem\_addr} viene registrato da \textbf{next\_mem\_addr} (e non da \textbf{current\_mem\_addr}): l'indirizzo arriva così alla memoria con un ciclo di anticipo rispetto allo stato che ne consumerà il dato. Poiché la memoria ha lettura sincrona con latenza di un ciclo, questa convenzione permette a ogni stato di richiedere una lettura e allo stato successivo (dopo un solo ciclo "cuscinetto") di usarne il risultato. + \end{itemize} + \newpage + + \subsection{Processo combinatorio} + Questo è il processo principale del modulo hardware: esso è responsabile della logica interna e della gestione degli stati FSM.\\ + Vengono di seguito analizzati tutti gli stati presenti. + + + \begin{lstlisting} + type state_type is ( + S_IDLE, S_RESET, S_DONE, + + S_00_READ, S_00_WAIT, S_00_CHECK, S_00_GO_NEXT, + + S_01_CHECK_NUMBER, S_01_WAIT, S_01_WRITE, S_01_CHECK_END, S_01_COPY, S_01_GO_NEXT, S_01_WAIT_FOR_COUNT, + + S_10_PLACE_AT_START, S_10_WAIT_FOR_CHECK, S_10_CHECK_ID, S_10_WAIT, S_10_COMPARE, S_10_GO_NEXT, S_10_UPDATE_COUNT, S_10_WAIT_FOR_COUNT, + + S_11_UPDATE_COUNT, S_11_WAIT_FOR_COUNT + ); + \end{lstlisting} + + \subsubsection{Stati di gestione del protocollo} + \begin{itemize} + \item \textbf{S\_IDLE:} Stato di attesa. Quando viene rilevato il segnale \textbf{START=1}, viene avviata l'operazione indicata dal codice \textbf{i\_op}. Al dispatch viene anche azzerato il registro \textbf{popped\_id}, così \textbf{o\_task\_id} varrà 0 per ogni operazione diversa da una rimozione andata a buon fine. + \item \textbf{S\_RESET:} Stato di reset. Imposta il contatore nella prima cella di memoria a 0, invalidando tutte le altre, mentre \textbf{DONE} rimane a 1 come richiesto dalla specifica. + \item \textbf{S\_DONE:} Alza \textbf{DONE} e lo tiene a 1 finché \textbf{START} non torna a 0, come richiesto dal protocollo di handshake. Tutte le operazioni raggiungono questo stato un ciclo dopo il proprio stato terminale: \textbf{DONE} sale quindi sempre \emph{dopo} il commit in memoria dell'ultima scrittura, e la logica esterna che campiona la memoria sul fronte di \textbf{DONE} legge dati già aggiornati. + \end{itemize} + \newpage + + \subsubsection{Operazione 00} + Questa operazione decrementa la priorità di tutti i task presenti in lista. + Se un task ha già la priorità minima \textbf{11}, questa non viene modificata. + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.4\textwidth]{DIAGRAMS/S_00_DIAGRAM.png}} + + \vspace{0.5cm} + Gli stati presenti sono 4: + \begin{itemize} + \item \textbf{S\_00\_READ:} Seleziona il primo elemento in lista + \item \textbf{S\_00\_WAIT:} Stato cuscinetto. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato + \item \textbf{S\_00\_CHECK:} Controlla se l'indirizzo selezionato è un task valido. In tal caso, se possibile, ne incrementa la priorità numerica di 1. + \item \textbf{S\_00\_GO\_NEXT:} Seleziona la cella di memoria successiva + \end{itemize} + \newpage + + \subsubsection{Operazione 01} + Questa operazione rimuove il primo task della lista e sposta in alto tutti i task sottostanti. + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_01_DIAGRAM.png}} + + \vspace{0.5cm} + Gli stati presenti sono 7: + \begin{itemize} + \item \textbf{S\_01\_CHECK\_NUMBER:} Se non ci sono task termina subito (\textbf{o\_task\_id} resterà \textbf{000000}). Altrimenti avvia la lettura del primo task. + \item \textbf{S\_01\_WAIT:} Stato cuscinetto. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato + \item \textbf{S\_01\_WRITE:} Salva l'ID del primo task nel registro \textbf{popped\_id} (verrà presentato su \textbf{o\_task\_id} in \textbf{S\_DONE}) e avvia la lettura del task successivo. + \item \textbf{S\_01\_CHECK\_END:} Controlla se ha raggiunto la fine della lista. In tal caso scrive nella prima cella il valore del contatore decrementato di uno. + \item \textbf{S\_01\_COPY:} Copia il contenuto della cella \textbf{n+1} dentro alla cella \textbf{n}. + \item \textbf{S\_01\_GO\_NEXT:} Passa al task successivo. + \item \textbf{S\_01\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + \end{itemize} + \newpage + + \subsubsection{Operazione 10} + Questa operazione inserisce un nuovo task nella posizione corretta secondo la sua priorità, in coda ai task di pari priorità. L'operazione è divisa in due fasi: + \begin{enumerate} + \item \textbf{Scansione duplicati:} la lista viene percorsa dall'ultimo task verso il primo; se viene trovato un task con lo stesso ID, l'inserimento viene ignorato (la specifica vieta la presenza di due task con lo stesso ID). Vengono inoltre scartate immediatamente le richieste con ID = 0, valore riservato dalla specifica come condizione di errore. + \item \textbf{Inserimento dal fondo:} partendo dall'ultimo task e salendo, viene controllata la priorità del task corrente. Se questa risulta numericamente maggiore (gerarchicamente inferiore) rispetto a quella del task da inserire, la cella viene copiata in quella sottostante e il confronto prosegue verso l'alto. Contrariamente, se la priorità dovesse risultare minore o uguale, il nuovo task viene inserito nella cella sottostante: il confronto "minore o uguale" è ciò che colloca il nuovo task \emph{dopo} quelli di pari priorità, garantendo l'ordine FIFO richiesto. + \end{enumerate} + + Si fa notare come il caso limite di lista piena non può verificarsi: con ID a 6 bit e ID = 0 escluso esistono al più 63 task distinti, e un 64-esimo inserimento sarebbe necessariamente un duplicato, quindi ignorato dalla fase di scansione. + + \vspace{0.5cm} + Di seguito viene illustrato un esempio di inserimento del task \textbf{011110 01}. + + Nota: la scansione iniziale per identificare i duplicati viene ignorata nell'esempio. + + \begin{itemize} + + \item L’ultimo task presenta una priorità gerarchicamente minore, di conseguenza viene copiato nella cella sottostante. + + \includegraphics[width=0.7\textwidth]{S_10_EXAMPLE/S_10_ITERATION1.png} + + \item Si passa quindi al task soprastante. Anche questo presenta una priorità inferiore e viene pertanto copiato nella cella sottostante. + + \includegraphics[width=0.7\textwidth]{S_10_EXAMPLE/S_10_ITERATION2.png} + + \item Il task nella cella 1 presenta invece una priorità maggiore o uguale: il nuovo task viene quindi inserito nella cella sottostante. + + \includegraphics[width=0.87\textwidth]{S_10_EXAMPLE/S_10_ITERATION3.png} + + \item Infine, viene aggiornato il contatore. + + \end{itemize} + \newpage + + + + + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_10_DIAGRAM.png}} + \vspace{0.5cm} + Gli stati presenti sono 8: + \begin{itemize} + \item \textbf{S\_10\_PLACE\_AT\_START:} Scarta le richieste con ID = 0 e avvia la scansione duplicati dall'ultimo task della lista. + + \item \textbf{S\_10\_WAIT\_FOR\_CHECK:} Stato cuscinetto della fase di scansione. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato. + + \item \textbf{S\_10\_CHECK\_ID:} Confronta l'ID del task letto con quello da inserire. Se coincidono, l'operazione termina senza modifiche; se la scansione ha raggiunto la cima della lista, rilegge l'ultimo task e passa alla fase di inserimento; altrimenti prosegue la scansione verso l'alto. + + \item \textbf{S\_10\_WAIT:} Stato cuscinetto della fase di inserimento. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato. + + \item \textbf{S\_10\_COMPARE:} Verifica la condizione di inserimento del nuovo task. + Se tutta la lista è stata scorsa (o era vuota), il nuovo task viene scritto in testa. + In caso contrario, se il task da inserire presenta una priorità numericamente maggiore o uguale rispetto al task corrente, viene scritto nella cella sottostante; + se invece presenta una priorità numericamente minore, è il task corrente a venire copiato nella cella sottostante. + + \item \textbf{S\_10\_GO\_NEXT:} Seleziona il task precedente nella lista, da confrontare al giro successivo. + + \item \textbf{S\_10\_UPDATE\_COUNT:} Aggiorna il contatore con il numero totale di task presenti nella lista. + + \item \textbf{S\_10\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + + \end{itemize} + \newpage + + + \subsubsection{Operazione 11} + Questa operazione svuota completamente la lista impostando il contatore dei task a 0 (non è necessario resettare tutti i valori nella memoria). + + \vspace{0.5cm} + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_11_DIAGRAM.png}} + \vspace{0.5cm} + Gli stati presenti sono 2: + \begin{itemize} + \item \textbf{S\_11\_UPDATE\_COUNT:} Imposta il contatore a 0. + + \item \textbf{S\_11\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + + \end{itemize} + + + + + + + + + \newpage + \section{Risultati sperimentali} + \subsection{Report di sintesi} + \subsubsection{Risorse utilizzate} + La seguente tabella mostra le risorse hardware occupate dal design sul dispositivo target Artix-7 FPGA xc7a200tfbg484-1. L'utilizzo è estremamente contenuto: le Slice LUT occupano solo lo 0.13\% delle risorse disponibili e i registri lo 0.03\%, confermando che il modulo è decisamente leggero. Inoltre, non è stato inferito alcun latch: tutti gli elementi di memoria sono flip-flop, a conferma che il processo combinatorio assegna un valore di default a ogni segnale in ogni ramo. + + \begin{table}[H] + \centering + \caption{Risorse utilizzate -- Slice Logic} + \label{tab:utilization} + \begin{tabular}{lrrrrr} + \toprule + \textbf{Site Type} & \textbf{Used} & \textbf{Fixed} & \textbf{Prohibited} & \textbf{Available} & \textbf{Util\%} \\ + \midrule + Slice LUTs* & 181 & 0 & 0 & 134600 & 0.13 \\ + \quad LUT as Logic & 181 & 0 & 0 & 134600 & 0.13 \\ + \quad LUT as Memory & 0 & 0 & 0 & 46200 & 0.00 \\ + Slice Registers & 71 & 0 & 0 & 269200 & 0.03 \\ + \quad Register as Flip Flop & 71 & 0 & 0 & 269200 & 0.03 \\ + \quad Register as Latch & 0 & 0 & 0 & 269200 & 0.00 \\ + F7 Muxes & 0 & 0 & 0 & 67300 & 0.00 \\ + F8 Muxes & 0 & 0 & 0 & 33650 & 0.00 \\ + Unique Control Sets & 6 & -- & 0 & 33650 & 0.02 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + \subsubsection{FSM codificata} + La tabella riporta la codifica degli stati FSM generata automaticamente dal tool di sintesi. Sono presenti in totale 24 stati. Vivado ha scelto una codifica \textbf{one-hot} (un flip-flop per stato, 24 bit complessivi), tipica sulle FPGA: aumenta il numero di registri, risorsa abbondante, ma minimizza la logica di decodifica dello stato e ne accorcia i percorsi combinatori. Per compattezza la tabella riporta, per ogni stato, l'indice del bit attivo della codifica one-hot e la codifica sequenziale a 5 bit di partenza. + \begin{table}[H] + \caption{FSM -- Codifica degli stati} + \label{tab:fsm-encoding} + \centering + \begin{tabular}{lcc} + \toprule + \textbf{Stato} & \textbf{One-hot (bit attivo)} & \textbf{Previous Encoding} \\ + \midrule + \texttt{s\_reset} & 0 & 00001 \\ + \texttt{s\_done} & 1 & 00010 \\ + \texttt{s\_idle} & 2 & 00000 \\ + \texttt{s\_00\_read} & 3 & 00011 \\ + \texttt{s\_00\_wait} & 4 & 00100 \\ + \texttt{s\_00\_check} & 5 & 00101 \\ + \texttt{s\_00\_go\_next} & 6 & 00110 \\ + \texttt{s\_01\_check\_number} & 7 & 00111 \\ + \texttt{s\_01\_wait} & 8 & 01000 \\ + \texttt{s\_01\_write} & 9 & 01001 \\ + \texttt{s\_01\_check\_end} & 10 & 01010 \\ + \texttt{s\_01\_wait\_for\_count}& 11 & 01101 \\ + \texttt{s\_01\_copy} & 12 & 01011 \\ + \texttt{s\_01\_go\_next} & 13 & 01100 \\ + \texttt{s\_10\_place\_at\_start}& 14 & 01110 \\ + \texttt{s\_10\_wait\_for\_check}& 15 & 01111 \\ + \texttt{s\_10\_check\_id} & 16 & 10000 \\ + \texttt{s\_10\_wait} & 17 & 10001 \\ + \texttt{s\_10\_compare} & 18 & 10010 \\ + \texttt{s\_10\_update\_count} & 19 & 10100 \\ + \texttt{s\_10\_wait\_for\_count}& 20 & 10101 \\ + \texttt{s\_10\_go\_next} & 21 & 10011 \\ + \texttt{s\_11\_update\_count} & 22 & 10110 \\ + \texttt{s\_11\_wait\_for\_count}& 23 & 10111 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + + \subsubsection{Statistiche RTL} + La tabella dettaglia i componenti RTL inferiti dal tool di sintesi a partire dal codice VHDL. Sono presenti sommatori a 16, 9 e 8 bit per l'aritmetica su indirizzi, priorità e contatore. I registri a 16, 8, 6 e 1 bit corrispondono ai segnali interni e alle uscite registrate del design. I multiplexer a 24 ingressi riflettono la selezione tra i 24 stati della FSM (quelli a 24 bit operano sulla codifica one-hot dello stato). + \begin{table}[H] + \caption{Statistiche RTL -- Componenti} + \label{tab:rtl-stats} + \centering + \small + \begin{tabular}{rlrl} + \toprule + \textbf{Ingressi} & \textbf{Bit} & \textbf{Tipo} & \textbf{Quantità} \\ + \midrule + \multicolumn{4}{l}{\textit{Adders}} \\ + 2 & 16 bit & Adder & 4 \\ + 2 & 9 bit & Adder & 1 \\ + 2 & 8 bit & Adder & 3 \\ + \midrule + \multicolumn{4}{l}{\textit{Registers}} \\ + -- & 16 bit & Register & 1 \\ + -- & 8 bit & Register & 2 \\ + -- & 6 bit & Register & 2 \\ + -- & 1 bit & Register & 3 \\ + \midrule + \multicolumn{4}{l}{\textit{Muxes}} \\ + 24 & 24 bit & Mux & 1 \\ + 4 & 24 bit & Mux & 1 \\ + 2 & 24 bit & Mux & 7 \\ + 2 & 16 bit & Mux & 3 \\ + 24 & 16 bit & Mux & 1 \\ + 2 & 8 bit & Mux & 4 \\ + 24 & 8 bit & Mux & 2 \\ + 2 & 6 bit & Mux & 1 \\ + 24 & 6 bit & Mux & 2 \\ + 2 & 1 bit & Mux & 1 \\ + 24 & 1 bit & Mux & 6 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + + \subsubsection{Timing} + La specifica richiede che il progetto funzioni con un periodo di clock di almeno 20 ns. Il requisito è stato verificato in sintesi applicando il vincolo \texttt{create\_clock -period 20.000} sul segnale \texttt{i\_clk}: + + \begin{table}[H] + \centering + \caption{Design Timing Summary (periodo di clock 20 ns)} + \label{tab:timing} + \begin{tabular}{lrr} + \toprule + \textbf{Metrica} & \textbf{Slack (ns)} & \textbf{Endpoint in violazione} \\ + \midrule + Worst Negative Slack (setup, WNS) & $+14.786$ & 0 / 114 \\ + Worst Hold Slack (WHS) & $+0.149$ & 0 / 114 \\ + Worst Pulse Width Slack (WPWS) & $+9.500$ & 0 / 72 \\ + \bottomrule + \end{tabular} + \end{table} + + Lo slack di setup ampiamente positivo indica che il percorso critico è di circa 5.2 ns: il modulo rispetta il vincolo dei 20 ns con un margine di quasi 4 volte. La correttezza funzionale del circuito sintetizzato è inoltre confermata dalla simulazione post-sintesi (functional) di tutti i test bench descritti nella sezione successiva. + \newpage + + \subsection{Report di simulazioni} + \subsubsection{Test bench 1} + Il test bench di esempio fornito dal docente copre le operazioni base quali reset, inserimento in lista, rimozione dalla lista, decremento di priorità e svuotamento della lista. + + Seppur non vengano coperti molti casi limite, questo test bench ci offre la possibilità di analizzare facilmente i tempi di esecuzione delle singole operazioni. + Le 10 operazioni, infatti, vengono eseguite correttamente in 2540 ns.\\ + In particolar modo, le latenze in cicli di clock (periodo 20 ns), con \textbf{N} task presenti in lista e \textbf{k} task spostati, sono le seguenti: + \begin{itemize} + \item \textbf{OP 00}: $(4 + 3N) \cdot 20\,$ns + \item \textbf{OP 01}: $(6 + 3k) \cdot 20\,$ns, con $k = N - 1$; lista vuota: $2 \cdot 20\,$ns + \item \textbf{OP 10}: $(6 + 2\max(N,1) + 3k) \cdot 20\,$ns + \item \textbf{OP 11}: $3 \cdot 20\,$ns + \end{itemize} + + Nota: nell'operazione \textbf{10} il termine $2\max(N,1)$ è il costo della scansione duplicati, che percorre sempre l'intera lista, mentre $3k$ è il costo degli spostamenti, con $k$ compreso tra 0 (inserimento in fondo) e $N$ (inserimento in testa). + Per caratterizzare il comportamento medio, si considera una distribuzione delle priorità equiprobabile: $E[T] = \left(6 + \frac{25}{8}N\right) \cdot 20\,$ns. + + Tutte le formule sono state verificate al ciclo esatto da un test bench dedicato (par. 3.2.3). + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/RESET.png} + \caption{Operazione di reset.} + \label{fig:reset} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/INSERIMENTO_VUOTA.png} + \caption{Operazione di inserimento in lista vuota.} + \label{fig:insert_empty} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/SVUOTA.png} + \caption{Operazione di svuotamento della lista.} + \label{fig:empty} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/INSERIMENTO_PIENA.png} + \caption{Operazione di inserimento in lista popolata.} + \label{fig:insert_full} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/RIMOZIONE.png} + \caption{Operazione di rimozione di un task.} + \label{fig:remove} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/DECREMENTA.png} + \caption{Operazione di decremento della priorità.} + \label{fig:decrease} + \end{figure} + + + + + + + + + + + + + + + + + + + + + + \newpage + + \subsubsection{Test bench 2 (casi limite)} + Il secondo test bench è stato pensato per coprire i possibili casi limite che potrebbero presentarsi: + + \begin{table}[H] + \centering + \renewcommand{\arraystretch}{1.6} + \begin{tabular}{|m{6cm}|m{8cm}|} + \hline + \textbf{Caso testato} & \textbf{Descrizione} \\ + \hline + DONE durante il reset & DONE rimane a 1 durante reset e inizializzazione. \\ + \hline + Reset asincrono & Reset durante operazioni in corso: il modulo torna allo stato iniziale senza corrompere la memoria. \\ + \hline + Operazioni su lista vuota & Rimozione, decremento e svuotamento su lista vuota non producono scritture. La rimozione restituisce ID = 000000. \\ + \hline + Saturazione della priorità & Task già a priorità 11 non vengono modificati da ulteriori decrementi. \\ + \hline + Ordinamento e FIFO & Inserimenti con priorità diverse e tra task di pari priorità; l'ordine di estrazione è verificato con rimozioni successive. \\ + \hline + ID duplicati e ID = 0 & L'inserimento viene ignorato se l'ID è già presente o vale 0; DONE viene emesso comunque. \\ + \hline + Sequenza di stress & Inserimenti, invecchiamenti, rimozioni e svuotamento in sequenza mista. \\ + \hline + \end{tabular} + \caption*{Casi limite testati nel test bench 2} + \label{tab:testbench2} + \end{table} + + \subsubsection{Test bench 3 (latenze)} + Un terzo test bench misura, per ciascuna operazione, il numero esatto di cicli di clock che intercorrono tra il campionamento di START e l'assertion di DONE, confrontandolo con le formule di latenza riportate nel paragrafo 3.2.1. Le 15 misure (inserimenti con 0--3 spostamenti e inserimento in fondo, rimozioni con lista vuota e con 1--4 task, invecchiamenti con 0--4 task incluso il caso di saturazione completa) coincidono tutte al ciclo esatto con il valore atteso: la FSM non contiene quindi stati morti né attese superflue. + + Tutti e tre i test bench passano sia in simulazione comportamentale sia in simulazione post-sintesi functional. + + + + + + + + + + \newpage + \section{Conclusioni} + I test comportamentali e post-sintesi mostrano che il modulo funziona correttamente, rispettando la specifica. + Il componente completa l'elaborazione del test bench di esempio in 2540 ns, con un utilizzo delle risorse hardware + estremamente contenuto: le Slice LUT occupano lo 0.13\% delle risorse disponibili sul + dispositivo target Artix-7 FPGA xc7a200tfbg484-1, senza alcun latch inferito, confermando la leggerezza e la pulizia del design. Il vincolo di clock di 20 ns è rispettato con ampio margine (WNS $+14.786$ ns, percorso critico $\approx 5.2$ ns). + + In fase di progettazione ho scelto deliberatamente di adottare un numero di stati superiore allo stretto necessario, privilegiando la leggibilità rispetto all'efficienza. Questa scelta, pur garantendo la correttezza del comportamento, introduce una leggera inefficienza temporale: + accorpando o eliminando alcuni stati intermedi sarebbe possibile ridurre la latenza complessiva di qualche punto percentuale. + Ad esempio, gli stati iniziali di alcune operazioni possono essere accorpati nello stato \textbf{S\_IDLE}, all'interno del ramo di decodifica dell'operazione corrispondente. + + +\end{document} \ No newline at end of file diff --git a/progetto_reti_logiche.cache/sim/ssm.db b/progetto_reti_logiche.cache/sim/ssm.db new file mode 100644 index 0000000..f0dde68 --- /dev/null +++ b/progetto_reti_logiche.cache/sim/ssm.db @@ -0,0 +1,10 @@ +################################################################################ +# DONOT REMOVE THIS FILE +# Unified simulation database file for selected simulation model for IP +# +# File: ssm.db (Tue Mar 3 17:54:07 2026) +# +# This file is generated by the unified simulation automation and contains the +# selected simulation model information for the IP/BD instances. +# DONOT REMOVE THIS FILE +################################################################################ diff --git a/progetto_reti_logiche.cache/wt/project.wpc b/progetto_reti_logiche.cache/wt/project.wpc new file mode 100644 index 0000000..3e85024 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +6d6f64655f636f756e7465727c42617463684d6f6465:1 +6d6f64655f636f756e7465727c4755494d6f6465:39 +eof: diff --git a/progetto_reti_logiche.cache/wt/synthesis.wdf b/progetto_reti_logiche.cache/wt/synthesis.wdf new file mode 100644 index 0000000..18883a1 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/synthesis.wdf @@ -0,0 +1,52 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030746662673438342d31:00:00 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+ + + + + + + +
+ + diff --git a/progetto_reti_logiche.cache/wt/xsim.wdf b/progetto_reti_logiche.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/progetto_reti_logiche.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/progetto_reti_logiche.hw/progetto_reti_logiche.lpr b/progetto_reti_logiche.hw/progetto_reti_logiche.lpr new file mode 100644 index 0000000..04ef66e --- /dev/null +++ b/progetto_reti_logiche.hw/progetto_reti_logiche.lpr @@ -0,0 +1,7 @@ + + + + + + + diff --git a/progetto_reti_logiche.ip_user_files/README.txt b/progetto_reti_logiche.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/progetto_reti_logiche.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_26.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_26.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_27.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_27.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_28.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_28.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_29.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/.Vivado_Synthesis.queue.rst b/progetto_reti_logiche.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst b/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..4960303 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/.vivado.end.rst b/progetto_reti_logiche.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/ISEWrap.js b/progetto_reti_logiche.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/progetto_reti_logiche.runs/synth_1/ISEWrap.sh b/progetto_reti_logiche.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e085d18 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/bash + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/progetto_reti_logiche.runs/synth_1/__synthesis_is_complete__ b/progetto_reti_logiche.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/gen_run.xml b/progetto_reti_logiche.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..d43dd4b --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/gen_run.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/htr.txt b/progetto_reti_logiche.runs/synth_1/htr.txt new file mode 100644 index 0000000..f0971b4 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl diff --git a/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb b/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb new file mode 100644 index 0000000..4cb4ed4 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb @@ -0,0 +1 @@ + 6No compile time benefit to using incremental synthesis \ No newline at end of file diff --git a/progetto_reti_logiche.runs/synth_1/project.wdf b/progetto_reti_logiche.runs/synth_1/project.wdf new file mode 100644 index 0000000..1d56225 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3630353136636534303563393461656261623931373435306630653133333835:506172656e742050412070726f6a656374204944:00 +eof:2983737119 diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp new file mode 100644 index 0000000..e6a1abe Binary files /dev/null and b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp differ diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche.tcl b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.tcl new file mode 100644 index 0000000..88a3b36 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.tcl @@ -0,0 +1,107 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param general.usePosixSpawnForFork 1 +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7a200tfbg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/wt [current_project] +set_property parent.project_path /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_vhdl -library xil_defaultlib /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef project_reti_logiche.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +generate_parallel_reports -reports { "report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb" } +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds new file mode 100644 index 0000000..b83d504 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds @@ -0,0 +1,257 @@ +#----------------------------------------------------------- +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Fri Jun 12 14:52:36 2026 +# Process ID : 33507 +# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1 +# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl +# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds +# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou +# Running On : cachyos-x8664 +# Platform : cachyos +# Operating System : CachyOS +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F +# CPU Frequency : 4313.234 MHz +# CPU Physical cores : 12 +# CPU Logical cores : 20 +# Host memory : 16502 MB +# Swap memory : 16501 MB +# Total Virtual : 33003 MB +# Available Virtual : 19387 MB +#----------------------------------------------------------- +source project_reti_logiche.tcl -notrace +Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 33546 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151] +INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a200tfbg484-1 +INFO: [Device 21-403] Loading part xc7a200tfbg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + s_reset | 000000000000000000000001 | 00001 + s_done | 000000000000000000000010 | 00010 + s_idle | 000000000000000000000100 | 00000 + s_00_read | 000000000000000000001000 | 00011 + s_00_wait | 000000000000000000010000 | 00100 + s_00_check | 000000000000000000100000 | 00101 + s_00_go_next | 000000000000000001000000 | 00110 + s_01_check_number | 000000000000000010000000 | 00111 + s_01_wait | 000000000000000100000000 | 01000 + s_01_write | 000000000000001000000000 | 01001 + s_01_check_end | 000000000000010000000000 | 01010 + s_01_wait_for_count | 000000000000100000000000 | 01101 + s_01_copy | 000000000001000000000000 | 01011 + s_01_go_next | 000000000010000000000000 | 01100 + s_10_place_at_start | 000000000100000000000000 | 01110 + s_10_wait_for_check | 000000001000000000000000 | 01111 + s_10_check_id | 000000010000000000000000 | 10000 + s_10_wait | 000000100000000000000000 | 10001 + s_10_compare | 000001000000000000000000 | 10010 + s_10_update_count | 000010000000000000000000 | 10100 + s_10_wait_for_count | 000100000000000000000000 | 10101 + s_10_go_next | 001000000000000000000000 | 10011 + s_11_update_count | 010000000000000000000000 | 10110 + s_11_wait_for_count | 100000000000000000000000 | 10111 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 4 + 2 Input 9 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 2 + 6 Bit Registers := 2 + 1 Bit Registers := 3 ++---Muxes : + 24 Input 24 Bit Muxes := 1 + 4 Input 24 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 7 + 2 Input 16 Bit Muxes := 3 + 24 Input 16 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 4 + 24 Input 8 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 + 24 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 740 (col length:100) +BRAMs: 730 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 18| +|3 |LUT1 | 34| +|4 |LUT2 | 16| +|5 |LUT3 | 25| +|6 |LUT4 | 44| +|7 |LUT5 | 22| +|8 |LUT6 | 78| +|9 |FDCE | 25| +|10 |FDPE | 2| +|11 |FDRE | 44| +|12 |IBUF | 21| +|13 |OBUF | 33| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 363| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463 +INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 3d7ece1d +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026... diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.pb b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.pb new file mode 100644 index 0000000..0ffdde3 Binary files /dev/null and b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.pb differ diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt new file mode 100644 index 0000000..18b9943 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt @@ -0,0 +1,188 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +| Date : Fri Jun 12 14:52:50 2026 +| Host : cachyos-x8664 running 64-bit CachyOS +| Command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +| Design : project_reti_logiche +| Device : xc7a200tfbg484-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 181 | 0 | 0 | 134600 | 0.13 | +| LUT as Logic | 181 | 0 | 0 | 134600 | 0.13 | +| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 | +| Slice Registers | 71 | 0 | 0 | 269200 | 0.03 | +| Register as Flip Flop | 71 | 0 | 0 | 269200 | 0.03 | +| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 | +| Unique Control Sets | 6 | | 0 | 33650 | 0.02 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances +** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 2 | Yes | - | Set | +| 25 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 44 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 730 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 740 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 54 | 0 | 0 | 285 | 18.95 | +| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 0 | 40 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 78 | LUT | +| LUT4 | 44 | LUT | +| FDRE | 44 | Flop & Latch | +| LUT1 | 34 | LUT | +| OBUF | 33 | IO | +| LUT3 | 25 | LUT | +| FDCE | 25 | Flop & Latch | +| LUT5 | 22 | LUT | +| IBUF | 21 | IO | +| CARRY4 | 18 | CarryLogic | +| LUT2 | 16 | LUT | +| FDPE | 2 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/progetto_reti_logiche.runs/synth_1/rundef.js b/progetto_reti_logiche.runs/synth_1/rundef.js new file mode 100644 index 0000000..d5d6754 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;"; +} else { + PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/progetto_reti_logiche.runs/synth_1/runme.bat b/progetto_reti_logiche.runs/synth_1/runme.bat new file mode 100644 index 0000000..60fbf14 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/progetto_reti_logiche.runs/synth_1/runme.log b/progetto_reti_logiche.runs/synth_1/runme.log new file mode 100644 index 0000000..f2d80ce --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.log @@ -0,0 +1,247 @@ + +*** Running vivado + with args -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl + + +****** Vivado v2025.2 (64-bit) + **** SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 + **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 + **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 + **** Start of session at: Fri Jun 12 14:52:36 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +source project_reti_logiche.tcl -notrace +Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 33546 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151] +INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a200tfbg484-1 +INFO: [Device 21-403] Loading part xc7a200tfbg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + s_reset | 000000000000000000000001 | 00001 + s_done | 000000000000000000000010 | 00010 + s_idle | 000000000000000000000100 | 00000 + s_00_read | 000000000000000000001000 | 00011 + s_00_wait | 000000000000000000010000 | 00100 + s_00_check | 000000000000000000100000 | 00101 + s_00_go_next | 000000000000000001000000 | 00110 + s_01_check_number | 000000000000000010000000 | 00111 + s_01_wait | 000000000000000100000000 | 01000 + s_01_write | 000000000000001000000000 | 01001 + s_01_check_end | 000000000000010000000000 | 01010 + s_01_wait_for_count | 000000000000100000000000 | 01101 + s_01_copy | 000000000001000000000000 | 01011 + s_01_go_next | 000000000010000000000000 | 01100 + s_10_place_at_start | 000000000100000000000000 | 01110 + s_10_wait_for_check | 000000001000000000000000 | 01111 + s_10_check_id | 000000010000000000000000 | 10000 + s_10_wait | 000000100000000000000000 | 10001 + s_10_compare | 000001000000000000000000 | 10010 + s_10_update_count | 000010000000000000000000 | 10100 + s_10_wait_for_count | 000100000000000000000000 | 10101 + s_10_go_next | 001000000000000000000000 | 10011 + s_11_update_count | 010000000000000000000000 | 10110 + s_11_wait_for_count | 100000000000000000000000 | 10111 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 4 + 2 Input 9 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 2 + 6 Bit Registers := 2 + 1 Bit Registers := 3 ++---Muxes : + 24 Input 24 Bit Muxes := 1 + 4 Input 24 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 7 + 2 Input 16 Bit Muxes := 3 + 24 Input 16 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 4 + 24 Input 8 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 + 24 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 740 (col length:100) +BRAMs: 730 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 18| +|3 |LUT1 | 34| +|4 |LUT2 | 16| +|5 |LUT3 | 25| +|6 |LUT4 | 44| +|7 |LUT5 | 22| +|8 |LUT6 | 78| +|9 |FDCE | 25| +|10 |FDPE | 2| +|11 |FDRE | 44| +|12 |IBUF | 21| +|13 |OBUF | 33| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 363| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463 +INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 3d7ece1d +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026... diff --git a/progetto_reti_logiche.runs/synth_1/runme.sh b/progetto_reti_logiche.runs/synth_1/runme.sh new file mode 100755 index 0000000..646b7fc --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin +else + PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl diff --git a/progetto_reti_logiche.runs/synth_1/vivado.jou b/progetto_reti_logiche.runs/synth_1/vivado.jou new file mode 100644 index 0000000..bbc0a51 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Fri Jun 12 14:52:36 2026 +# Process ID : 33507 +# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1 +# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl +# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds +# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou +# Running On : cachyos-x8664 +# Platform : cachyos +# Operating System : CachyOS +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F +# CPU Frequency : 4313.234 MHz +# CPU Physical cores : 12 +# CPU Logical cores : 20 +# Host memory : 16502 MB +# Swap memory : 16501 MB +# Total Virtual : 33003 MB +# Available Virtual : 19387 MB +#----------------------------------------------------------- +source project_reti_logiche.tcl -notrace diff --git a/progetto_reti_logiche.runs/synth_1/vivado.pb b/progetto_reti_logiche.runs/synth_1/vivado.pb new file mode 100644 index 0000000..2e54844 Binary files /dev/null and b/progetto_reti_logiche.runs/synth_1/vivado.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.log new file mode 100644 index 0000000..633c98e --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'project_reti_logiche' diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.sh b/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.sh new file mode 100755 index 0000000..cdd45a3 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/compile.sh @@ -0,0 +1,28 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : compile.sh +# Simulator : AMD Vivado Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Fri Jun 12 15:55:43 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# compile VHDL design sources +echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj" +xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee compile.log + +echo "Waiting for jobs to finish..." +echo "No pending jobs, compilation finished." diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..2f60c4a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator v2025.2 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture fsm of entity xil_defaultlib.project_reti_logiche [project_reti_logiche_default] +Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge +Built simulation snapshot project_tb_edge_behav diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh new file mode 100755 index 0000000..63b062f --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Fri Jun 12 15:55:44 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log + diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log new file mode 100644 index 0000000..cff1490 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log @@ -0,0 +1,24 @@ +# +# An unexpected error has occurred (11) Segmentation fault +# +Stack: +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7fd51747195c] +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7fd51747242e] +/usr/lib/libc.so.6(+0x3e2d0) [0x7fd556e4d2d0] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7fd52434ebcb] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7fd52434f1e1] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector >&) const+0x6f) [0x7fd52436a6ff] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0xb7) [0x7fd5243c2cd7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0x128) [0x7fd5243c60c8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7fd5243a9596] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7fd5243a3f64] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7fd5243f1b2f] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7fd5243f1ca4] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7fd5242391a7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7fd52423922c] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7fd52423a8e8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7fd5243f137e] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7fd5244037da] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7fd524403c62] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7fd5242050dc] +[0x7fd506f7a1ea] diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb new file mode 100644 index 0000000..ecb626c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb new file mode 100644 index 0000000..4f79ae6 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge.tcl new file mode 100644 index 0000000..fe47dd3 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run all diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb new file mode 100644 index 0000000..83efe52 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_vhdl.prj b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_vhdl.prj new file mode 100644 index 0000000..72f258c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_vhdl.prj @@ -0,0 +1,7 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" \ +"../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \ + +# Do not sort compile order +nosort diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb new file mode 100644 index 0000000..fc4bb91 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.log new file mode 100644 index 0000000..1d3f1ed --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.log @@ -0,0 +1,147 @@ +Time resolution is 1 ps +Note: === GRUPPO 0: Reset === +Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.0 OK: reset base +Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.1 OK: reset asincrono durante operazione +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 1: Inserimento === +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.0 OK: insert in lista vuota +Time: 3670 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.1 OK: insert con priorità massima in testa +Time: 6010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.2 OK: insert con priorità minima in fondo +Time: 8230 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali +Time: 10450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo +Time: 12950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.5 OK: insert con ID duplicato ignorato +Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 2: Rimozione === +Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0 +Time: 16990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto +Time: 18930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato +Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 3: Decremento priorità === +Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.0 OK: decremento su lista vuota +Time: 23130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.1 OK: saturazione a priorità 3 +Time: 25350 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica +Time: 27870 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino) +Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 4: Svuota lista === +Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.0 OK: svuota lista popolata +Time: 33050 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.1 OK: svuota lista già vuota +Time: 34730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0 +Time: 36690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto +Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 5: Sequenze composite === +Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto +Time: 41490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.1 OK: ordinamento completo con priorità miste +Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 6: Rimozione multipla e ordinamento === +Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota +Time: 48310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1 +Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 7: Decremento ripetuto === +Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3 +Time: 53430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente +Time: 57010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.1 OK: decremento su lista con un solo task +Time: 59330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota +Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 8: Insert dopo rimozione e casi limite === +Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto +Time: 64950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato +Time: 67830 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato +Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 9: o_task_id per OP diverso da 01 === +Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1 +Time: 72490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1 +Time: 74450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1 +Time: 76330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1 +Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 10: Protocollo, reset avanzato, stress === +Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset +Time: 79750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert) +Time: 92030 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato +Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 11: Insert con ID=0 === +Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato +Time: 96290 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato +Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 12: Capacita' massima 63 task === +Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata +Time: 231450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati +Time: 235970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.2 OK: drain di 63 task nell'ordine atteso +Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 13: Stale memory e duplicati ai bordi === +Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.0 OK: re-insert di ID appena rimosso +Time: 365710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.1 OK: duplicato in prima posizione ignorato +Time: 368130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.2 OK: duplicato in ultima posizione ignorato +Time: 368250 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.3 OK: re-insert stesso ID dopo clear +Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 14: Reset asincrono avanzato === +Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.0 OK: reset a meta' shift di OP=01 +Time: 373150 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.1 OK: reset durante la scrittura del count +Time: 375930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.2 OK: reset durante OP=00 +Time: 378470 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.3 OK: reset mentre DONE=1 +Time: 380550 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.4 OK: reset corto non allineato +Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 15: START lento dopo DONE=1 === +Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.0 OK: nessun doppio pop con START lento +Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.1 OK: nessun doppio age con START lento +Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.2 OK: insert con START tenuto 2 cicli extra +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: ====================================== + Tutti i test edge case sono PASSATI +====================================== +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616 +INFO: xsimkernel Simulation Memory Usage: 291592 KB (Peak: 337672 KB), Simulation CPU Usage: 710 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh new file mode 100755 index 0000000..113c34b --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Fri Jun 12 15:55:46 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log" +xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log + diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..98e6892 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/Compile_Options.txt new file mode 100644 index 0000000..063403c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_reti_logiche_behav" "xil_defaultlib.project_reti_logiche" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..db6a2fc Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.c new file mode 100644 index 0000000..98f96bd --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_26(char*, char *); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[4] = {(funcp)execute_26, (funcp)execute_27, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 4; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc", (void **)funcTab, 4); + iki_vhdl_file_variable_register(dp + 9192); + iki_vhdl_file_variable_register(dp + 9248); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_reti_logiche_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..86cadfd Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.dbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.dbg new file mode 100644 index 0000000..fead99f Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.mem b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.mem new file mode 100644 index 0000000..cdb952a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.reloc b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.reloc new file mode 100644 index 0000000..8b9749d Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rlx b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rlx new file mode 100644 index 0000000..430b379 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 13885744666178239796 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_reti_logiche_behav xil_defaultlib.project_reti_logiche" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_reti_logiche_behav/xsimk\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o\" -L\"/opt/vivado/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rtti b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rtti new file mode 100644 index 0000000..f295db5 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.svtype b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.svtype new file mode 100644 index 0000000..6dc1deb Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.type b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.type new file mode 100644 index 0000000..ae5aab5 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.version b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.xdbg new file mode 100644 index 0000000..a125b88 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimSettings.ini new file mode 100644 index 0000000..e940291 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=173 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=159 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimk b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimk new file mode 100644 index 0000000..51d6e6f Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log new file mode 100644 index 0000000..ebacc77 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_reti_logiche_behav/xsimk -simmode gui -wdb project_reti_logiche_behav.wdb -simrunnum 0 -socket 60931 +Design successfully loaded +Design Loading Memory Usage: 196484 KB (Peak: 196604 KB) +Design Loading CPU Usage: 750 ms +Simulation completed +Simulation Memory Usage: 278220 KB (Peak: 335752 KB) +Simulation CPU Usage: 770 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..f100233 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_behav" "xil_defaultlib.project_tb" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..82742bd Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..2bf8d8a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 9; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_behav/xsim.reloc", (void **)funcTab, 9); + iki_vhdl_file_variable_register(dp + 562288); + iki_vhdl_file_variable_register(dp + 562344); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..5b60d60 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.dbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.dbg new file mode 100644 index 0000000..843c2f0 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.mem b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.mem new file mode 100644 index 0000000..8232315 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.reloc b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.reloc new file mode 100644 index 0000000..8fe29ba Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rlx b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rlx new file mode 100644 index 0000000..cca0547 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 7473175962787144638 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_behav xil_defaultlib.project_tb" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_behav/xsimk\" \"xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rtti b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rtti new file mode 100644 index 0000000..65528a4 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.svtype b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.svtype new file mode 100644 index 0000000..6dc1deb Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.type b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.type new file mode 100644 index 0000000..6310699 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.version b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.xdbg new file mode 100644 index 0000000..f108f6b Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimSettings.ini new file mode 100644 index 0000000..12bac95 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=120 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=181 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimk b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimk new file mode 100755 index 0000000..e6aa17c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimkernel.log new file mode 100644 index 0000000..5ffaa00 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_behav/xsimk -simmode gui -wdb project_tb_behav.wdb -simrunnum 0 -socket 39125 +Design successfully loaded +Design Loading Memory Usage: 198324 KB (Peak: 198324 KB) +Design Loading CPU Usage: 690 ms +Simulation completed +Simulation Memory Usage: 291512 KB (Peak: 337592 KB) +Simulation CPU Usage: 700 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/Compile_Options.txt new file mode 100644 index 0000000..e7c995c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_edge_behav" "xil_defaultlib.project_tb_edge" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..f2ccf13 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.c new file mode 100644 index 0000000..1b69791 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.c @@ -0,0 +1,116 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_40(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[10] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 10; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc", (void **)funcTab, 10); + iki_vhdl_file_variable_register(dp + 535048); + iki_vhdl_file_variable_register(dp + 535104); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_edge_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..c64ab7a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.dbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.dbg new file mode 100644 index 0000000..b93fe6e Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.mem b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.mem new file mode 100644 index 0000000..d5a3012 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.reloc b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.reloc new file mode 100644 index 0000000..5654ef3 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rlx b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rlx new file mode 100644 index 0000000..0b58733 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 5620043674301555198 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_behav/xsimk\" \"xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rtti b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rtti new file mode 100644 index 0000000..798728d Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.svtype b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.svtype new file mode 100644 index 0000000..6dc1deb Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.type b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.type new file mode 100644 index 0000000..97387f2 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.version b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.xdbg new file mode 100644 index 0000000..4efd2ce Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimSettings.ini new file mode 100644 index 0000000..50bf1bb --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=156 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91 +OBJECT_NAME_COLUMN_WIDTH=191 +OBJECT_VALUE_COLUMN_WIDTH=1024 +OBJECT_DATA_TYPE_COLUMN_WIDTH=76 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimk b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimk new file mode 100755 index 0000000..face02d Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log new file mode 100644 index 0000000..c19589a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_edge_behav/xsimk -simmode gui -wdb project_tb_edge_behav.wdb -simrunnum 0 -socket 59621 +Design successfully loaded +Design Loading Memory Usage: 198404 KB (Peak: 198404 KB) +Design Loading CPU Usage: 680 ms +Simulation completed +Simulation Memory Usage: 291592 KB (Peak: 337672 KB) +Simulation CPU Usage: 710 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt new file mode 100644 index 0000000..43596fa --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_timing_behav" "xil_defaultlib.project_tb_timing" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..f5ed70a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.c new file mode 100644 index 0000000..a95fd1a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 9; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc", (void **)funcTab, 9); + iki_vhdl_file_variable_register(dp + 534752); + iki_vhdl_file_variable_register(dp + 534808); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_timing_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_timing_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_timing_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..daae89e Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.dbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.dbg new file mode 100644 index 0000000..36aef2b Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.mem b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.mem new file mode 100644 index 0000000..9ede051 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.reloc b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.reloc new file mode 100644 index 0000000..07141c3 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rlx b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rlx new file mode 100644 index 0000000..b3877d0 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6692423544243212696 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_timing_behav xil_defaultlib.project_tb_timing" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_timing_behav/xsimk\" \"xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rtti b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rtti new file mode 100644 index 0000000..15d16c9 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.svtype b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.svtype new file mode 100644 index 0000000..6dc1deb Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.type b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.type new file mode 100644 index 0000000..42b6e96 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.version b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.xdbg new file mode 100644 index 0000000..05a7799 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimSettings.ini new file mode 100644 index 0000000..f5861df --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=168 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91 +OBJECT_NAME_COLUMN_WIDTH=191 +OBJECT_VALUE_COLUMN_WIDTH=5823 +OBJECT_DATA_TYPE_COLUMN_WIDTH=96 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimk b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimk new file mode 100755 index 0000000..724bbf6 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimkernel.log new file mode 100644 index 0000000..c1bdfa9 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_timing_behav/xsimk -simmode gui -wdb project_tb_timing_behav.wdb -simrunnum 0 -socket 42147 +Design successfully loaded +Design Loading Memory Usage: 198300 KB (Peak: 198300 KB) +Design Loading CPU Usage: 700 ms +Simulation completed +Simulation Memory Usage: 291488 KB (Peak: 337568 KB) +Simulation CPU Usage: 720 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.vdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.vdb new file mode 100644 index 0000000..bd63e91 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb.vdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb.vdb new file mode 100644 index 0000000..582dbf5 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb new file mode 100644 index 0000000..bed12dc Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb new file mode 100644 index 0000000..67ab537 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..905adb4 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.7 +2020.2 +Nov 14 2025 +12:36:23 +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd,1781272532,vhdl,,,,project_reti_logiche,,,,,,,, diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.ini b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.log new file mode 100644 index 0000000..633c98e --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'project_reti_logiche' diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.pb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.pb new file mode 100644 index 0000000..b9bab86 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.log new file mode 100644 index 0000000..3cd0469 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.log @@ -0,0 +1,3 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_reti_logiche +INFO: [VRFC 10-311] analyzing module glbl diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.sh b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.sh new file mode 100755 index 0000000..45ba697 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.sh @@ -0,0 +1,32 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : compile.sh +# Simulator : AMD Vivado Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Fri Jun 12 15:48:15 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# compile Verilog/System Verilog design sources +echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj" +xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log + +# compile VHDL design sources +echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj" +xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log + +echo "Waiting for jobs to finish..." +echo "No pending jobs, compilation finished." diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log new file mode 100644 index 0000000..81bee70 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log @@ -0,0 +1,36 @@ +Vivado Simulator v2025.2 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling package vl.vl_types +Compiling module xil_defaultlib.glbl +Compiling module unisims_ver.x_lut2_mux4 +Compiling module unisims_ver.LUT2 +Compiling module unisims_ver.LUT4 +Compiling module unisims_ver.LUT5 +Compiling module unisims_ver.x_lut1_mux2 +Compiling module unisims_ver.LUT1 +Compiling module unisims_ver.x_lut3_mux8 +Compiling module unisims_ver.LUT3 +Compiling module unisims_ver.LUT6 +Compiling module unisims_ver.FDPE_default +Compiling module unisims_ver.FDCE_default +Compiling module unisims_ver.CARRY4 +Compiling module unisims_ver.FDRE_default +Compiling module unisims_ver.BUFG +Compiling module unisims_ver.IBUF +Compiling module unisims_ver.OBUF +Compiling module xil_defaultlib.project_reti_logiche +Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge +Built simulation snapshot project_tb_edge_func_synth diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh new file mode 100755 index 0000000..8c6335f --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Fri Jun 12 15:48:17 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log new file mode 100644 index 0000000..b83a9b4 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log @@ -0,0 +1,24 @@ +# +# An unexpected error has occurred (11) Segmentation fault +# +Stack: +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7ff9b8e7195c] +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7ff9b8e7242e] +/usr/lib/libc.so.6(+0x3e2d0) [0x7ff9f884d2d0] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7ff9c5d4ebcb] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7ff9c5d4f1e1] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector >&) const+0x6f) [0x7ff9c5d6a6ff] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0xb7) [0x7ff9c5dc2cd7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0x128) [0x7ff9c5dc60c8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7ff9c5da9596] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7ff9c5da3f64] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7ff9c5df1b2f] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7ff9c5df1ca4] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7ff9c5c391a7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7ff9c5c3922c] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7ff9c5c3a8e8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7ff9c5df137e] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7ff9c5e037da] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7ff9c5e03c62] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7ff9c5c050dc] +[0x7ff9a937ac6a] diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl new file mode 100644 index 0000000..fe47dd3 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run all diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v new file mode 100644 index 0000000..0af6440 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v @@ -0,0 +1,3225 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Fri Jun 12 15:48:15 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode funcsim -nolib -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_4_n_0 ; + wire \FSM_onehot_state[17]_i_5_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[21]_i_7_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire \current_mem_addr[0]_i_10_n_0 ; + wire \current_mem_addr[0]_i_11_n_0 ; + wire \current_mem_addr[0]_i_1_n_0 ; + wire \current_mem_addr[0]_i_2_n_0 ; + wire \current_mem_addr[0]_i_3_n_0 ; + wire \current_mem_addr[0]_i_4_n_0 ; + wire \current_mem_addr[0]_i_5_n_0 ; + wire \current_mem_addr[0]_i_6_n_0 ; + wire \current_mem_addr[0]_i_7_n_0 ; + wire \current_mem_addr[0]_i_8_n_0 ; + wire \current_mem_addr[0]_i_9_n_0 ; + wire \current_mem_addr[10]_i_1_n_0 ; + wire \current_mem_addr[10]_i_2_n_0 ; + wire \current_mem_addr[10]_i_3_n_0 ; + wire \current_mem_addr[10]_i_4_n_0 ; + wire \current_mem_addr[11]_i_10_n_0 ; + wire \current_mem_addr[11]_i_1_n_0 ; + wire \current_mem_addr[11]_i_2_n_0 ; + wire \current_mem_addr[11]_i_3_n_0 ; + wire \current_mem_addr[11]_i_4_n_0 ; + wire \current_mem_addr[11]_i_7_n_0 ; + wire \current_mem_addr[11]_i_8_n_0 ; + wire \current_mem_addr[11]_i_9_n_0 ; + wire \current_mem_addr[12]_i_1_n_0 ; + wire \current_mem_addr[12]_i_2_n_0 ; + wire \current_mem_addr[12]_i_3_n_0 ; + wire \current_mem_addr[12]_i_4_n_0 ; + wire \current_mem_addr[13]_i_1_n_0 ; + wire \current_mem_addr[13]_i_2_n_0 ; + wire \current_mem_addr[13]_i_3_n_0 ; + wire \current_mem_addr[13]_i_4_n_0 ; + wire \current_mem_addr[14]_i_1_n_0 ; + wire \current_mem_addr[14]_i_2_n_0 ; + wire \current_mem_addr[14]_i_3_n_0 ; + wire \current_mem_addr[14]_i_4_n_0 ; + wire \current_mem_addr[14]_i_5_n_0 ; + wire \current_mem_addr[14]_i_6_n_0 ; + wire \current_mem_addr[14]_i_7_n_0 ; + wire \current_mem_addr[14]_i_8_n_0 ; + wire \current_mem_addr[15]_i_13_n_0 ; + wire \current_mem_addr[15]_i_14_n_0 ; + wire \current_mem_addr[15]_i_15_n_0 ; + wire \current_mem_addr[15]_i_16_n_0 ; + wire \current_mem_addr[15]_i_17_n_0 ; + wire \current_mem_addr[15]_i_18_n_0 ; + wire \current_mem_addr[15]_i_19_n_0 ; + wire \current_mem_addr[15]_i_1_n_0 ; + wire \current_mem_addr[15]_i_20_n_0 ; + wire \current_mem_addr[15]_i_21_n_0 ; + wire \current_mem_addr[15]_i_22_n_0 ; + wire \current_mem_addr[15]_i_23_n_0 ; + wire \current_mem_addr[15]_i_24_n_0 ; + wire \current_mem_addr[15]_i_2_n_0 ; + wire \current_mem_addr[15]_i_3_n_0 ; + wire \current_mem_addr[15]_i_4_n_0 ; + wire \current_mem_addr[15]_i_5_n_0 ; + wire \current_mem_addr[15]_i_7_n_0 ; + wire \current_mem_addr[15]_i_8_n_0 ; + wire \current_mem_addr[1]_i_1_n_0 ; + wire \current_mem_addr[1]_i_2_n_0 ; + wire \current_mem_addr[1]_i_3_n_0 ; + wire \current_mem_addr[1]_i_4_n_0 ; + wire \current_mem_addr[1]_i_5_n_0 ; + wire \current_mem_addr[1]_i_6_n_0 ; + wire \current_mem_addr[1]_i_7_n_0 ; + wire \current_mem_addr[2]_i_1_n_0 ; + wire \current_mem_addr[2]_i_2_n_0 ; + wire \current_mem_addr[2]_i_3_n_0 ; + wire \current_mem_addr[2]_i_4_n_0 ; + wire \current_mem_addr[3]_i_10_n_0 ; + wire \current_mem_addr[3]_i_11_n_0 ; + wire \current_mem_addr[3]_i_12_n_0 ; + wire \current_mem_addr[3]_i_1_n_0 ; + wire \current_mem_addr[3]_i_2_n_0 ; + wire \current_mem_addr[3]_i_3_n_0 ; + wire \current_mem_addr[3]_i_4_n_0 ; + wire \current_mem_addr[3]_i_5_n_0 ; + wire \current_mem_addr[3]_i_6_n_0 ; + wire \current_mem_addr[3]_i_9_n_0 ; + wire \current_mem_addr[4]_i_10_n_0 ; + wire \current_mem_addr[4]_i_11_n_0 ; + wire \current_mem_addr[4]_i_12_n_0 ; + wire \current_mem_addr[4]_i_13_n_0 ; + wire \current_mem_addr[4]_i_1_n_0 ; + wire \current_mem_addr[4]_i_2_n_0 ; + wire \current_mem_addr[4]_i_3_n_0 ; + wire \current_mem_addr[4]_i_4_n_0 ; + wire \current_mem_addr[4]_i_5_n_0 ; + wire \current_mem_addr[4]_i_6_n_0 ; + wire \current_mem_addr[4]_i_7_n_0 ; + wire \current_mem_addr[5]_i_1_n_0 ; + wire \current_mem_addr[5]_i_2_n_0 ; + wire \current_mem_addr[5]_i_3_n_0 ; + wire \current_mem_addr[5]_i_4_n_0 ; + wire \current_mem_addr[5]_i_5_n_0 ; + wire \current_mem_addr[6]_i_1_n_0 ; + wire \current_mem_addr[6]_i_2_n_0 ; + wire \current_mem_addr[6]_i_3_n_0 ; + wire \current_mem_addr[6]_i_4_n_0 ; + wire \current_mem_addr[6]_i_5_n_0 ; + wire \current_mem_addr[7]_i_10_n_0 ; + wire \current_mem_addr[7]_i_11_n_0 ; + wire \current_mem_addr[7]_i_1_n_0 ; + wire \current_mem_addr[7]_i_2_n_0 ; + wire \current_mem_addr[7]_i_3_n_0 ; + wire \current_mem_addr[7]_i_4_n_0 ; + wire \current_mem_addr[7]_i_5_n_0 ; + wire \current_mem_addr[7]_i_8_n_0 ; + wire \current_mem_addr[7]_i_9_n_0 ; + wire \current_mem_addr[8]_i_10_n_0 ; + wire \current_mem_addr[8]_i_1_n_0 ; + wire \current_mem_addr[8]_i_2_n_0 ; + wire \current_mem_addr[8]_i_3_n_0 ; + wire \current_mem_addr[8]_i_4_n_0 ; + wire \current_mem_addr[8]_i_7_n_0 ; + wire \current_mem_addr[8]_i_8_n_0 ; + wire \current_mem_addr[8]_i_9_n_0 ; + wire \current_mem_addr[9]_i_1_n_0 ; + wire \current_mem_addr[9]_i_2_n_0 ; + wire \current_mem_addr[9]_i_3_n_0 ; + wire \current_mem_addr[9]_i_4_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_1 ; + wire \current_mem_addr_reg[11]_i_5_n_2 ; + wire \current_mem_addr_reg[11]_i_5_n_3 ; + wire \current_mem_addr_reg[11]_i_6_n_0 ; + wire \current_mem_addr_reg[11]_i_6_n_1 ; + wire \current_mem_addr_reg[11]_i_6_n_2 ; + wire \current_mem_addr_reg[11]_i_6_n_3 ; + wire \current_mem_addr_reg[12]_i_5_n_0 ; + wire \current_mem_addr_reg[12]_i_5_n_1 ; + wire \current_mem_addr_reg[12]_i_5_n_2 ; + wire \current_mem_addr_reg[12]_i_5_n_3 ; + wire \current_mem_addr_reg[15]_i_10_n_1 ; + wire \current_mem_addr_reg[15]_i_10_n_2 ; + wire \current_mem_addr_reg[15]_i_10_n_3 ; + wire \current_mem_addr_reg[15]_i_11_n_1 ; + wire \current_mem_addr_reg[15]_i_11_n_2 ; + wire \current_mem_addr_reg[15]_i_11_n_3 ; + wire \current_mem_addr_reg[15]_i_12_n_0 ; + wire \current_mem_addr_reg[15]_i_12_n_1 ; + wire \current_mem_addr_reg[15]_i_12_n_2 ; + wire \current_mem_addr_reg[15]_i_12_n_3 ; + wire \current_mem_addr_reg[15]_i_6_n_2 ; + wire \current_mem_addr_reg[15]_i_6_n_3 ; + wire \current_mem_addr_reg[15]_i_9_n_2 ; + wire \current_mem_addr_reg[15]_i_9_n_3 ; + wire \current_mem_addr_reg[3]_i_7_n_0 ; + wire \current_mem_addr_reg[3]_i_7_n_1 ; + wire \current_mem_addr_reg[3]_i_7_n_2 ; + wire \current_mem_addr_reg[3]_i_7_n_3 ; + wire \current_mem_addr_reg[3]_i_8_n_0 ; + wire \current_mem_addr_reg[3]_i_8_n_1 ; + wire \current_mem_addr_reg[3]_i_8_n_2 ; + wire \current_mem_addr_reg[3]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_8_n_0 ; + wire \current_mem_addr_reg[4]_i_8_n_1 ; + wire \current_mem_addr_reg[4]_i_8_n_2 ; + wire \current_mem_addr_reg[4]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_9_n_0 ; + wire \current_mem_addr_reg[4]_i_9_n_1 ; + wire \current_mem_addr_reg[4]_i_9_n_2 ; + wire \current_mem_addr_reg[4]_i_9_n_3 ; + wire \current_mem_addr_reg[7]_i_6_n_0 ; + wire \current_mem_addr_reg[7]_i_6_n_1 ; + wire \current_mem_addr_reg[7]_i_6_n_2 ; + wire \current_mem_addr_reg[7]_i_6_n_3 ; + wire \current_mem_addr_reg[7]_i_7_n_0 ; + wire \current_mem_addr_reg[7]_i_7_n_1 ; + wire \current_mem_addr_reg[7]_i_7_n_2 ; + wire \current_mem_addr_reg[7]_i_7_n_3 ; + wire \current_mem_addr_reg[8]_i_5_n_0 ; + wire \current_mem_addr_reg[8]_i_5_n_1 ; + wire \current_mem_addr_reg[8]_i_5_n_2 ; + wire \current_mem_addr_reg[8]_i_5_n_3 ; + wire \current_mem_addr_reg[8]_i_6_n_0 ; + wire \current_mem_addr_reg[8]_i_6_n_1 ; + wire \current_mem_addr_reg[8]_i_6_n_2 ; + wire \current_mem_addr_reg[8]_i_6_n_3 ; + wire [5:0]current_popped_id; + wire \current_popped_id[5]_i_1_n_0 ; + wire \current_popped_id[5]_i_2_n_0 ; + wire [7:0]current_task_count; + wire \current_task_count[0]_i_1_n_0 ; + wire \current_task_count[1]_i_1_n_0 ; + wire \current_task_count[2]_i_1_n_0 ; + wire \current_task_count[3]_i_1_n_0 ; + wire \current_task_count[4]_i_1_n_0 ; + wire \current_task_count[4]_i_2_n_0 ; + wire \current_task_count[5]_i_1_n_0 ; + wire \current_task_count[5]_i_2_n_0 ; + wire \current_task_count[5]_i_3_n_0 ; + wire \current_task_count[6]_i_1_n_0 ; + wire \current_task_count[7]_i_1_n_0 ; + wire \current_task_count[7]_i_2_n_0 ; + wire \current_task_count[7]_i_3_n_0 ; + wire \current_task_count[7]_i_4_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in23; + wire [15:1]in26; + wire [15:1]in27; + wire [15:0]in30; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[3]_i_3_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_en_i_4_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire o_mem_we_i_3_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED ; + wire [0:0]\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_task_count[3]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_task_count[4]), + .I1(current_task_count[3]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(current_task_count[2]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[13]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h2100002100214200)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_3_n_0 ), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\FSM_onehot_state[12]_i_10_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[5]), + .I3(\current_task_count[5]_i_2_n_0 ), + .I4(o_mem_addr_OBUF[4]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_task_count[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF2)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[15]_i_3 + (.I0(i_task_id_IBUF[5]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[3]), + .I3(i_task_id_IBUF[4]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF1)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_4_n_0 ), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state[17]_i_4_n_0 ), + .I1(\FSM_onehot_state[17]_i_5_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[17]_i_4 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[17]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[17]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h20)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[17]_i_4_n_0 ), + .I2(\FSM_onehot_state[17]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000002)) + \FSM_onehot_state[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFFFEFF)) + \FSM_onehot_state[21]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(\FSM_onehot_state[21]_i_4_n_0 ), + .I2(\FSM_onehot_state[21]_i_5_n_0 ), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_7_n_0 ), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[15]), + .I3(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[10]), + .I1(o_mem_addr_OBUF[11]), + .I2(o_mem_addr_OBUF[9]), + .I3(o_mem_addr_OBUF[8]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'hBF0B)) + \FSM_onehot_state[21]_i_7 + (.I0(i_task_priority_IBUF[0]), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(i_task_priority_IBUF[1]), + .O(\FSM_onehot_state[21]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state[23]_i_4_n_0 ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[2] ), + .I5(\FSM_onehot_state[23]_i_5_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_2 + (.I0(o_mem_en_i_2_n_0), + .I1(\FSM_onehot_state[23]_i_6_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .I3(\FSM_onehot_state_reg_n_0_[7] ), + .I4(\FSM_onehot_state_reg_n_0_[14] ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[15] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[22] ), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[4] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA8)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[8]_i_2 + (.I0(current_task_count[7]), + .I1(current_task_count[6]), + .I2(current_task_count[3]), + .I3(current_task_count[4]), + .I4(current_task_count[5]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT6 #( + .INIT(64'hFF54FF54FFFFFF54)) + \current_mem_addr[0]_i_1 + (.I0(\current_mem_addr[0]_i_2_n_0 ), + .I1(\current_mem_addr[0]_i_3_n_0 ), + .I2(\current_mem_addr[0]_i_4_n_0 ), + .I3(\current_mem_addr[0]_i_5_n_0 ), + .I4(current_task_count[0]), + .I5(\current_mem_addr[0]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'hE)) + \current_mem_addr[0]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .O(\current_mem_addr[0]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'hFEEE)) + \current_mem_addr[0]_i_11 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000000000000777)) + \current_mem_addr[0]_i_2 + (.I0(in30[0]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .I4(\current_mem_addr[0]_i_7_n_0 ), + .I5(\current_mem_addr[3]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[0]_i_3 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + \current_mem_addr[0]_i_4 + (.I0(\current_mem_addr[0]_i_8_n_0 ), + .I1(\current_mem_addr[0]_i_9_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in30[0]), + .I4(\current_mem_addr[0]_i_10_n_0 ), + .I5(\current_mem_addr[0]_i_11_n_0 ), + .O(\current_mem_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAEFF00AEAE)) + \current_mem_addr[0]_i_5 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\current_mem_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \current_mem_addr[0]_i_6 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\current_mem_addr[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[0]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(o_mem_addr_OBUF[0]), + .O(\current_mem_addr[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h55555554)) + \current_mem_addr[0]_i_8 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[9] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[0]_i_9 + (.I0(\FSM_onehot_state[23]_i_4_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[8] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state_reg_n_0_[4] ), + .O(\current_mem_addr[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[10]_i_1 + (.I0(\current_mem_addr[10]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[10]), + .I3(\current_mem_addr[10]_i_3_n_0 ), + .I4(\current_mem_addr[10]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[10]_i_2 + (.I0(in26[10]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[10]_i_3 + (.I0(in30[10]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[10]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[10]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[10]), + .O(\current_mem_addr[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[11]_i_1 + (.I0(\current_mem_addr[11]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[11]), + .I3(\current_mem_addr[11]_i_3_n_0 ), + .I4(\current_mem_addr[11]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[11]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[11]_i_2 + (.I0(in26[11]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[11]_i_3 + (.I0(in27[11]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[11]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[11]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[11]), + .O(\current_mem_addr[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[11]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[12]_i_1 + (.I0(\current_mem_addr[12]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[12]), + .I3(\current_mem_addr[12]_i_3_n_0 ), + .I4(\current_mem_addr[12]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[12]_i_2 + (.I0(in26[12]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[12]_i_3 + (.I0(in30[12]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[12]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[12]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[12]), + .O(\current_mem_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[13]_i_1 + (.I0(\current_mem_addr[13]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[13]), + .I3(\current_mem_addr[13]_i_3_n_0 ), + .I4(\current_mem_addr[13]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[13]_i_2 + (.I0(in26[13]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[13]_i_3 + (.I0(in30[13]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[13]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[13]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[13]), + .O(\current_mem_addr[13]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[14]_i_1 + (.I0(\current_mem_addr[14]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[14]), + .I3(\current_mem_addr[14]_i_4_n_0 ), + .I4(\current_mem_addr[14]_i_5_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[14]_i_2 + (.I0(in26[14]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_mem_addr[14]_i_3 + (.I0(\current_mem_addr[14]_i_7_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\current_mem_addr[14]_i_8_n_0 ), + .O(\current_mem_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[14]_i_4 + (.I0(in30[14]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[14]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[14]_i_5 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[14]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[14]), + .O(\current_mem_addr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'h00000045)) + \current_mem_addr[14]_i_6 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[14]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[8] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\current_mem_addr[14]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .O(\current_mem_addr[14]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_mem_addr[15]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_16 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\current_mem_addr[15]_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_17 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_18 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_19 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \current_mem_addr[15]_i_2 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\current_mem_addr[15]_i_4_n_0 ), + .I3(\current_mem_addr[15]_i_5_n_0 ), + .I4(in26[15]), + .I5(\current_mem_addr[15]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_20 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_20_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_21 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_21_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_22 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[15]_i_22_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_23 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[15]_i_23_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_24 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[15]_i_24_n_0 )); + LUT6 #( + .INIT(64'h0000000011010000)) + \current_mem_addr[15]_i_3 + (.I0(\FSM_onehot_state[1]_i_3_n_0 ), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\current_mem_addr[14]_i_3_n_0 ), + .I5(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[15]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[15]), + .O(\current_mem_addr[15]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[15]_i_5 + (.I0(in27[15]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[15]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[15]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h45)) + \current_mem_addr[15]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_8 + (.I0(\current_mem_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\current_mem_addr[14]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[1]_i_1 + (.I0(\current_mem_addr[1]_i_2_n_0 ), + .I1(\current_mem_addr[1]_i_3_n_0 ), + .I2(\current_mem_addr[1]_i_4_n_0 ), + .I3(\current_mem_addr[1]_i_5_n_0 ), + .I4(\current_mem_addr[1]_i_6_n_0 ), + .I5(\current_mem_addr[1]_i_7_n_0 ), + .O(\current_mem_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[1]_i_2 + (.I0(current_task_count[1]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA8A8AAA8AAAAAAAA)) + \current_mem_addr[1]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\current_mem_addr[14]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[1]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[1]), + .O(\current_mem_addr[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[1]_i_5 + (.I0(in30[1]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[1]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[1]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[1]_i_7 + (.I0(in26[1]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[1]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFEEFE)) + \current_mem_addr[2]_i_1 + (.I0(\current_mem_addr[2]_i_2_n_0 ), + .I1(\current_mem_addr[2]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[2]), + .I3(\current_mem_addr[15]_i_3_n_0 ), + .I4(\current_mem_addr[2]_i_4_n_0 ), + .O(\current_mem_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[2]_i_2 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[2]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[2]), + .O(\current_mem_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[2]_i_3 + (.I0(in30[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[2]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[2]_i_4 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[2]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[2]), + .O(\current_mem_addr[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF0FFB0)) + \current_mem_addr[3]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\current_mem_addr[3]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[3]), + .I3(\current_mem_addr[3]_i_3_n_0 ), + .I4(\current_mem_addr[3]_i_4_n_0 ), + .I5(\current_mem_addr[3]_i_5_n_0 ), + .O(\current_mem_addr[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_10 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[3]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_11 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[3]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_12 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_12_n_0 )); + LUT5 #( + .INIT(32'h0000008A)) + \current_mem_addr[3]_i_2 + (.I0(\current_mem_addr[14]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[3]_i_3 + (.I0(\current_mem_addr[3]_i_6_n_0 ), + .I1(in23[3]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[3]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[3]), + .O(\current_mem_addr[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[3]_i_4 + (.I0(in23[3]), + .I1(\current_mem_addr[15]_i_8_n_0 ), + .O(\current_mem_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[3]_i_5 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[3]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[3]), + .O(\current_mem_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[3]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_mem_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[4]_i_1 + (.I0(\current_mem_addr[4]_i_2_n_0 ), + .I1(\current_mem_addr[4]_i_3_n_0 ), + .I2(\current_mem_addr[4]_i_4_n_0 ), + .I3(\current_mem_addr[4]_i_5_n_0 ), + .I4(\current_mem_addr[4]_i_6_n_0 ), + .I5(\current_mem_addr[4]_i_7_n_0 ), + .O(\current_mem_addr[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_10 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[4]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_11 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[4]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_12 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[4]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_13 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[4]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[4]_i_2 + (.I0(current_task_count[4]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[4]_i_3 + (.I0(in26[4]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[4]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[4]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[4]), + .O(\current_mem_addr[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[4]_i_5 + (.I0(in30[4]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in26[4]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in27[4]), + .O(\current_mem_addr[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hAA8A)) + \current_mem_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\current_mem_addr[14]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[5]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\current_mem_addr[5]_i_2_n_0 ), + .I3(\current_mem_addr[5]_i_3_n_0 ), + .I4(\current_mem_addr[5]_i_4_n_0 ), + .I5(\current_mem_addr[5]_i_5_n_0 ), + .O(\current_mem_addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[5]_i_2 + (.I0(in26[5]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[5]_i_3 + (.I0(in26[5]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[5]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[5]), + .O(\current_mem_addr[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[5]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[5]), + .O(\current_mem_addr[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[5]_i_5 + (.I0(current_task_count[5]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[6]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\current_mem_addr[6]_i_2_n_0 ), + .I3(\current_mem_addr[6]_i_3_n_0 ), + .I4(\current_mem_addr[6]_i_4_n_0 ), + .I5(\current_mem_addr[6]_i_5_n_0 ), + .O(\current_mem_addr[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[6]_i_2 + (.I0(in26[6]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[6]_i_3 + (.I0(in26[6]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[6]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[6]), + .O(\current_mem_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[6]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[6]), + .O(\current_mem_addr[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[6]_i_5 + (.I0(current_task_count[6]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[7]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\current_mem_addr[7]_i_2_n_0 ), + .I3(\current_mem_addr[7]_i_3_n_0 ), + .I4(\current_mem_addr[7]_i_4_n_0 ), + .I5(\current_mem_addr[7]_i_5_n_0 ), + .O(\current_mem_addr[7]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[7]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_11 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[7]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[7]_i_2 + (.I0(in26[7]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[7]_i_3 + (.I0(in26[7]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[7]), + .O(\current_mem_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[7]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[7]), + .O(\current_mem_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[7]_i_5 + (.I0(current_task_count[7]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[7]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[7]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[8]_i_1 + (.I0(\current_mem_addr[8]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[8]), + .I3(\current_mem_addr[8]_i_3_n_0 ), + .I4(\current_mem_addr[8]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[8]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[8]_i_2 + (.I0(in26[8]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[8]_i_3 + (.I0(in30[8]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[8]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[8]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[8]), + .O(\current_mem_addr[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[8]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[8]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[9]_i_1 + (.I0(\current_mem_addr[9]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[9]), + .I3(\current_mem_addr[9]_i_3_n_0 ), + .I4(\current_mem_addr[9]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[9]_i_2 + (.I0(in26[9]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[9]_i_3 + (.I0(in30[9]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[9]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[9]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[9]), + .O(\current_mem_addr[9]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_5 + (.CI(\current_mem_addr_reg[7]_i_6_n_0 ), + .CO({\current_mem_addr_reg[11]_i_5_n_0 ,\current_mem_addr_reg[11]_i_5_n_1 ,\current_mem_addr_reg[11]_i_5_n_2 ,\current_mem_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_6 + (.CI(\current_mem_addr_reg[7]_i_7_n_0 ), + .CO({\current_mem_addr_reg[11]_i_6_n_0 ,\current_mem_addr_reg[11]_i_6_n_1 ,\current_mem_addr_reg[11]_i_6_n_2 ,\current_mem_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in30[11:8]), + .S({\current_mem_addr[11]_i_7_n_0 ,\current_mem_addr[11]_i_8_n_0 ,\current_mem_addr[11]_i_9_n_0 ,\current_mem_addr[11]_i_10_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[12]_i_5 + (.CI(\current_mem_addr_reg[8]_i_6_n_0 ), + .CO({\current_mem_addr_reg[12]_i_5_n_0 ,\current_mem_addr_reg[12]_i_5_n_1 ,\current_mem_addr_reg[12]_i_5_n_2 ,\current_mem_addr_reg[12]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_10 + (.CI(\current_mem_addr_reg[11]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_10_n_1 ,\current_mem_addr_reg[15]_i_10_n_2 ,\current_mem_addr_reg[15]_i_10_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[15:12]), + .S(o_mem_addr_OBUF[15:12])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_11 + (.CI(\current_mem_addr_reg[11]_i_6_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_11_n_1 ,\current_mem_addr_reg[15]_i_11_n_2 ,\current_mem_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in30[15:12]), + .S({\current_mem_addr[15]_i_17_n_0 ,\current_mem_addr[15]_i_18_n_0 ,\current_mem_addr[15]_i_19_n_0 ,\current_mem_addr[15]_i_20_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_12 + (.CI(\current_mem_addr_reg[8]_i_5_n_0 ), + .CO({\current_mem_addr_reg[15]_i_12_n_0 ,\current_mem_addr_reg[15]_i_12_n_1 ,\current_mem_addr_reg[15]_i_12_n_2 ,\current_mem_addr_reg[15]_i_12_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in26[12:9]), + .S({\current_mem_addr[15]_i_21_n_0 ,\current_mem_addr[15]_i_22_n_0 ,\current_mem_addr[15]_i_23_n_0 ,\current_mem_addr[15]_i_24_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_6 + (.CI(\current_mem_addr_reg[15]_i_12_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_6_n_2 ,\current_mem_addr_reg[15]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED [3],in26[15:13]}), + .S({1'b0,\current_mem_addr[15]_i_13_n_0 ,\current_mem_addr[15]_i_14_n_0 ,\current_mem_addr[15]_i_15_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_9 + (.CI(\current_mem_addr_reg[12]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_9_n_2 ,\current_mem_addr_reg[15]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED [3],in23[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_7 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_7_n_0 ,\current_mem_addr_reg[3]_i_7_n_1 ,\current_mem_addr_reg[3]_i_7_n_2 ,\current_mem_addr_reg[3]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in27[3:1],in30[0]}), + .S({o_mem_addr_OBUF[3:2],\current_mem_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_8_n_0 ,\current_mem_addr_reg[3]_i_8_n_1 ,\current_mem_addr_reg[3]_i_8_n_2 ,\current_mem_addr_reg[3]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in30[3:1],\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED [0]}), + .S({\current_mem_addr[3]_i_10_n_0 ,\current_mem_addr[3]_i_11_n_0 ,\current_mem_addr[3]_i_12_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_8_n_0 ,\current_mem_addr_reg[4]_i_8_n_1 ,\current_mem_addr_reg[4]_i_8_n_2 ,\current_mem_addr_reg[4]_i_8_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in26[4:1]), + .S({\current_mem_addr[4]_i_10_n_0 ,\current_mem_addr[4]_i_11_n_0 ,\current_mem_addr[4]_i_12_n_0 ,\current_mem_addr[4]_i_13_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_9 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_9_n_0 ,\current_mem_addr_reg[4]_i_9_n_1 ,\current_mem_addr_reg[4]_i_9_n_2 ,\current_mem_addr_reg[4]_i_9_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_6 + (.CI(\current_mem_addr_reg[3]_i_7_n_0 ), + .CO({\current_mem_addr_reg[7]_i_6_n_0 ,\current_mem_addr_reg[7]_i_6_n_1 ,\current_mem_addr_reg[7]_i_6_n_2 ,\current_mem_addr_reg[7]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_7 + (.CI(\current_mem_addr_reg[3]_i_8_n_0 ), + .CO({\current_mem_addr_reg[7]_i_7_n_0 ,\current_mem_addr_reg[7]_i_7_n_1 ,\current_mem_addr_reg[7]_i_7_n_2 ,\current_mem_addr_reg[7]_i_7_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in30[7:4]), + .S({\current_mem_addr[7]_i_8_n_0 ,\current_mem_addr[7]_i_9_n_0 ,\current_mem_addr[7]_i_10_n_0 ,\current_mem_addr[7]_i_11_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_5 + (.CI(\current_mem_addr_reg[4]_i_8_n_0 ), + .CO({\current_mem_addr_reg[8]_i_5_n_0 ,\current_mem_addr_reg[8]_i_5_n_1 ,\current_mem_addr_reg[8]_i_5_n_2 ,\current_mem_addr_reg[8]_i_5_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in26[8:5]), + .S({\current_mem_addr[8]_i_7_n_0 ,\current_mem_addr[8]_i_8_n_0 ,\current_mem_addr[8]_i_9_n_0 ,\current_mem_addr[8]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_6 + (.CI(\current_mem_addr_reg[4]_i_9_n_0 ), + .CO({\current_mem_addr_reg[8]_i_6_n_0 ,\current_mem_addr_reg[8]_i_6_n_1 ,\current_mem_addr_reg[8]_i_6_n_2 ,\current_mem_addr_reg[8]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000EA)) + \current_popped_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555540)) + \current_popped_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(i_start_IBUF), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_popped_id[0]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_popped_id[1]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_popped_id[2]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_popped_id[3]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_popped_id[4]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_popped_id[5]), + .R(\current_popped_id[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'h54)) + \current_task_count[0]_i_1 + (.I0(current_task_count[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_task_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_task_count[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_task_count[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_task_count[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[3]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[2]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBEAA)) + \current_task_count[4]_i_1 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_task_count[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[4]), + .O(\current_task_count[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF44FF4F444444444)) + \current_task_count[5]_i_1 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[5]), + .I3(current_task_count[4]), + .I4(\current_task_count[5]_i_3_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_task_count[5]_i_2 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[2]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[3]), + .O(\current_task_count[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + \current_task_count[5]_i_3 + (.I0(current_task_count[3]), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(current_task_count[2]), + .O(\current_task_count[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h8FF48484)) + \current_task_count[6]_i_1 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[6]), + .I3(\current_task_count[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_task_count[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[0] ), + .O(\current_task_count[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4CFF4F084C084C0)) + \current_task_count[7]_i_2 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \current_task_count[7]_i_3 + (.I0(current_task_count[4]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[5]), + .O(\current_task_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_task_count[7]_i_4 + (.I0(current_task_count[2]), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[3]), + .I4(current_task_count[5]), + .I5(current_task_count[4]), + .O(\current_task_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[0]_i_1_n_0 ), + .Q(current_task_count[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[1]_i_1_n_0 ), + .Q(current_task_count[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[2]_i_1_n_0 ), + .Q(current_task_count[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[3]_i_1_n_0 ), + .Q(current_task_count[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[4]_i_1_n_0 ), + .Q(current_task_count[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[5]_i_1_n_0 ), + .Q(current_task_count[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[6]_i_1_n_0 ), + .Q(current_task_count[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[7]_i_2_n_0 ), + .Q(current_task_count[7]), + .R(1'b0)); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT6 #( + .INIT(64'hFFE0FFE0FFFFFFE0)) + \o_mem_data[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .I2(i_mem_data_IBUF[0]), + .I3(\o_mem_data[0]_i_2_n_0 ), + .I4(i_task_priority_IBUF[0]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_task_count[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFBAFFBAFFFFFFBA)) + \o_mem_data[1]_i_1 + (.I0(\o_mem_data[1]_i_2_n_0 ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[11]_i_1_n_0 ), + .I3(\o_mem_data[1]_i_4_n_0 ), + .I4(i_mem_data_IBUF[1]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAA8880)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[0]), + .I4(i_task_priority_IBUF[1]), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_3 + (.I0(current_task_count[0]), + .I1(current_task_count[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888F8888888888)) + \o_mem_data[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(\o_mem_data[3]_i_3_n_0 ), + .I4(i_task_id_IBUF[1]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h2AAA8000)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[2]), + .I4(current_task_count[3]), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888888000000008)) + \o_mem_data[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(current_task_count[3]), + .O(\o_mem_data[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\o_mem_data[4]_i_2_n_0 ), + .I3(i_task_id_IBUF[2]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBEAAAAAA)) + \o_mem_data[4]_i_2 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[5]), + .I2(\o_mem_data[5]_i_2_n_0 ), + .I3(i_task_id_IBUF[3]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4F444444)) + \o_mem_data[5]_i_2 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\o_mem_data[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5555555555555556)) + \o_mem_data[5]_i_3 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[3]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[2]), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[6]_i_1 + (.I0(\o_mem_data[6]_i_2_n_0 ), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_3_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_2 + (.I0(current_task_count[6]), + .I1(current_task_count[4]), + .I2(current_task_count[5]), + .I3(\current_task_count[5]_i_3_n_0 ), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h55554055)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h82)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_task_count[7]_i_3_n_0 ), + .I2(current_task_count[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'hE200)) + \o_mem_data[6]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(\FSM_onehot_state[21]_i_2_n_0 ), + .I2(i_mem_data_IBUF[6]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(i_task_id_IBUF[5]), + .I4(\o_mem_data[7]_i_3_n_0 ), + .I5(\o_mem_data[7]_i_4_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FB00FB)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\o_mem_data[7]_i_5_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\FSM_onehot_state[21]_i_2_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h88080080)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\current_task_count[7]_i_4_n_0 ), + .I3(current_task_count[6]), + .I4(current_task_count[7]), + .O(\o_mem_data[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA208)) + \o_mem_data[7]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[6]), + .I2(\current_task_count[7]_i_3_n_0 ), + .I3(current_task_count[7]), + .O(\o_mem_data[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \o_mem_data[7]_i_5 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_we_i_3_n_0), + .I3(o_mem_en_i_2_n_0), + .I4(o_mem_en_i_3_n_0), + .I5(\FSM_onehot_state[17]_i_3_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(\FSM_onehot_state[10]_i_1_n_0 ), + .I3(o_mem_en_i_4_n_0), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(o_mem_en_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + o_mem_en_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[22] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .O(o_mem_en_i_4_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hFFFD)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(o_mem_we_i_3_n_0), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(ctrl_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000111)) + o_mem_we_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[22] ), + .O(o_mem_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0444)) + o_mem_we_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(o_mem_we_i_3_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.wdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.wdb new file mode 100644 index 0000000..0b92c6f Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vhdl.prj b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vhdl.prj new file mode 100644 index 0000000..18ba9dd --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vhdl.prj @@ -0,0 +1,6 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \ + +# Do not sort compile order +nosort diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vlog.prj b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vlog.prj new file mode 100644 index 0000000..9dab6c1 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_vlog.prj @@ -0,0 +1,6 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib --include "../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \ +"project_tb_edge_func_synth.v" \ + +# Do not sort compile order +nosort diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.v b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.v new file mode 100644 index 0000000..e92d2fe --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.v @@ -0,0 +1,3225 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Fri Jun 12 14:53:50 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode funcsim -nolib -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_4_n_0 ; + wire \FSM_onehot_state[17]_i_5_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[21]_i_7_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire \current_mem_addr[0]_i_10_n_0 ; + wire \current_mem_addr[0]_i_11_n_0 ; + wire \current_mem_addr[0]_i_1_n_0 ; + wire \current_mem_addr[0]_i_2_n_0 ; + wire \current_mem_addr[0]_i_3_n_0 ; + wire \current_mem_addr[0]_i_4_n_0 ; + wire \current_mem_addr[0]_i_5_n_0 ; + wire \current_mem_addr[0]_i_6_n_0 ; + wire \current_mem_addr[0]_i_7_n_0 ; + wire \current_mem_addr[0]_i_8_n_0 ; + wire \current_mem_addr[0]_i_9_n_0 ; + wire \current_mem_addr[10]_i_1_n_0 ; + wire \current_mem_addr[10]_i_2_n_0 ; + wire \current_mem_addr[10]_i_3_n_0 ; + wire \current_mem_addr[10]_i_4_n_0 ; + wire \current_mem_addr[11]_i_10_n_0 ; + wire \current_mem_addr[11]_i_1_n_0 ; + wire \current_mem_addr[11]_i_2_n_0 ; + wire \current_mem_addr[11]_i_3_n_0 ; + wire \current_mem_addr[11]_i_4_n_0 ; + wire \current_mem_addr[11]_i_7_n_0 ; + wire \current_mem_addr[11]_i_8_n_0 ; + wire \current_mem_addr[11]_i_9_n_0 ; + wire \current_mem_addr[12]_i_1_n_0 ; + wire \current_mem_addr[12]_i_2_n_0 ; + wire \current_mem_addr[12]_i_3_n_0 ; + wire \current_mem_addr[12]_i_4_n_0 ; + wire \current_mem_addr[13]_i_1_n_0 ; + wire \current_mem_addr[13]_i_2_n_0 ; + wire \current_mem_addr[13]_i_3_n_0 ; + wire \current_mem_addr[13]_i_4_n_0 ; + wire \current_mem_addr[14]_i_1_n_0 ; + wire \current_mem_addr[14]_i_2_n_0 ; + wire \current_mem_addr[14]_i_3_n_0 ; + wire \current_mem_addr[14]_i_4_n_0 ; + wire \current_mem_addr[14]_i_5_n_0 ; + wire \current_mem_addr[14]_i_6_n_0 ; + wire \current_mem_addr[14]_i_7_n_0 ; + wire \current_mem_addr[14]_i_8_n_0 ; + wire \current_mem_addr[15]_i_13_n_0 ; + wire \current_mem_addr[15]_i_14_n_0 ; + wire \current_mem_addr[15]_i_15_n_0 ; + wire \current_mem_addr[15]_i_16_n_0 ; + wire \current_mem_addr[15]_i_17_n_0 ; + wire \current_mem_addr[15]_i_18_n_0 ; + wire \current_mem_addr[15]_i_19_n_0 ; + wire \current_mem_addr[15]_i_1_n_0 ; + wire \current_mem_addr[15]_i_20_n_0 ; + wire \current_mem_addr[15]_i_21_n_0 ; + wire \current_mem_addr[15]_i_22_n_0 ; + wire \current_mem_addr[15]_i_23_n_0 ; + wire \current_mem_addr[15]_i_24_n_0 ; + wire \current_mem_addr[15]_i_2_n_0 ; + wire \current_mem_addr[15]_i_3_n_0 ; + wire \current_mem_addr[15]_i_4_n_0 ; + wire \current_mem_addr[15]_i_5_n_0 ; + wire \current_mem_addr[15]_i_7_n_0 ; + wire \current_mem_addr[15]_i_8_n_0 ; + wire \current_mem_addr[1]_i_1_n_0 ; + wire \current_mem_addr[1]_i_2_n_0 ; + wire \current_mem_addr[1]_i_3_n_0 ; + wire \current_mem_addr[1]_i_4_n_0 ; + wire \current_mem_addr[1]_i_5_n_0 ; + wire \current_mem_addr[1]_i_6_n_0 ; + wire \current_mem_addr[1]_i_7_n_0 ; + wire \current_mem_addr[2]_i_1_n_0 ; + wire \current_mem_addr[2]_i_2_n_0 ; + wire \current_mem_addr[2]_i_3_n_0 ; + wire \current_mem_addr[2]_i_4_n_0 ; + wire \current_mem_addr[3]_i_10_n_0 ; + wire \current_mem_addr[3]_i_11_n_0 ; + wire \current_mem_addr[3]_i_12_n_0 ; + wire \current_mem_addr[3]_i_1_n_0 ; + wire \current_mem_addr[3]_i_2_n_0 ; + wire \current_mem_addr[3]_i_3_n_0 ; + wire \current_mem_addr[3]_i_4_n_0 ; + wire \current_mem_addr[3]_i_5_n_0 ; + wire \current_mem_addr[3]_i_6_n_0 ; + wire \current_mem_addr[3]_i_9_n_0 ; + wire \current_mem_addr[4]_i_10_n_0 ; + wire \current_mem_addr[4]_i_11_n_0 ; + wire \current_mem_addr[4]_i_12_n_0 ; + wire \current_mem_addr[4]_i_13_n_0 ; + wire \current_mem_addr[4]_i_1_n_0 ; + wire \current_mem_addr[4]_i_2_n_0 ; + wire \current_mem_addr[4]_i_3_n_0 ; + wire \current_mem_addr[4]_i_4_n_0 ; + wire \current_mem_addr[4]_i_5_n_0 ; + wire \current_mem_addr[4]_i_6_n_0 ; + wire \current_mem_addr[4]_i_7_n_0 ; + wire \current_mem_addr[5]_i_1_n_0 ; + wire \current_mem_addr[5]_i_2_n_0 ; + wire \current_mem_addr[5]_i_3_n_0 ; + wire \current_mem_addr[5]_i_4_n_0 ; + wire \current_mem_addr[5]_i_5_n_0 ; + wire \current_mem_addr[6]_i_1_n_0 ; + wire \current_mem_addr[6]_i_2_n_0 ; + wire \current_mem_addr[6]_i_3_n_0 ; + wire \current_mem_addr[6]_i_4_n_0 ; + wire \current_mem_addr[6]_i_5_n_0 ; + wire \current_mem_addr[7]_i_10_n_0 ; + wire \current_mem_addr[7]_i_11_n_0 ; + wire \current_mem_addr[7]_i_1_n_0 ; + wire \current_mem_addr[7]_i_2_n_0 ; + wire \current_mem_addr[7]_i_3_n_0 ; + wire \current_mem_addr[7]_i_4_n_0 ; + wire \current_mem_addr[7]_i_5_n_0 ; + wire \current_mem_addr[7]_i_8_n_0 ; + wire \current_mem_addr[7]_i_9_n_0 ; + wire \current_mem_addr[8]_i_10_n_0 ; + wire \current_mem_addr[8]_i_1_n_0 ; + wire \current_mem_addr[8]_i_2_n_0 ; + wire \current_mem_addr[8]_i_3_n_0 ; + wire \current_mem_addr[8]_i_4_n_0 ; + wire \current_mem_addr[8]_i_7_n_0 ; + wire \current_mem_addr[8]_i_8_n_0 ; + wire \current_mem_addr[8]_i_9_n_0 ; + wire \current_mem_addr[9]_i_1_n_0 ; + wire \current_mem_addr[9]_i_2_n_0 ; + wire \current_mem_addr[9]_i_3_n_0 ; + wire \current_mem_addr[9]_i_4_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_1 ; + wire \current_mem_addr_reg[11]_i_5_n_2 ; + wire \current_mem_addr_reg[11]_i_5_n_3 ; + wire \current_mem_addr_reg[11]_i_6_n_0 ; + wire \current_mem_addr_reg[11]_i_6_n_1 ; + wire \current_mem_addr_reg[11]_i_6_n_2 ; + wire \current_mem_addr_reg[11]_i_6_n_3 ; + wire \current_mem_addr_reg[12]_i_5_n_0 ; + wire \current_mem_addr_reg[12]_i_5_n_1 ; + wire \current_mem_addr_reg[12]_i_5_n_2 ; + wire \current_mem_addr_reg[12]_i_5_n_3 ; + wire \current_mem_addr_reg[15]_i_10_n_1 ; + wire \current_mem_addr_reg[15]_i_10_n_2 ; + wire \current_mem_addr_reg[15]_i_10_n_3 ; + wire \current_mem_addr_reg[15]_i_11_n_1 ; + wire \current_mem_addr_reg[15]_i_11_n_2 ; + wire \current_mem_addr_reg[15]_i_11_n_3 ; + wire \current_mem_addr_reg[15]_i_12_n_0 ; + wire \current_mem_addr_reg[15]_i_12_n_1 ; + wire \current_mem_addr_reg[15]_i_12_n_2 ; + wire \current_mem_addr_reg[15]_i_12_n_3 ; + wire \current_mem_addr_reg[15]_i_6_n_2 ; + wire \current_mem_addr_reg[15]_i_6_n_3 ; + wire \current_mem_addr_reg[15]_i_9_n_2 ; + wire \current_mem_addr_reg[15]_i_9_n_3 ; + wire \current_mem_addr_reg[3]_i_7_n_0 ; + wire \current_mem_addr_reg[3]_i_7_n_1 ; + wire \current_mem_addr_reg[3]_i_7_n_2 ; + wire \current_mem_addr_reg[3]_i_7_n_3 ; + wire \current_mem_addr_reg[3]_i_8_n_0 ; + wire \current_mem_addr_reg[3]_i_8_n_1 ; + wire \current_mem_addr_reg[3]_i_8_n_2 ; + wire \current_mem_addr_reg[3]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_8_n_0 ; + wire \current_mem_addr_reg[4]_i_8_n_1 ; + wire \current_mem_addr_reg[4]_i_8_n_2 ; + wire \current_mem_addr_reg[4]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_9_n_0 ; + wire \current_mem_addr_reg[4]_i_9_n_1 ; + wire \current_mem_addr_reg[4]_i_9_n_2 ; + wire \current_mem_addr_reg[4]_i_9_n_3 ; + wire \current_mem_addr_reg[7]_i_6_n_0 ; + wire \current_mem_addr_reg[7]_i_6_n_1 ; + wire \current_mem_addr_reg[7]_i_6_n_2 ; + wire \current_mem_addr_reg[7]_i_6_n_3 ; + wire \current_mem_addr_reg[7]_i_7_n_0 ; + wire \current_mem_addr_reg[7]_i_7_n_1 ; + wire \current_mem_addr_reg[7]_i_7_n_2 ; + wire \current_mem_addr_reg[7]_i_7_n_3 ; + wire \current_mem_addr_reg[8]_i_5_n_0 ; + wire \current_mem_addr_reg[8]_i_5_n_1 ; + wire \current_mem_addr_reg[8]_i_5_n_2 ; + wire \current_mem_addr_reg[8]_i_5_n_3 ; + wire \current_mem_addr_reg[8]_i_6_n_0 ; + wire \current_mem_addr_reg[8]_i_6_n_1 ; + wire \current_mem_addr_reg[8]_i_6_n_2 ; + wire \current_mem_addr_reg[8]_i_6_n_3 ; + wire [5:0]current_popped_id; + wire \current_popped_id[5]_i_1_n_0 ; + wire \current_popped_id[5]_i_2_n_0 ; + wire [7:0]current_task_count; + wire \current_task_count[0]_i_1_n_0 ; + wire \current_task_count[1]_i_1_n_0 ; + wire \current_task_count[2]_i_1_n_0 ; + wire \current_task_count[3]_i_1_n_0 ; + wire \current_task_count[4]_i_1_n_0 ; + wire \current_task_count[4]_i_2_n_0 ; + wire \current_task_count[5]_i_1_n_0 ; + wire \current_task_count[5]_i_2_n_0 ; + wire \current_task_count[5]_i_3_n_0 ; + wire \current_task_count[6]_i_1_n_0 ; + wire \current_task_count[7]_i_1_n_0 ; + wire \current_task_count[7]_i_2_n_0 ; + wire \current_task_count[7]_i_3_n_0 ; + wire \current_task_count[7]_i_4_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in23; + wire [15:1]in26; + wire [15:1]in27; + wire [15:0]in30; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[3]_i_3_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_en_i_4_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire o_mem_we_i_3_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED ; + wire [0:0]\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_task_count[3]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_task_count[4]), + .I1(current_task_count[3]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(current_task_count[2]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[13]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h2100002100214200)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_3_n_0 ), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\FSM_onehot_state[12]_i_10_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[5]), + .I3(\current_task_count[5]_i_2_n_0 ), + .I4(o_mem_addr_OBUF[4]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_task_count[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF2)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[15]_i_3 + (.I0(i_task_id_IBUF[5]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[3]), + .I3(i_task_id_IBUF[4]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF1)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_4_n_0 ), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state[17]_i_4_n_0 ), + .I1(\FSM_onehot_state[17]_i_5_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[17]_i_4 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[17]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[17]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h20)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[17]_i_4_n_0 ), + .I2(\FSM_onehot_state[17]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000002)) + \FSM_onehot_state[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFFFEFF)) + \FSM_onehot_state[21]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(\FSM_onehot_state[21]_i_4_n_0 ), + .I2(\FSM_onehot_state[21]_i_5_n_0 ), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_7_n_0 ), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[15]), + .I3(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[10]), + .I1(o_mem_addr_OBUF[11]), + .I2(o_mem_addr_OBUF[9]), + .I3(o_mem_addr_OBUF[8]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'hBF0B)) + \FSM_onehot_state[21]_i_7 + (.I0(i_task_priority_IBUF[0]), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(i_task_priority_IBUF[1]), + .O(\FSM_onehot_state[21]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state[23]_i_4_n_0 ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[2] ), + .I5(\FSM_onehot_state[23]_i_5_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_2 + (.I0(o_mem_en_i_2_n_0), + .I1(\FSM_onehot_state[23]_i_6_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .I3(\FSM_onehot_state_reg_n_0_[7] ), + .I4(\FSM_onehot_state_reg_n_0_[14] ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[15] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[22] ), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[4] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA8)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[8]_i_2 + (.I0(current_task_count[7]), + .I1(current_task_count[6]), + .I2(current_task_count[3]), + .I3(current_task_count[4]), + .I4(current_task_count[5]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT6 #( + .INIT(64'hFF54FF54FFFFFF54)) + \current_mem_addr[0]_i_1 + (.I0(\current_mem_addr[0]_i_2_n_0 ), + .I1(\current_mem_addr[0]_i_3_n_0 ), + .I2(\current_mem_addr[0]_i_4_n_0 ), + .I3(\current_mem_addr[0]_i_5_n_0 ), + .I4(current_task_count[0]), + .I5(\current_mem_addr[0]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'hE)) + \current_mem_addr[0]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .O(\current_mem_addr[0]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'hFEEE)) + \current_mem_addr[0]_i_11 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000000000000777)) + \current_mem_addr[0]_i_2 + (.I0(in30[0]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .I4(\current_mem_addr[0]_i_7_n_0 ), + .I5(\current_mem_addr[3]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[0]_i_3 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + \current_mem_addr[0]_i_4 + (.I0(\current_mem_addr[0]_i_8_n_0 ), + .I1(\current_mem_addr[0]_i_9_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in30[0]), + .I4(\current_mem_addr[0]_i_10_n_0 ), + .I5(\current_mem_addr[0]_i_11_n_0 ), + .O(\current_mem_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAEFF00AEAE)) + \current_mem_addr[0]_i_5 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\current_mem_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \current_mem_addr[0]_i_6 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\current_mem_addr[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[0]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(o_mem_addr_OBUF[0]), + .O(\current_mem_addr[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h55555554)) + \current_mem_addr[0]_i_8 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[9] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[0]_i_9 + (.I0(\FSM_onehot_state[23]_i_4_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[8] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state_reg_n_0_[4] ), + .O(\current_mem_addr[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[10]_i_1 + (.I0(\current_mem_addr[10]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[10]), + .I3(\current_mem_addr[10]_i_3_n_0 ), + .I4(\current_mem_addr[10]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[10]_i_2 + (.I0(in26[10]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[10]_i_3 + (.I0(in30[10]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[10]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[10]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[10]), + .O(\current_mem_addr[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[11]_i_1 + (.I0(\current_mem_addr[11]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[11]), + .I3(\current_mem_addr[11]_i_3_n_0 ), + .I4(\current_mem_addr[11]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[11]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[11]_i_2 + (.I0(in26[11]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[11]_i_3 + (.I0(in27[11]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[11]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[11]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[11]), + .O(\current_mem_addr[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[11]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[12]_i_1 + (.I0(\current_mem_addr[12]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[12]), + .I3(\current_mem_addr[12]_i_3_n_0 ), + .I4(\current_mem_addr[12]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[12]_i_2 + (.I0(in26[12]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[12]_i_3 + (.I0(in30[12]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[12]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[12]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[12]), + .O(\current_mem_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[13]_i_1 + (.I0(\current_mem_addr[13]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[13]), + .I3(\current_mem_addr[13]_i_3_n_0 ), + .I4(\current_mem_addr[13]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[13]_i_2 + (.I0(in26[13]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[13]_i_3 + (.I0(in30[13]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[13]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[13]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[13]), + .O(\current_mem_addr[13]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[14]_i_1 + (.I0(\current_mem_addr[14]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[14]), + .I3(\current_mem_addr[14]_i_4_n_0 ), + .I4(\current_mem_addr[14]_i_5_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[14]_i_2 + (.I0(in26[14]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_mem_addr[14]_i_3 + (.I0(\current_mem_addr[14]_i_7_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\current_mem_addr[14]_i_8_n_0 ), + .O(\current_mem_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[14]_i_4 + (.I0(in30[14]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[14]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[14]_i_5 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[14]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[14]), + .O(\current_mem_addr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'h00000045)) + \current_mem_addr[14]_i_6 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[14]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[8] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\current_mem_addr[14]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .O(\current_mem_addr[14]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_mem_addr[15]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_16 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\current_mem_addr[15]_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_17 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_18 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_19 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \current_mem_addr[15]_i_2 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\current_mem_addr[15]_i_4_n_0 ), + .I3(\current_mem_addr[15]_i_5_n_0 ), + .I4(in26[15]), + .I5(\current_mem_addr[15]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_20 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_20_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_21 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_21_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_22 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[15]_i_22_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_23 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[15]_i_23_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_24 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[15]_i_24_n_0 )); + LUT6 #( + .INIT(64'h0000000011010000)) + \current_mem_addr[15]_i_3 + (.I0(\FSM_onehot_state[1]_i_3_n_0 ), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\current_mem_addr[14]_i_3_n_0 ), + .I5(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[15]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[15]), + .O(\current_mem_addr[15]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[15]_i_5 + (.I0(in27[15]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[15]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[15]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h45)) + \current_mem_addr[15]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_8 + (.I0(\current_mem_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\current_mem_addr[14]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[1]_i_1 + (.I0(\current_mem_addr[1]_i_2_n_0 ), + .I1(\current_mem_addr[1]_i_3_n_0 ), + .I2(\current_mem_addr[1]_i_4_n_0 ), + .I3(\current_mem_addr[1]_i_5_n_0 ), + .I4(\current_mem_addr[1]_i_6_n_0 ), + .I5(\current_mem_addr[1]_i_7_n_0 ), + .O(\current_mem_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[1]_i_2 + (.I0(current_task_count[1]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA8A8AAA8AAAAAAAA)) + \current_mem_addr[1]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\current_mem_addr[14]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[1]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[1]), + .O(\current_mem_addr[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[1]_i_5 + (.I0(in30[1]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[1]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[1]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[1]_i_7 + (.I0(in26[1]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[1]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFEEFE)) + \current_mem_addr[2]_i_1 + (.I0(\current_mem_addr[2]_i_2_n_0 ), + .I1(\current_mem_addr[2]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[2]), + .I3(\current_mem_addr[15]_i_3_n_0 ), + .I4(\current_mem_addr[2]_i_4_n_0 ), + .O(\current_mem_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[2]_i_2 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[2]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[2]), + .O(\current_mem_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[2]_i_3 + (.I0(in30[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[2]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[2]_i_4 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[2]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[2]), + .O(\current_mem_addr[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF0FFB0)) + \current_mem_addr[3]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\current_mem_addr[3]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[3]), + .I3(\current_mem_addr[3]_i_3_n_0 ), + .I4(\current_mem_addr[3]_i_4_n_0 ), + .I5(\current_mem_addr[3]_i_5_n_0 ), + .O(\current_mem_addr[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_10 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[3]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_11 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[3]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_12 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_12_n_0 )); + LUT5 #( + .INIT(32'h0000008A)) + \current_mem_addr[3]_i_2 + (.I0(\current_mem_addr[14]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[3]_i_3 + (.I0(\current_mem_addr[3]_i_6_n_0 ), + .I1(in23[3]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[3]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[3]), + .O(\current_mem_addr[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[3]_i_4 + (.I0(in23[3]), + .I1(\current_mem_addr[15]_i_8_n_0 ), + .O(\current_mem_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[3]_i_5 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[3]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[3]), + .O(\current_mem_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[3]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_mem_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[4]_i_1 + (.I0(\current_mem_addr[4]_i_2_n_0 ), + .I1(\current_mem_addr[4]_i_3_n_0 ), + .I2(\current_mem_addr[4]_i_4_n_0 ), + .I3(\current_mem_addr[4]_i_5_n_0 ), + .I4(\current_mem_addr[4]_i_6_n_0 ), + .I5(\current_mem_addr[4]_i_7_n_0 ), + .O(\current_mem_addr[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_10 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[4]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_11 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[4]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_12 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[4]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_13 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[4]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[4]_i_2 + (.I0(current_task_count[4]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[4]_i_3 + (.I0(in26[4]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[4]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[4]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[4]), + .O(\current_mem_addr[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[4]_i_5 + (.I0(in30[4]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in26[4]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in27[4]), + .O(\current_mem_addr[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hAA8A)) + \current_mem_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\current_mem_addr[14]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[5]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\current_mem_addr[5]_i_2_n_0 ), + .I3(\current_mem_addr[5]_i_3_n_0 ), + .I4(\current_mem_addr[5]_i_4_n_0 ), + .I5(\current_mem_addr[5]_i_5_n_0 ), + .O(\current_mem_addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[5]_i_2 + (.I0(in26[5]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[5]_i_3 + (.I0(in26[5]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[5]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[5]), + .O(\current_mem_addr[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[5]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[5]), + .O(\current_mem_addr[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[5]_i_5 + (.I0(current_task_count[5]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[6]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\current_mem_addr[6]_i_2_n_0 ), + .I3(\current_mem_addr[6]_i_3_n_0 ), + .I4(\current_mem_addr[6]_i_4_n_0 ), + .I5(\current_mem_addr[6]_i_5_n_0 ), + .O(\current_mem_addr[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[6]_i_2 + (.I0(in26[6]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[6]_i_3 + (.I0(in26[6]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[6]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[6]), + .O(\current_mem_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[6]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[6]), + .O(\current_mem_addr[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[6]_i_5 + (.I0(current_task_count[6]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[7]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\current_mem_addr[7]_i_2_n_0 ), + .I3(\current_mem_addr[7]_i_3_n_0 ), + .I4(\current_mem_addr[7]_i_4_n_0 ), + .I5(\current_mem_addr[7]_i_5_n_0 ), + .O(\current_mem_addr[7]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[7]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_11 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[7]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[7]_i_2 + (.I0(in26[7]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[7]_i_3 + (.I0(in26[7]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[7]), + .O(\current_mem_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[7]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[7]), + .O(\current_mem_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[7]_i_5 + (.I0(current_task_count[7]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[7]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[7]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[8]_i_1 + (.I0(\current_mem_addr[8]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[8]), + .I3(\current_mem_addr[8]_i_3_n_0 ), + .I4(\current_mem_addr[8]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[8]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[8]_i_2 + (.I0(in26[8]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[8]_i_3 + (.I0(in30[8]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[8]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[8]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[8]), + .O(\current_mem_addr[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[8]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[8]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[9]_i_1 + (.I0(\current_mem_addr[9]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[9]), + .I3(\current_mem_addr[9]_i_3_n_0 ), + .I4(\current_mem_addr[9]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[9]_i_2 + (.I0(in26[9]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[9]_i_3 + (.I0(in30[9]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[9]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[9]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[9]), + .O(\current_mem_addr[9]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_5 + (.CI(\current_mem_addr_reg[7]_i_6_n_0 ), + .CO({\current_mem_addr_reg[11]_i_5_n_0 ,\current_mem_addr_reg[11]_i_5_n_1 ,\current_mem_addr_reg[11]_i_5_n_2 ,\current_mem_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_6 + (.CI(\current_mem_addr_reg[7]_i_7_n_0 ), + .CO({\current_mem_addr_reg[11]_i_6_n_0 ,\current_mem_addr_reg[11]_i_6_n_1 ,\current_mem_addr_reg[11]_i_6_n_2 ,\current_mem_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in30[11:8]), + .S({\current_mem_addr[11]_i_7_n_0 ,\current_mem_addr[11]_i_8_n_0 ,\current_mem_addr[11]_i_9_n_0 ,\current_mem_addr[11]_i_10_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[12]_i_5 + (.CI(\current_mem_addr_reg[8]_i_6_n_0 ), + .CO({\current_mem_addr_reg[12]_i_5_n_0 ,\current_mem_addr_reg[12]_i_5_n_1 ,\current_mem_addr_reg[12]_i_5_n_2 ,\current_mem_addr_reg[12]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_10 + (.CI(\current_mem_addr_reg[11]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_10_n_1 ,\current_mem_addr_reg[15]_i_10_n_2 ,\current_mem_addr_reg[15]_i_10_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[15:12]), + .S(o_mem_addr_OBUF[15:12])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_11 + (.CI(\current_mem_addr_reg[11]_i_6_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_11_n_1 ,\current_mem_addr_reg[15]_i_11_n_2 ,\current_mem_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in30[15:12]), + .S({\current_mem_addr[15]_i_17_n_0 ,\current_mem_addr[15]_i_18_n_0 ,\current_mem_addr[15]_i_19_n_0 ,\current_mem_addr[15]_i_20_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_12 + (.CI(\current_mem_addr_reg[8]_i_5_n_0 ), + .CO({\current_mem_addr_reg[15]_i_12_n_0 ,\current_mem_addr_reg[15]_i_12_n_1 ,\current_mem_addr_reg[15]_i_12_n_2 ,\current_mem_addr_reg[15]_i_12_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in26[12:9]), + .S({\current_mem_addr[15]_i_21_n_0 ,\current_mem_addr[15]_i_22_n_0 ,\current_mem_addr[15]_i_23_n_0 ,\current_mem_addr[15]_i_24_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_6 + (.CI(\current_mem_addr_reg[15]_i_12_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_6_n_2 ,\current_mem_addr_reg[15]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED [3],in26[15:13]}), + .S({1'b0,\current_mem_addr[15]_i_13_n_0 ,\current_mem_addr[15]_i_14_n_0 ,\current_mem_addr[15]_i_15_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_9 + (.CI(\current_mem_addr_reg[12]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_9_n_2 ,\current_mem_addr_reg[15]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED [3],in23[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_7 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_7_n_0 ,\current_mem_addr_reg[3]_i_7_n_1 ,\current_mem_addr_reg[3]_i_7_n_2 ,\current_mem_addr_reg[3]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in27[3:1],in30[0]}), + .S({o_mem_addr_OBUF[3:2],\current_mem_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_8_n_0 ,\current_mem_addr_reg[3]_i_8_n_1 ,\current_mem_addr_reg[3]_i_8_n_2 ,\current_mem_addr_reg[3]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in30[3:1],\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED [0]}), + .S({\current_mem_addr[3]_i_10_n_0 ,\current_mem_addr[3]_i_11_n_0 ,\current_mem_addr[3]_i_12_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_8_n_0 ,\current_mem_addr_reg[4]_i_8_n_1 ,\current_mem_addr_reg[4]_i_8_n_2 ,\current_mem_addr_reg[4]_i_8_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in26[4:1]), + .S({\current_mem_addr[4]_i_10_n_0 ,\current_mem_addr[4]_i_11_n_0 ,\current_mem_addr[4]_i_12_n_0 ,\current_mem_addr[4]_i_13_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_9 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_9_n_0 ,\current_mem_addr_reg[4]_i_9_n_1 ,\current_mem_addr_reg[4]_i_9_n_2 ,\current_mem_addr_reg[4]_i_9_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_6 + (.CI(\current_mem_addr_reg[3]_i_7_n_0 ), + .CO({\current_mem_addr_reg[7]_i_6_n_0 ,\current_mem_addr_reg[7]_i_6_n_1 ,\current_mem_addr_reg[7]_i_6_n_2 ,\current_mem_addr_reg[7]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_7 + (.CI(\current_mem_addr_reg[3]_i_8_n_0 ), + .CO({\current_mem_addr_reg[7]_i_7_n_0 ,\current_mem_addr_reg[7]_i_7_n_1 ,\current_mem_addr_reg[7]_i_7_n_2 ,\current_mem_addr_reg[7]_i_7_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in30[7:4]), + .S({\current_mem_addr[7]_i_8_n_0 ,\current_mem_addr[7]_i_9_n_0 ,\current_mem_addr[7]_i_10_n_0 ,\current_mem_addr[7]_i_11_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_5 + (.CI(\current_mem_addr_reg[4]_i_8_n_0 ), + .CO({\current_mem_addr_reg[8]_i_5_n_0 ,\current_mem_addr_reg[8]_i_5_n_1 ,\current_mem_addr_reg[8]_i_5_n_2 ,\current_mem_addr_reg[8]_i_5_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in26[8:5]), + .S({\current_mem_addr[8]_i_7_n_0 ,\current_mem_addr[8]_i_8_n_0 ,\current_mem_addr[8]_i_9_n_0 ,\current_mem_addr[8]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_6 + (.CI(\current_mem_addr_reg[4]_i_9_n_0 ), + .CO({\current_mem_addr_reg[8]_i_6_n_0 ,\current_mem_addr_reg[8]_i_6_n_1 ,\current_mem_addr_reg[8]_i_6_n_2 ,\current_mem_addr_reg[8]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000EA)) + \current_popped_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555540)) + \current_popped_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(i_start_IBUF), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_popped_id[0]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_popped_id[1]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_popped_id[2]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_popped_id[3]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_popped_id[4]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_popped_id[5]), + .R(\current_popped_id[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'h54)) + \current_task_count[0]_i_1 + (.I0(current_task_count[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_task_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_task_count[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_task_count[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_task_count[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[3]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[2]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBEAA)) + \current_task_count[4]_i_1 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_task_count[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[4]), + .O(\current_task_count[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF44FF4F444444444)) + \current_task_count[5]_i_1 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[5]), + .I3(current_task_count[4]), + .I4(\current_task_count[5]_i_3_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_task_count[5]_i_2 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[2]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[3]), + .O(\current_task_count[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + \current_task_count[5]_i_3 + (.I0(current_task_count[3]), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(current_task_count[2]), + .O(\current_task_count[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h8FF48484)) + \current_task_count[6]_i_1 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[6]), + .I3(\current_task_count[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_task_count[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[0] ), + .O(\current_task_count[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4CFF4F084C084C0)) + \current_task_count[7]_i_2 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \current_task_count[7]_i_3 + (.I0(current_task_count[4]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[5]), + .O(\current_task_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_task_count[7]_i_4 + (.I0(current_task_count[2]), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[3]), + .I4(current_task_count[5]), + .I5(current_task_count[4]), + .O(\current_task_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[0]_i_1_n_0 ), + .Q(current_task_count[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[1]_i_1_n_0 ), + .Q(current_task_count[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[2]_i_1_n_0 ), + .Q(current_task_count[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[3]_i_1_n_0 ), + .Q(current_task_count[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[4]_i_1_n_0 ), + .Q(current_task_count[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[5]_i_1_n_0 ), + .Q(current_task_count[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[6]_i_1_n_0 ), + .Q(current_task_count[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[7]_i_2_n_0 ), + .Q(current_task_count[7]), + .R(1'b0)); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT6 #( + .INIT(64'hFFE0FFE0FFFFFFE0)) + \o_mem_data[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .I2(i_mem_data_IBUF[0]), + .I3(\o_mem_data[0]_i_2_n_0 ), + .I4(i_task_priority_IBUF[0]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_task_count[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFBAFFBAFFFFFFBA)) + \o_mem_data[1]_i_1 + (.I0(\o_mem_data[1]_i_2_n_0 ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[11]_i_1_n_0 ), + .I3(\o_mem_data[1]_i_4_n_0 ), + .I4(i_mem_data_IBUF[1]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAA8880)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[0]), + .I4(i_task_priority_IBUF[1]), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_3 + (.I0(current_task_count[0]), + .I1(current_task_count[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888F8888888888)) + \o_mem_data[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(\o_mem_data[3]_i_3_n_0 ), + .I4(i_task_id_IBUF[1]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h2AAA8000)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[2]), + .I4(current_task_count[3]), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888888000000008)) + \o_mem_data[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(current_task_count[3]), + .O(\o_mem_data[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\o_mem_data[4]_i_2_n_0 ), + .I3(i_task_id_IBUF[2]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBEAAAAAA)) + \o_mem_data[4]_i_2 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[5]), + .I2(\o_mem_data[5]_i_2_n_0 ), + .I3(i_task_id_IBUF[3]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4F444444)) + \o_mem_data[5]_i_2 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\o_mem_data[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5555555555555556)) + \o_mem_data[5]_i_3 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[3]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[2]), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[6]_i_1 + (.I0(\o_mem_data[6]_i_2_n_0 ), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_3_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_2 + (.I0(current_task_count[6]), + .I1(current_task_count[4]), + .I2(current_task_count[5]), + .I3(\current_task_count[5]_i_3_n_0 ), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h55554055)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h82)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_task_count[7]_i_3_n_0 ), + .I2(current_task_count[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'hE200)) + \o_mem_data[6]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(\FSM_onehot_state[21]_i_2_n_0 ), + .I2(i_mem_data_IBUF[6]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(i_task_id_IBUF[5]), + .I4(\o_mem_data[7]_i_3_n_0 ), + .I5(\o_mem_data[7]_i_4_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FB00FB)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\o_mem_data[7]_i_5_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\FSM_onehot_state[21]_i_2_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h88080080)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\current_task_count[7]_i_4_n_0 ), + .I3(current_task_count[6]), + .I4(current_task_count[7]), + .O(\o_mem_data[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA208)) + \o_mem_data[7]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[6]), + .I2(\current_task_count[7]_i_3_n_0 ), + .I3(current_task_count[7]), + .O(\o_mem_data[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \o_mem_data[7]_i_5 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_we_i_3_n_0), + .I3(o_mem_en_i_2_n_0), + .I4(o_mem_en_i_3_n_0), + .I5(\FSM_onehot_state[17]_i_3_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(\FSM_onehot_state[10]_i_1_n_0 ), + .I3(o_mem_en_i_4_n_0), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(o_mem_en_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + o_mem_en_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[22] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .O(o_mem_en_i_4_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hFFFD)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(o_mem_we_i_3_n_0), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(ctrl_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000111)) + o_mem_we_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[22] ), + .O(o_mem_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0444)) + o_mem_we_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(o_mem_we_i_3_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.wdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.wdb new file mode 100644 index 0000000..7439ade Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_func_synth.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing.tcl b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v new file mode 100644 index 0000000..876045e --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v @@ -0,0 +1,3225 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Fri Jun 12 14:53:04 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode funcsim -nolib -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_4_n_0 ; + wire \FSM_onehot_state[17]_i_5_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[21]_i_7_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire \current_mem_addr[0]_i_10_n_0 ; + wire \current_mem_addr[0]_i_11_n_0 ; + wire \current_mem_addr[0]_i_1_n_0 ; + wire \current_mem_addr[0]_i_2_n_0 ; + wire \current_mem_addr[0]_i_3_n_0 ; + wire \current_mem_addr[0]_i_4_n_0 ; + wire \current_mem_addr[0]_i_5_n_0 ; + wire \current_mem_addr[0]_i_6_n_0 ; + wire \current_mem_addr[0]_i_7_n_0 ; + wire \current_mem_addr[0]_i_8_n_0 ; + wire \current_mem_addr[0]_i_9_n_0 ; + wire \current_mem_addr[10]_i_1_n_0 ; + wire \current_mem_addr[10]_i_2_n_0 ; + wire \current_mem_addr[10]_i_3_n_0 ; + wire \current_mem_addr[10]_i_4_n_0 ; + wire \current_mem_addr[11]_i_10_n_0 ; + wire \current_mem_addr[11]_i_1_n_0 ; + wire \current_mem_addr[11]_i_2_n_0 ; + wire \current_mem_addr[11]_i_3_n_0 ; + wire \current_mem_addr[11]_i_4_n_0 ; + wire \current_mem_addr[11]_i_7_n_0 ; + wire \current_mem_addr[11]_i_8_n_0 ; + wire \current_mem_addr[11]_i_9_n_0 ; + wire \current_mem_addr[12]_i_1_n_0 ; + wire \current_mem_addr[12]_i_2_n_0 ; + wire \current_mem_addr[12]_i_3_n_0 ; + wire \current_mem_addr[12]_i_4_n_0 ; + wire \current_mem_addr[13]_i_1_n_0 ; + wire \current_mem_addr[13]_i_2_n_0 ; + wire \current_mem_addr[13]_i_3_n_0 ; + wire \current_mem_addr[13]_i_4_n_0 ; + wire \current_mem_addr[14]_i_1_n_0 ; + wire \current_mem_addr[14]_i_2_n_0 ; + wire \current_mem_addr[14]_i_3_n_0 ; + wire \current_mem_addr[14]_i_4_n_0 ; + wire \current_mem_addr[14]_i_5_n_0 ; + wire \current_mem_addr[14]_i_6_n_0 ; + wire \current_mem_addr[14]_i_7_n_0 ; + wire \current_mem_addr[14]_i_8_n_0 ; + wire \current_mem_addr[15]_i_13_n_0 ; + wire \current_mem_addr[15]_i_14_n_0 ; + wire \current_mem_addr[15]_i_15_n_0 ; + wire \current_mem_addr[15]_i_16_n_0 ; + wire \current_mem_addr[15]_i_17_n_0 ; + wire \current_mem_addr[15]_i_18_n_0 ; + wire \current_mem_addr[15]_i_19_n_0 ; + wire \current_mem_addr[15]_i_1_n_0 ; + wire \current_mem_addr[15]_i_20_n_0 ; + wire \current_mem_addr[15]_i_21_n_0 ; + wire \current_mem_addr[15]_i_22_n_0 ; + wire \current_mem_addr[15]_i_23_n_0 ; + wire \current_mem_addr[15]_i_24_n_0 ; + wire \current_mem_addr[15]_i_2_n_0 ; + wire \current_mem_addr[15]_i_3_n_0 ; + wire \current_mem_addr[15]_i_4_n_0 ; + wire \current_mem_addr[15]_i_5_n_0 ; + wire \current_mem_addr[15]_i_7_n_0 ; + wire \current_mem_addr[15]_i_8_n_0 ; + wire \current_mem_addr[1]_i_1_n_0 ; + wire \current_mem_addr[1]_i_2_n_0 ; + wire \current_mem_addr[1]_i_3_n_0 ; + wire \current_mem_addr[1]_i_4_n_0 ; + wire \current_mem_addr[1]_i_5_n_0 ; + wire \current_mem_addr[1]_i_6_n_0 ; + wire \current_mem_addr[1]_i_7_n_0 ; + wire \current_mem_addr[2]_i_1_n_0 ; + wire \current_mem_addr[2]_i_2_n_0 ; + wire \current_mem_addr[2]_i_3_n_0 ; + wire \current_mem_addr[2]_i_4_n_0 ; + wire \current_mem_addr[3]_i_10_n_0 ; + wire \current_mem_addr[3]_i_11_n_0 ; + wire \current_mem_addr[3]_i_12_n_0 ; + wire \current_mem_addr[3]_i_1_n_0 ; + wire \current_mem_addr[3]_i_2_n_0 ; + wire \current_mem_addr[3]_i_3_n_0 ; + wire \current_mem_addr[3]_i_4_n_0 ; + wire \current_mem_addr[3]_i_5_n_0 ; + wire \current_mem_addr[3]_i_6_n_0 ; + wire \current_mem_addr[3]_i_9_n_0 ; + wire \current_mem_addr[4]_i_10_n_0 ; + wire \current_mem_addr[4]_i_11_n_0 ; + wire \current_mem_addr[4]_i_12_n_0 ; + wire \current_mem_addr[4]_i_13_n_0 ; + wire \current_mem_addr[4]_i_1_n_0 ; + wire \current_mem_addr[4]_i_2_n_0 ; + wire \current_mem_addr[4]_i_3_n_0 ; + wire \current_mem_addr[4]_i_4_n_0 ; + wire \current_mem_addr[4]_i_5_n_0 ; + wire \current_mem_addr[4]_i_6_n_0 ; + wire \current_mem_addr[4]_i_7_n_0 ; + wire \current_mem_addr[5]_i_1_n_0 ; + wire \current_mem_addr[5]_i_2_n_0 ; + wire \current_mem_addr[5]_i_3_n_0 ; + wire \current_mem_addr[5]_i_4_n_0 ; + wire \current_mem_addr[5]_i_5_n_0 ; + wire \current_mem_addr[6]_i_1_n_0 ; + wire \current_mem_addr[6]_i_2_n_0 ; + wire \current_mem_addr[6]_i_3_n_0 ; + wire \current_mem_addr[6]_i_4_n_0 ; + wire \current_mem_addr[6]_i_5_n_0 ; + wire \current_mem_addr[7]_i_10_n_0 ; + wire \current_mem_addr[7]_i_11_n_0 ; + wire \current_mem_addr[7]_i_1_n_0 ; + wire \current_mem_addr[7]_i_2_n_0 ; + wire \current_mem_addr[7]_i_3_n_0 ; + wire \current_mem_addr[7]_i_4_n_0 ; + wire \current_mem_addr[7]_i_5_n_0 ; + wire \current_mem_addr[7]_i_8_n_0 ; + wire \current_mem_addr[7]_i_9_n_0 ; + wire \current_mem_addr[8]_i_10_n_0 ; + wire \current_mem_addr[8]_i_1_n_0 ; + wire \current_mem_addr[8]_i_2_n_0 ; + wire \current_mem_addr[8]_i_3_n_0 ; + wire \current_mem_addr[8]_i_4_n_0 ; + wire \current_mem_addr[8]_i_7_n_0 ; + wire \current_mem_addr[8]_i_8_n_0 ; + wire \current_mem_addr[8]_i_9_n_0 ; + wire \current_mem_addr[9]_i_1_n_0 ; + wire \current_mem_addr[9]_i_2_n_0 ; + wire \current_mem_addr[9]_i_3_n_0 ; + wire \current_mem_addr[9]_i_4_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_1 ; + wire \current_mem_addr_reg[11]_i_5_n_2 ; + wire \current_mem_addr_reg[11]_i_5_n_3 ; + wire \current_mem_addr_reg[11]_i_6_n_0 ; + wire \current_mem_addr_reg[11]_i_6_n_1 ; + wire \current_mem_addr_reg[11]_i_6_n_2 ; + wire \current_mem_addr_reg[11]_i_6_n_3 ; + wire \current_mem_addr_reg[12]_i_5_n_0 ; + wire \current_mem_addr_reg[12]_i_5_n_1 ; + wire \current_mem_addr_reg[12]_i_5_n_2 ; + wire \current_mem_addr_reg[12]_i_5_n_3 ; + wire \current_mem_addr_reg[15]_i_10_n_1 ; + wire \current_mem_addr_reg[15]_i_10_n_2 ; + wire \current_mem_addr_reg[15]_i_10_n_3 ; + wire \current_mem_addr_reg[15]_i_11_n_1 ; + wire \current_mem_addr_reg[15]_i_11_n_2 ; + wire \current_mem_addr_reg[15]_i_11_n_3 ; + wire \current_mem_addr_reg[15]_i_12_n_0 ; + wire \current_mem_addr_reg[15]_i_12_n_1 ; + wire \current_mem_addr_reg[15]_i_12_n_2 ; + wire \current_mem_addr_reg[15]_i_12_n_3 ; + wire \current_mem_addr_reg[15]_i_6_n_2 ; + wire \current_mem_addr_reg[15]_i_6_n_3 ; + wire \current_mem_addr_reg[15]_i_9_n_2 ; + wire \current_mem_addr_reg[15]_i_9_n_3 ; + wire \current_mem_addr_reg[3]_i_7_n_0 ; + wire \current_mem_addr_reg[3]_i_7_n_1 ; + wire \current_mem_addr_reg[3]_i_7_n_2 ; + wire \current_mem_addr_reg[3]_i_7_n_3 ; + wire \current_mem_addr_reg[3]_i_8_n_0 ; + wire \current_mem_addr_reg[3]_i_8_n_1 ; + wire \current_mem_addr_reg[3]_i_8_n_2 ; + wire \current_mem_addr_reg[3]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_8_n_0 ; + wire \current_mem_addr_reg[4]_i_8_n_1 ; + wire \current_mem_addr_reg[4]_i_8_n_2 ; + wire \current_mem_addr_reg[4]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_9_n_0 ; + wire \current_mem_addr_reg[4]_i_9_n_1 ; + wire \current_mem_addr_reg[4]_i_9_n_2 ; + wire \current_mem_addr_reg[4]_i_9_n_3 ; + wire \current_mem_addr_reg[7]_i_6_n_0 ; + wire \current_mem_addr_reg[7]_i_6_n_1 ; + wire \current_mem_addr_reg[7]_i_6_n_2 ; + wire \current_mem_addr_reg[7]_i_6_n_3 ; + wire \current_mem_addr_reg[7]_i_7_n_0 ; + wire \current_mem_addr_reg[7]_i_7_n_1 ; + wire \current_mem_addr_reg[7]_i_7_n_2 ; + wire \current_mem_addr_reg[7]_i_7_n_3 ; + wire \current_mem_addr_reg[8]_i_5_n_0 ; + wire \current_mem_addr_reg[8]_i_5_n_1 ; + wire \current_mem_addr_reg[8]_i_5_n_2 ; + wire \current_mem_addr_reg[8]_i_5_n_3 ; + wire \current_mem_addr_reg[8]_i_6_n_0 ; + wire \current_mem_addr_reg[8]_i_6_n_1 ; + wire \current_mem_addr_reg[8]_i_6_n_2 ; + wire \current_mem_addr_reg[8]_i_6_n_3 ; + wire [5:0]current_popped_id; + wire \current_popped_id[5]_i_1_n_0 ; + wire \current_popped_id[5]_i_2_n_0 ; + wire [7:0]current_task_count; + wire \current_task_count[0]_i_1_n_0 ; + wire \current_task_count[1]_i_1_n_0 ; + wire \current_task_count[2]_i_1_n_0 ; + wire \current_task_count[3]_i_1_n_0 ; + wire \current_task_count[4]_i_1_n_0 ; + wire \current_task_count[4]_i_2_n_0 ; + wire \current_task_count[5]_i_1_n_0 ; + wire \current_task_count[5]_i_2_n_0 ; + wire \current_task_count[5]_i_3_n_0 ; + wire \current_task_count[6]_i_1_n_0 ; + wire \current_task_count[7]_i_1_n_0 ; + wire \current_task_count[7]_i_2_n_0 ; + wire \current_task_count[7]_i_3_n_0 ; + wire \current_task_count[7]_i_4_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in23; + wire [15:1]in26; + wire [15:1]in27; + wire [15:0]in30; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[3]_i_3_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_en_i_4_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire o_mem_we_i_3_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED ; + wire [0:0]\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_task_count[3]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_task_count[4]), + .I1(current_task_count[3]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(current_task_count[2]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[13]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h2100002100214200)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_3_n_0 ), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\FSM_onehot_state[12]_i_10_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[5]), + .I3(\current_task_count[5]_i_2_n_0 ), + .I4(o_mem_addr_OBUF[4]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_task_count[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF2)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[15]_i_3 + (.I0(i_task_id_IBUF[5]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[3]), + .I3(i_task_id_IBUF[4]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF1)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_4_n_0 ), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state[17]_i_4_n_0 ), + .I1(\FSM_onehot_state[17]_i_5_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[17]_i_4 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[17]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[17]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h20)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[17]_i_4_n_0 ), + .I2(\FSM_onehot_state[17]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000002)) + \FSM_onehot_state[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFFFEFF)) + \FSM_onehot_state[21]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(\FSM_onehot_state[21]_i_4_n_0 ), + .I2(\FSM_onehot_state[21]_i_5_n_0 ), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_7_n_0 ), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[15]), + .I3(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[10]), + .I1(o_mem_addr_OBUF[11]), + .I2(o_mem_addr_OBUF[9]), + .I3(o_mem_addr_OBUF[8]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'hBF0B)) + \FSM_onehot_state[21]_i_7 + (.I0(i_task_priority_IBUF[0]), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(i_task_priority_IBUF[1]), + .O(\FSM_onehot_state[21]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state[23]_i_4_n_0 ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[2] ), + .I5(\FSM_onehot_state[23]_i_5_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_2 + (.I0(o_mem_en_i_2_n_0), + .I1(\FSM_onehot_state[23]_i_6_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .I3(\FSM_onehot_state_reg_n_0_[7] ), + .I4(\FSM_onehot_state_reg_n_0_[14] ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[15] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[22] ), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[4] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA8)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[8]_i_2 + (.I0(current_task_count[7]), + .I1(current_task_count[6]), + .I2(current_task_count[3]), + .I3(current_task_count[4]), + .I4(current_task_count[5]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT6 #( + .INIT(64'hFF54FF54FFFFFF54)) + \current_mem_addr[0]_i_1 + (.I0(\current_mem_addr[0]_i_2_n_0 ), + .I1(\current_mem_addr[0]_i_3_n_0 ), + .I2(\current_mem_addr[0]_i_4_n_0 ), + .I3(\current_mem_addr[0]_i_5_n_0 ), + .I4(current_task_count[0]), + .I5(\current_mem_addr[0]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'hE)) + \current_mem_addr[0]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .O(\current_mem_addr[0]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'hFEEE)) + \current_mem_addr[0]_i_11 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000000000000777)) + \current_mem_addr[0]_i_2 + (.I0(in30[0]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .I4(\current_mem_addr[0]_i_7_n_0 ), + .I5(\current_mem_addr[3]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[0]_i_3 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + \current_mem_addr[0]_i_4 + (.I0(\current_mem_addr[0]_i_8_n_0 ), + .I1(\current_mem_addr[0]_i_9_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in30[0]), + .I4(\current_mem_addr[0]_i_10_n_0 ), + .I5(\current_mem_addr[0]_i_11_n_0 ), + .O(\current_mem_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAEFF00AEAE)) + \current_mem_addr[0]_i_5 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\current_mem_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \current_mem_addr[0]_i_6 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\current_mem_addr[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[0]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(o_mem_addr_OBUF[0]), + .O(\current_mem_addr[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h55555554)) + \current_mem_addr[0]_i_8 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[9] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[0]_i_9 + (.I0(\FSM_onehot_state[23]_i_4_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[8] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state_reg_n_0_[4] ), + .O(\current_mem_addr[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[10]_i_1 + (.I0(\current_mem_addr[10]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[10]), + .I3(\current_mem_addr[10]_i_3_n_0 ), + .I4(\current_mem_addr[10]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[10]_i_2 + (.I0(in26[10]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[10]_i_3 + (.I0(in30[10]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[10]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[10]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[10]), + .O(\current_mem_addr[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[11]_i_1 + (.I0(\current_mem_addr[11]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[11]), + .I3(\current_mem_addr[11]_i_3_n_0 ), + .I4(\current_mem_addr[11]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[11]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[11]_i_2 + (.I0(in26[11]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[11]_i_3 + (.I0(in27[11]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[11]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[11]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[11]), + .O(\current_mem_addr[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[11]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[12]_i_1 + (.I0(\current_mem_addr[12]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[12]), + .I3(\current_mem_addr[12]_i_3_n_0 ), + .I4(\current_mem_addr[12]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[12]_i_2 + (.I0(in26[12]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[12]_i_3 + (.I0(in30[12]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[12]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[12]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[12]), + .O(\current_mem_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[13]_i_1 + (.I0(\current_mem_addr[13]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[13]), + .I3(\current_mem_addr[13]_i_3_n_0 ), + .I4(\current_mem_addr[13]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[13]_i_2 + (.I0(in26[13]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[13]_i_3 + (.I0(in30[13]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[13]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[13]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[13]), + .O(\current_mem_addr[13]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[14]_i_1 + (.I0(\current_mem_addr[14]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[14]), + .I3(\current_mem_addr[14]_i_4_n_0 ), + .I4(\current_mem_addr[14]_i_5_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[14]_i_2 + (.I0(in26[14]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_mem_addr[14]_i_3 + (.I0(\current_mem_addr[14]_i_7_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\current_mem_addr[14]_i_8_n_0 ), + .O(\current_mem_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[14]_i_4 + (.I0(in30[14]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[14]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[14]_i_5 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[14]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[14]), + .O(\current_mem_addr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'h00000045)) + \current_mem_addr[14]_i_6 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[14]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[8] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\current_mem_addr[14]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .O(\current_mem_addr[14]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_mem_addr[15]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_16 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\current_mem_addr[15]_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_17 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_18 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_19 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \current_mem_addr[15]_i_2 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\current_mem_addr[15]_i_4_n_0 ), + .I3(\current_mem_addr[15]_i_5_n_0 ), + .I4(in26[15]), + .I5(\current_mem_addr[15]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_20 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_20_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_21 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_21_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_22 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[15]_i_22_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_23 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[15]_i_23_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_24 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[15]_i_24_n_0 )); + LUT6 #( + .INIT(64'h0000000011010000)) + \current_mem_addr[15]_i_3 + (.I0(\FSM_onehot_state[1]_i_3_n_0 ), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\current_mem_addr[14]_i_3_n_0 ), + .I5(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[15]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[15]), + .O(\current_mem_addr[15]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[15]_i_5 + (.I0(in27[15]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[15]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[15]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h45)) + \current_mem_addr[15]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_8 + (.I0(\current_mem_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\current_mem_addr[14]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[1]_i_1 + (.I0(\current_mem_addr[1]_i_2_n_0 ), + .I1(\current_mem_addr[1]_i_3_n_0 ), + .I2(\current_mem_addr[1]_i_4_n_0 ), + .I3(\current_mem_addr[1]_i_5_n_0 ), + .I4(\current_mem_addr[1]_i_6_n_0 ), + .I5(\current_mem_addr[1]_i_7_n_0 ), + .O(\current_mem_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[1]_i_2 + (.I0(current_task_count[1]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA8A8AAA8AAAAAAAA)) + \current_mem_addr[1]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\current_mem_addr[14]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[1]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[1]), + .O(\current_mem_addr[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[1]_i_5 + (.I0(in30[1]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[1]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[1]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[1]_i_7 + (.I0(in26[1]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[1]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFEEFE)) + \current_mem_addr[2]_i_1 + (.I0(\current_mem_addr[2]_i_2_n_0 ), + .I1(\current_mem_addr[2]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[2]), + .I3(\current_mem_addr[15]_i_3_n_0 ), + .I4(\current_mem_addr[2]_i_4_n_0 ), + .O(\current_mem_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[2]_i_2 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[2]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[2]), + .O(\current_mem_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[2]_i_3 + (.I0(in30[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[2]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[2]_i_4 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[2]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[2]), + .O(\current_mem_addr[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF0FFB0)) + \current_mem_addr[3]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\current_mem_addr[3]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[3]), + .I3(\current_mem_addr[3]_i_3_n_0 ), + .I4(\current_mem_addr[3]_i_4_n_0 ), + .I5(\current_mem_addr[3]_i_5_n_0 ), + .O(\current_mem_addr[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_10 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[3]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_11 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[3]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_12 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_12_n_0 )); + LUT5 #( + .INIT(32'h0000008A)) + \current_mem_addr[3]_i_2 + (.I0(\current_mem_addr[14]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[3]_i_3 + (.I0(\current_mem_addr[3]_i_6_n_0 ), + .I1(in23[3]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[3]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[3]), + .O(\current_mem_addr[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[3]_i_4 + (.I0(in23[3]), + .I1(\current_mem_addr[15]_i_8_n_0 ), + .O(\current_mem_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[3]_i_5 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[3]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[3]), + .O(\current_mem_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[3]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_mem_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[4]_i_1 + (.I0(\current_mem_addr[4]_i_2_n_0 ), + .I1(\current_mem_addr[4]_i_3_n_0 ), + .I2(\current_mem_addr[4]_i_4_n_0 ), + .I3(\current_mem_addr[4]_i_5_n_0 ), + .I4(\current_mem_addr[4]_i_6_n_0 ), + .I5(\current_mem_addr[4]_i_7_n_0 ), + .O(\current_mem_addr[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_10 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[4]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_11 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[4]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_12 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[4]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_13 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[4]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[4]_i_2 + (.I0(current_task_count[4]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[4]_i_3 + (.I0(in26[4]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[4]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[4]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[4]), + .O(\current_mem_addr[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[4]_i_5 + (.I0(in30[4]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in26[4]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in27[4]), + .O(\current_mem_addr[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hAA8A)) + \current_mem_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\current_mem_addr[14]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[5]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\current_mem_addr[5]_i_2_n_0 ), + .I3(\current_mem_addr[5]_i_3_n_0 ), + .I4(\current_mem_addr[5]_i_4_n_0 ), + .I5(\current_mem_addr[5]_i_5_n_0 ), + .O(\current_mem_addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[5]_i_2 + (.I0(in26[5]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[5]_i_3 + (.I0(in26[5]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[5]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[5]), + .O(\current_mem_addr[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[5]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[5]), + .O(\current_mem_addr[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[5]_i_5 + (.I0(current_task_count[5]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[6]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\current_mem_addr[6]_i_2_n_0 ), + .I3(\current_mem_addr[6]_i_3_n_0 ), + .I4(\current_mem_addr[6]_i_4_n_0 ), + .I5(\current_mem_addr[6]_i_5_n_0 ), + .O(\current_mem_addr[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[6]_i_2 + (.I0(in26[6]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[6]_i_3 + (.I0(in26[6]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[6]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[6]), + .O(\current_mem_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[6]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[6]), + .O(\current_mem_addr[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[6]_i_5 + (.I0(current_task_count[6]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[7]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\current_mem_addr[7]_i_2_n_0 ), + .I3(\current_mem_addr[7]_i_3_n_0 ), + .I4(\current_mem_addr[7]_i_4_n_0 ), + .I5(\current_mem_addr[7]_i_5_n_0 ), + .O(\current_mem_addr[7]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[7]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_11 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[7]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[7]_i_2 + (.I0(in26[7]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[7]_i_3 + (.I0(in26[7]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[7]), + .O(\current_mem_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[7]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[7]), + .O(\current_mem_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[7]_i_5 + (.I0(current_task_count[7]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[7]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[7]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[8]_i_1 + (.I0(\current_mem_addr[8]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[8]), + .I3(\current_mem_addr[8]_i_3_n_0 ), + .I4(\current_mem_addr[8]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[8]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[8]_i_2 + (.I0(in26[8]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[8]_i_3 + (.I0(in30[8]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[8]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[8]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[8]), + .O(\current_mem_addr[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[8]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[8]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[9]_i_1 + (.I0(\current_mem_addr[9]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[9]), + .I3(\current_mem_addr[9]_i_3_n_0 ), + .I4(\current_mem_addr[9]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[9]_i_2 + (.I0(in26[9]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[9]_i_3 + (.I0(in30[9]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[9]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[9]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[9]), + .O(\current_mem_addr[9]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_5 + (.CI(\current_mem_addr_reg[7]_i_6_n_0 ), + .CO({\current_mem_addr_reg[11]_i_5_n_0 ,\current_mem_addr_reg[11]_i_5_n_1 ,\current_mem_addr_reg[11]_i_5_n_2 ,\current_mem_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_6 + (.CI(\current_mem_addr_reg[7]_i_7_n_0 ), + .CO({\current_mem_addr_reg[11]_i_6_n_0 ,\current_mem_addr_reg[11]_i_6_n_1 ,\current_mem_addr_reg[11]_i_6_n_2 ,\current_mem_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in30[11:8]), + .S({\current_mem_addr[11]_i_7_n_0 ,\current_mem_addr[11]_i_8_n_0 ,\current_mem_addr[11]_i_9_n_0 ,\current_mem_addr[11]_i_10_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[12]_i_5 + (.CI(\current_mem_addr_reg[8]_i_6_n_0 ), + .CO({\current_mem_addr_reg[12]_i_5_n_0 ,\current_mem_addr_reg[12]_i_5_n_1 ,\current_mem_addr_reg[12]_i_5_n_2 ,\current_mem_addr_reg[12]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_10 + (.CI(\current_mem_addr_reg[11]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_10_n_1 ,\current_mem_addr_reg[15]_i_10_n_2 ,\current_mem_addr_reg[15]_i_10_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[15:12]), + .S(o_mem_addr_OBUF[15:12])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_11 + (.CI(\current_mem_addr_reg[11]_i_6_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_11_n_1 ,\current_mem_addr_reg[15]_i_11_n_2 ,\current_mem_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in30[15:12]), + .S({\current_mem_addr[15]_i_17_n_0 ,\current_mem_addr[15]_i_18_n_0 ,\current_mem_addr[15]_i_19_n_0 ,\current_mem_addr[15]_i_20_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_12 + (.CI(\current_mem_addr_reg[8]_i_5_n_0 ), + .CO({\current_mem_addr_reg[15]_i_12_n_0 ,\current_mem_addr_reg[15]_i_12_n_1 ,\current_mem_addr_reg[15]_i_12_n_2 ,\current_mem_addr_reg[15]_i_12_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in26[12:9]), + .S({\current_mem_addr[15]_i_21_n_0 ,\current_mem_addr[15]_i_22_n_0 ,\current_mem_addr[15]_i_23_n_0 ,\current_mem_addr[15]_i_24_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_6 + (.CI(\current_mem_addr_reg[15]_i_12_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_6_n_2 ,\current_mem_addr_reg[15]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED [3],in26[15:13]}), + .S({1'b0,\current_mem_addr[15]_i_13_n_0 ,\current_mem_addr[15]_i_14_n_0 ,\current_mem_addr[15]_i_15_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_9 + (.CI(\current_mem_addr_reg[12]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_9_n_2 ,\current_mem_addr_reg[15]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED [3],in23[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_7 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_7_n_0 ,\current_mem_addr_reg[3]_i_7_n_1 ,\current_mem_addr_reg[3]_i_7_n_2 ,\current_mem_addr_reg[3]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in27[3:1],in30[0]}), + .S({o_mem_addr_OBUF[3:2],\current_mem_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_8_n_0 ,\current_mem_addr_reg[3]_i_8_n_1 ,\current_mem_addr_reg[3]_i_8_n_2 ,\current_mem_addr_reg[3]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in30[3:1],\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED [0]}), + .S({\current_mem_addr[3]_i_10_n_0 ,\current_mem_addr[3]_i_11_n_0 ,\current_mem_addr[3]_i_12_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_8_n_0 ,\current_mem_addr_reg[4]_i_8_n_1 ,\current_mem_addr_reg[4]_i_8_n_2 ,\current_mem_addr_reg[4]_i_8_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in26[4:1]), + .S({\current_mem_addr[4]_i_10_n_0 ,\current_mem_addr[4]_i_11_n_0 ,\current_mem_addr[4]_i_12_n_0 ,\current_mem_addr[4]_i_13_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_9 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_9_n_0 ,\current_mem_addr_reg[4]_i_9_n_1 ,\current_mem_addr_reg[4]_i_9_n_2 ,\current_mem_addr_reg[4]_i_9_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_6 + (.CI(\current_mem_addr_reg[3]_i_7_n_0 ), + .CO({\current_mem_addr_reg[7]_i_6_n_0 ,\current_mem_addr_reg[7]_i_6_n_1 ,\current_mem_addr_reg[7]_i_6_n_2 ,\current_mem_addr_reg[7]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_7 + (.CI(\current_mem_addr_reg[3]_i_8_n_0 ), + .CO({\current_mem_addr_reg[7]_i_7_n_0 ,\current_mem_addr_reg[7]_i_7_n_1 ,\current_mem_addr_reg[7]_i_7_n_2 ,\current_mem_addr_reg[7]_i_7_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in30[7:4]), + .S({\current_mem_addr[7]_i_8_n_0 ,\current_mem_addr[7]_i_9_n_0 ,\current_mem_addr[7]_i_10_n_0 ,\current_mem_addr[7]_i_11_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_5 + (.CI(\current_mem_addr_reg[4]_i_8_n_0 ), + .CO({\current_mem_addr_reg[8]_i_5_n_0 ,\current_mem_addr_reg[8]_i_5_n_1 ,\current_mem_addr_reg[8]_i_5_n_2 ,\current_mem_addr_reg[8]_i_5_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in26[8:5]), + .S({\current_mem_addr[8]_i_7_n_0 ,\current_mem_addr[8]_i_8_n_0 ,\current_mem_addr[8]_i_9_n_0 ,\current_mem_addr[8]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_6 + (.CI(\current_mem_addr_reg[4]_i_9_n_0 ), + .CO({\current_mem_addr_reg[8]_i_6_n_0 ,\current_mem_addr_reg[8]_i_6_n_1 ,\current_mem_addr_reg[8]_i_6_n_2 ,\current_mem_addr_reg[8]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000EA)) + \current_popped_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555540)) + \current_popped_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(i_start_IBUF), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_popped_id[0]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_popped_id[1]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_popped_id[2]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_popped_id[3]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_popped_id[4]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_popped_id[5]), + .R(\current_popped_id[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'h54)) + \current_task_count[0]_i_1 + (.I0(current_task_count[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_task_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_task_count[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_task_count[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_task_count[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[3]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[2]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBEAA)) + \current_task_count[4]_i_1 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_task_count[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[4]), + .O(\current_task_count[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF44FF4F444444444)) + \current_task_count[5]_i_1 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[5]), + .I3(current_task_count[4]), + .I4(\current_task_count[5]_i_3_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_task_count[5]_i_2 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[2]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[3]), + .O(\current_task_count[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + \current_task_count[5]_i_3 + (.I0(current_task_count[3]), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(current_task_count[2]), + .O(\current_task_count[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h8FF48484)) + \current_task_count[6]_i_1 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[6]), + .I3(\current_task_count[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_task_count[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[0] ), + .O(\current_task_count[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4CFF4F084C084C0)) + \current_task_count[7]_i_2 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \current_task_count[7]_i_3 + (.I0(current_task_count[4]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[5]), + .O(\current_task_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_task_count[7]_i_4 + (.I0(current_task_count[2]), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[3]), + .I4(current_task_count[5]), + .I5(current_task_count[4]), + .O(\current_task_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[0]_i_1_n_0 ), + .Q(current_task_count[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[1]_i_1_n_0 ), + .Q(current_task_count[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[2]_i_1_n_0 ), + .Q(current_task_count[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[3]_i_1_n_0 ), + .Q(current_task_count[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[4]_i_1_n_0 ), + .Q(current_task_count[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[5]_i_1_n_0 ), + .Q(current_task_count[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[6]_i_1_n_0 ), + .Q(current_task_count[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[7]_i_2_n_0 ), + .Q(current_task_count[7]), + .R(1'b0)); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT6 #( + .INIT(64'hFFE0FFE0FFFFFFE0)) + \o_mem_data[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .I2(i_mem_data_IBUF[0]), + .I3(\o_mem_data[0]_i_2_n_0 ), + .I4(i_task_priority_IBUF[0]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_task_count[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFBAFFBAFFFFFFBA)) + \o_mem_data[1]_i_1 + (.I0(\o_mem_data[1]_i_2_n_0 ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[11]_i_1_n_0 ), + .I3(\o_mem_data[1]_i_4_n_0 ), + .I4(i_mem_data_IBUF[1]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAA8880)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[0]), + .I4(i_task_priority_IBUF[1]), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_3 + (.I0(current_task_count[0]), + .I1(current_task_count[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888F8888888888)) + \o_mem_data[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(\o_mem_data[3]_i_3_n_0 ), + .I4(i_task_id_IBUF[1]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h2AAA8000)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[2]), + .I4(current_task_count[3]), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888888000000008)) + \o_mem_data[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(current_task_count[3]), + .O(\o_mem_data[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\o_mem_data[4]_i_2_n_0 ), + .I3(i_task_id_IBUF[2]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBEAAAAAA)) + \o_mem_data[4]_i_2 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[5]), + .I2(\o_mem_data[5]_i_2_n_0 ), + .I3(i_task_id_IBUF[3]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4F444444)) + \o_mem_data[5]_i_2 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\o_mem_data[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5555555555555556)) + \o_mem_data[5]_i_3 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[3]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[2]), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[6]_i_1 + (.I0(\o_mem_data[6]_i_2_n_0 ), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_3_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_2 + (.I0(current_task_count[6]), + .I1(current_task_count[4]), + .I2(current_task_count[5]), + .I3(\current_task_count[5]_i_3_n_0 ), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h55554055)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h82)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_task_count[7]_i_3_n_0 ), + .I2(current_task_count[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'hE200)) + \o_mem_data[6]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(\FSM_onehot_state[21]_i_2_n_0 ), + .I2(i_mem_data_IBUF[6]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(i_task_id_IBUF[5]), + .I4(\o_mem_data[7]_i_3_n_0 ), + .I5(\o_mem_data[7]_i_4_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FB00FB)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\o_mem_data[7]_i_5_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\FSM_onehot_state[21]_i_2_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h88080080)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\current_task_count[7]_i_4_n_0 ), + .I3(current_task_count[6]), + .I4(current_task_count[7]), + .O(\o_mem_data[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA208)) + \o_mem_data[7]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[6]), + .I2(\current_task_count[7]_i_3_n_0 ), + .I3(current_task_count[7]), + .O(\o_mem_data[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \o_mem_data[7]_i_5 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_we_i_3_n_0), + .I3(o_mem_en_i_2_n_0), + .I4(o_mem_en_i_3_n_0), + .I5(\FSM_onehot_state[17]_i_3_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(\FSM_onehot_state[10]_i_1_n_0 ), + .I3(o_mem_en_i_4_n_0), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(o_mem_en_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + o_mem_en_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[22] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .O(o_mem_en_i_4_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hFFFD)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(o_mem_we_i_3_n_0), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(ctrl_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000111)) + o_mem_we_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[22] ), + .O(o_mem_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0444)) + o_mem_we_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(o_mem_we_i_3_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.wdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.wdb new file mode 100644 index 0000000..8ce2834 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log new file mode 100644 index 0000000..b0f8eb8 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log @@ -0,0 +1,152 @@ +Time resolution is 1 ps +Note: === GRUPPO 0: Reset === +Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.0 OK: reset base +Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.1 OK: reset asincrono durante operazione +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 1: Inserimento === +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.0 OK: insert in lista vuota +Time: 3670100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.1 OK: insert con priorità massima in testa +Time: 6010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.2 OK: insert con priorità minima in fondo +Time: 8230100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali +Time: 10450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo +Time: 12950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.5 OK: insert con ID duplicato ignorato +Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 2: Rimozione === +Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0 +Time: 16990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto +Time: 18930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato +Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 3: Decremento priorità === +Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.0 OK: decremento su lista vuota +Time: 23130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.1 OK: saturazione a priorità 3 +Time: 25350100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica +Time: 27870100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino) +Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 4: Svuota lista === +Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.0 OK: svuota lista popolata +Time: 33050100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.1 OK: svuota lista già vuota +Time: 34730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0 +Time: 36690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto +Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 5: Sequenze composite === +Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto +Time: 41490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.1 OK: ordinamento completo con priorità miste +Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 6: Rimozione multipla e ordinamento === +Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota +Time: 48310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1 +Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 7: Decremento ripetuto === +Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3 +Time: 53430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente +Time: 57010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.1 OK: decremento su lista con un solo task +Time: 59330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota +Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 8: Insert dopo rimozione e casi limite === +Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto +Time: 64950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato +Time: 67830100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato +Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 9: o_task_id per OP diverso da 01 === +Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1 +Time: 72490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1 +Time: 74450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1 +Time: 76330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1 +Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 10: Protocollo, reset avanzato, stress === +Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset +Time: 79750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert) +Time: 92030100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato +Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 11: Insert con ID=0 === +Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato +Time: 96290100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato +Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 12: Capacita' massima 63 task === +Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata +Time: 231450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati +Time: 235970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.2 OK: drain di 63 task nell'ordine atteso +Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 13: Stale memory e duplicati ai bordi === +Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.0 OK: re-insert di ID appena rimosso +Time: 365710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.1 OK: duplicato in prima posizione ignorato +Time: 368130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.2 OK: duplicato in ultima posizione ignorato +Time: 368250100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.3 OK: re-insert stesso ID dopo clear +Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 14: Reset asincrono avanzato === +Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.0 OK: reset a meta' shift di OP=01 +Time: 373150100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.1 OK: reset durante la scrittura del count +Time: 375930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.2 OK: reset durante OP=00 +Time: 378470100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.3 OK: reset mentre DONE=1 +Time: 380550100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.4 OK: reset corto non allineato +Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 15: START lento dopo DONE=1 === +Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.0 OK: nessun doppio pop con START lento +Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.1 OK: nessun doppio age con START lento +Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.2 OK: insert con START tenuto 2 cicli extra +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: ====================================== + Tutti i test edge case sono PASSATI +====================================== +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616 +Note: === GRUPPO 0: Reset === +Time: 389890 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: FAIL [0.0 reset-addr0] addr=0 expected=0x0 actual=0x1 +Time: 390040 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 390040 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 420 +INFO: xsimkernel Simulation Memory Usage: 294496 KB (Peak: 343308 KB), Simulation CPU Usage: 890 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh new file mode 100755 index 0000000..4f29b67 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Fri Jun 12 15:48:20 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log" +xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xelab.pb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xelab.pb new file mode 100644 index 0000000..5689620 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xelab.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt new file mode 100644 index 0000000..1de1768 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_edge_func_synth" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..694014c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c new file mode 100644 index 0000000..22669a6 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c @@ -0,0 +1,479 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void execute_1264(char*, char *); +IKI_DLLESPEC extern void execute_1265(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2351(char*, char *); +IKI_DLLESPEC extern void execute_2353(char*, char *); +IKI_DLLESPEC extern void execute_2354(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_2407(char*, char *); +IKI_DLLESPEC extern void execute_2408(char*, char *); +IKI_DLLESPEC extern void execute_2409(char*, char *); +IKI_DLLESPEC extern void execute_2410(char*, char *); +IKI_DLLESPEC extern void execute_2411(char*, char *); +IKI_DLLESPEC extern void execute_2412(char*, char *); +IKI_DLLESPEC extern void execute_2413(char*, char *); +IKI_DLLESPEC extern void execute_2414(char*, char *); +IKI_DLLESPEC extern void execute_2415(char*, char *); +IKI_DLLESPEC extern void execute_29(char*, char *); +IKI_DLLESPEC extern void execute_1276(char*, char *); +IKI_DLLESPEC extern void execute_1277(char*, char *); +IKI_DLLESPEC extern void execute_1278(char*, char *); +IKI_DLLESPEC extern void execute_1279(char*, char *); +IKI_DLLESPEC extern void execute_1275(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_43(char*, char *); +IKI_DLLESPEC extern void execute_44(char*, char *); +IKI_DLLESPEC extern void execute_47(char*, char *); +IKI_DLLESPEC extern void execute_1293(char*, char *); +IKI_DLLESPEC extern void execute_1294(char*, char *); +IKI_DLLESPEC extern void execute_1292(char*, char *); +IKI_DLLESPEC extern void execute_50(char*, char *); +IKI_DLLESPEC extern void execute_1296(char*, char *); +IKI_DLLESPEC extern void execute_1297(char*, char *); +IKI_DLLESPEC extern void execute_1298(char*, char *); +IKI_DLLESPEC extern void execute_1299(char*, char *); +IKI_DLLESPEC extern void execute_1300(char*, char *); +IKI_DLLESPEC extern void execute_1301(char*, char *); +IKI_DLLESPEC extern void execute_1302(char*, char *); +IKI_DLLESPEC extern void execute_1303(char*, char *); +IKI_DLLESPEC extern void execute_1295(char*, char *); +IKI_DLLESPEC extern void execute_56(char*, char *); +IKI_DLLESPEC extern void execute_57(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_198(char*, char *); +IKI_DLLESPEC extern void execute_199(char*, char *); +IKI_DLLESPEC extern void execute_1454(char*, char *); +IKI_DLLESPEC extern void execute_1455(char*, char *); +IKI_DLLESPEC extern void execute_1456(char*, char *); +IKI_DLLESPEC extern void execute_1457(char*, char *); +IKI_DLLESPEC extern void execute_201(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_203(char*, char *); +IKI_DLLESPEC extern void execute_1458(char*, char *); +IKI_DLLESPEC extern void execute_1459(char*, char *); +IKI_DLLESPEC extern void execute_1460(char*, char *); +IKI_DLLESPEC extern void execute_1461(char*, char *); +IKI_DLLESPEC extern void execute_1470(char*, char *); +IKI_DLLESPEC extern void execute_1471(char*, char *); +IKI_DLLESPEC extern void execute_1472(char*, char *); +IKI_DLLESPEC extern void execute_1475(char*, char *); +IKI_DLLESPEC extern void execute_1476(char*, char *); +IKI_DLLESPEC extern void execute_1477(char*, char *); +IKI_DLLESPEC extern void execute_1478(char*, char *); +IKI_DLLESPEC extern void execute_738(char*, char *); +IKI_DLLESPEC extern void execute_739(char*, char *); +IKI_DLLESPEC extern void execute_740(char*, char *); +IKI_DLLESPEC extern void execute_1845(char*, char *); +IKI_DLLESPEC extern void execute_1846(char*, char *); +IKI_DLLESPEC extern void execute_1847(char*, char *); +IKI_DLLESPEC extern void execute_2103(char*, char *); +IKI_DLLESPEC extern void execute_942(char*, char *); +IKI_DLLESPEC extern void execute_2104(char*, char *); +IKI_DLLESPEC extern void execute_984(char*, char *); +IKI_DLLESPEC extern void execute_2125(char*, char *); +IKI_DLLESPEC extern void execute_2126(char*, char *); +IKI_DLLESPEC extern void execute_2127(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_785(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_791(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_797(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_803(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_827(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_833(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_839(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_845(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_851(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_857(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_863(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_869(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_875(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_881(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_887(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_893(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_899(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_905(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_911(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_917(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_923(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_929(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_935(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_941(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1741(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1747(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1753(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1776(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1790(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1796(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1802(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1852(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1858(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1864(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1892(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1915(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1921(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1950(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1973(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2000(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2005(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2010(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2015(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2020(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2025(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2449(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2455(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2461(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2467(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2473(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2479(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2485(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2526(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2559(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2580(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2585(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2590(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2595(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2600(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2605(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[350] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)execute_1264, (funcp)execute_1265, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_2350, (funcp)execute_2351, (funcp)execute_2353, (funcp)execute_2354, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_2407, (funcp)execute_2408, (funcp)execute_2409, (funcp)execute_2410, (funcp)execute_2411, (funcp)execute_2412, (funcp)execute_2413, (funcp)execute_2414, (funcp)execute_2415, (funcp)execute_29, (funcp)execute_1276, (funcp)execute_1277, (funcp)execute_1278, (funcp)execute_1279, (funcp)execute_1275, (funcp)execute_38, (funcp)execute_39, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_43, (funcp)execute_44, (funcp)execute_47, (funcp)execute_1293, (funcp)execute_1294, (funcp)execute_1292, (funcp)execute_50, (funcp)execute_1296, (funcp)execute_1297, (funcp)execute_1298, (funcp)execute_1299, (funcp)execute_1300, (funcp)execute_1301, (funcp)execute_1302, (funcp)execute_1303, (funcp)execute_1295, (funcp)execute_56, (funcp)execute_57, (funcp)execute_197, (funcp)execute_198, (funcp)execute_199, (funcp)execute_1454, (funcp)execute_1455, (funcp)execute_1456, (funcp)execute_1457, (funcp)execute_201, (funcp)execute_202, (funcp)execute_203, (funcp)execute_1458, (funcp)execute_1459, (funcp)execute_1460, (funcp)execute_1461, (funcp)execute_1470, (funcp)execute_1471, (funcp)execute_1472, (funcp)execute_1475, (funcp)execute_1476, (funcp)execute_1477, (funcp)execute_1478, (funcp)execute_738, (funcp)execute_739, (funcp)execute_740, (funcp)execute_1845, (funcp)execute_1846, (funcp)execute_1847, (funcp)execute_2103, (funcp)execute_942, (funcp)execute_2104, (funcp)execute_984, (funcp)execute_2125, (funcp)execute_2126, (funcp)execute_2127, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_54, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_165, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_360, (funcp)transaction_397, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_785, (funcp)transaction_791, (funcp)transaction_797, (funcp)transaction_803, (funcp)transaction_827, (funcp)transaction_833, (funcp)transaction_839, (funcp)transaction_845, (funcp)transaction_851, (funcp)transaction_857, (funcp)transaction_863, (funcp)transaction_869, (funcp)transaction_875, (funcp)transaction_881, (funcp)transaction_887, (funcp)transaction_893, (funcp)transaction_899, (funcp)transaction_905, (funcp)transaction_911, (funcp)transaction_917, (funcp)transaction_923, (funcp)transaction_929, (funcp)transaction_935, (funcp)transaction_941, (funcp)transaction_1741, (funcp)transaction_1747, (funcp)transaction_1753, (funcp)transaction_1776, (funcp)transaction_1790, (funcp)transaction_1796, (funcp)transaction_1802, (funcp)transaction_1852, (funcp)transaction_1858, (funcp)transaction_1864, (funcp)transaction_1892, (funcp)transaction_1915, (funcp)transaction_1921, (funcp)transaction_1927, (funcp)transaction_1950, (funcp)transaction_1973, (funcp)transaction_2000, (funcp)transaction_2005, (funcp)transaction_2010, (funcp)transaction_2015, (funcp)transaction_2020, (funcp)transaction_2025, (funcp)transaction_2140, (funcp)transaction_2146, (funcp)transaction_2152, (funcp)transaction_2158, (funcp)transaction_2164, (funcp)transaction_2170, (funcp)transaction_2176, (funcp)transaction_2182, (funcp)transaction_2200, (funcp)transaction_2449, (funcp)transaction_2455, (funcp)transaction_2461, (funcp)transaction_2467, (funcp)transaction_2473, (funcp)transaction_2479, (funcp)transaction_2485, (funcp)transaction_2491, (funcp)transaction_2526, (funcp)transaction_2559, (funcp)transaction_2580, (funcp)transaction_2585, (funcp)transaction_2590, (funcp)transaction_2595, (funcp)transaction_2600, (funcp)transaction_2605}; +const int NumRelocateId= 350; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc", (void **)funcTab, 350); + iki_vhdl_file_variable_register(dp + 1091216); + iki_vhdl_file_variable_register(dp + 1091272); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096624, dp + 1639704, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096680, dp + 1640096, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096736, dp + 1640208, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096968, dp + 1640320, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096888, dp + 1640432, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096928, dp + 1639984, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1097584, dp + 1639872, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_edge_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..e0ed8d7 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.dbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.dbg new file mode 100644 index 0000000..1ebb4ca Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.mem b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.mem new file mode 100644 index 0000000..f1c2885 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.reloc b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.reloc new file mode 100644 index 0000000..9b7b454 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rlx b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rlx new file mode 100644 index 0000000..1108a1a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 1042013717637638161 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_func_synth/xsimk\" \"xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rtti b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rtti new file mode 100644 index 0000000..f039b6a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.svtype b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.svtype new file mode 100644 index 0000000..57a1c98 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.type b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.type new file mode 100644 index 0000000..3435d32 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.xdbg new file mode 100644 index 0000000..2fd407e Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimSettings.ini new file mode 100644 index 0000000..5862680 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=156 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109 +OBJECT_NAME_COLUMN_WIDTH=191 +OBJECT_VALUE_COLUMN_WIDTH=1024 +OBJECT_DATA_TYPE_COLUMN_WIDTH=76 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimk b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimk new file mode 100755 index 0000000..0c47047 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log new file mode 100644 index 0000000..3a44e3d --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_edge_func_synth/xsimk -simmode gui -wdb project_tb_edge_func_synth.wdb -simrunnum 0 -socket 41063 +Design successfully loaded +Design Loading Memory Usage: 199732 KB (Peak: 199732 KB) +Design Loading CPU Usage: 700 ms +Simulation completed +Simulation Memory Usage: 294496 KB (Peak: 343308 KB) +Simulation CPU Usage: 890 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt new file mode 100644 index 0000000..be910a6 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_func_synth" "xil_defaultlib.project_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..d781cd0 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.c new file mode 100644 index 0000000..1f9408a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.c @@ -0,0 +1,478 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1260(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2341(char*, char *); +IKI_DLLESPEC extern void execute_2342(char*, char *); +IKI_DLLESPEC extern void execute_2344(char*, char *); +IKI_DLLESPEC extern void execute_2345(char*, char *); +IKI_DLLESPEC extern void execute_2346(char*, char *); +IKI_DLLESPEC extern void execute_2347(char*, char *); +IKI_DLLESPEC extern void execute_2348(char*, char *); +IKI_DLLESPEC extern void execute_2349(char*, char *); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2351(char*, char *); +IKI_DLLESPEC extern void execute_2352(char*, char *); +IKI_DLLESPEC extern void execute_2353(char*, char *); +IKI_DLLESPEC extern void execute_2354(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_1267(char*, char *); +IKI_DLLESPEC extern void execute_1268(char*, char *); +IKI_DLLESPEC extern void execute_1269(char*, char *); +IKI_DLLESPEC extern void execute_1270(char*, char *); +IKI_DLLESPEC extern void execute_1266(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_42(char*, char *); +IKI_DLLESPEC extern void execute_43(char*, char *); +IKI_DLLESPEC extern void execute_46(char*, char *); +IKI_DLLESPEC extern void execute_1284(char*, char *); +IKI_DLLESPEC extern void execute_1285(char*, char *); +IKI_DLLESPEC extern void execute_1283(char*, char *); +IKI_DLLESPEC extern void execute_49(char*, char *); +IKI_DLLESPEC extern void execute_1287(char*, char *); +IKI_DLLESPEC extern void execute_1288(char*, char *); +IKI_DLLESPEC extern void execute_1289(char*, char *); +IKI_DLLESPEC extern void execute_1290(char*, char *); +IKI_DLLESPEC extern void execute_1291(char*, char *); +IKI_DLLESPEC extern void execute_1292(char*, char *); +IKI_DLLESPEC extern void execute_1293(char*, char *); +IKI_DLLESPEC extern void execute_1294(char*, char *); +IKI_DLLESPEC extern void execute_1286(char*, char *); +IKI_DLLESPEC extern void execute_55(char*, char *); +IKI_DLLESPEC extern void execute_56(char*, char *); +IKI_DLLESPEC extern void execute_196(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_198(char*, char *); +IKI_DLLESPEC extern void execute_1445(char*, char *); +IKI_DLLESPEC extern void execute_1446(char*, char *); +IKI_DLLESPEC extern void execute_1447(char*, char *); +IKI_DLLESPEC extern void execute_1448(char*, char *); +IKI_DLLESPEC extern void execute_200(char*, char *); +IKI_DLLESPEC extern void execute_201(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_1449(char*, char *); +IKI_DLLESPEC extern void execute_1450(char*, char *); +IKI_DLLESPEC extern void execute_1451(char*, char *); +IKI_DLLESPEC extern void execute_1452(char*, char *); +IKI_DLLESPEC extern void execute_1461(char*, char *); +IKI_DLLESPEC extern void execute_1462(char*, char *); +IKI_DLLESPEC extern void execute_1463(char*, char *); +IKI_DLLESPEC extern void execute_1466(char*, char *); +IKI_DLLESPEC extern void execute_1467(char*, char *); +IKI_DLLESPEC extern void execute_1468(char*, char *); +IKI_DLLESPEC extern void execute_1469(char*, char *); +IKI_DLLESPEC extern void execute_737(char*, char *); +IKI_DLLESPEC extern void execute_738(char*, char *); +IKI_DLLESPEC extern void execute_739(char*, char *); +IKI_DLLESPEC extern void execute_1836(char*, char *); +IKI_DLLESPEC extern void execute_1837(char*, char *); +IKI_DLLESPEC extern void execute_1838(char*, char *); +IKI_DLLESPEC extern void execute_2094(char*, char *); +IKI_DLLESPEC extern void execute_941(char*, char *); +IKI_DLLESPEC extern void execute_2095(char*, char *); +IKI_DLLESPEC extern void execute_983(char*, char *); +IKI_DLLESPEC extern void execute_2116(char*, char *); +IKI_DLLESPEC extern void execute_2117(char*, char *); +IKI_DLLESPEC extern void execute_2118(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_222(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_223(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_224(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_233(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_234(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_235(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_260(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_330(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_331(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_361(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_363(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_408(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_409(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_788(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_794(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_800(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_806(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_830(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_836(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_842(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_848(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_854(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_860(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_866(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_872(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_878(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_884(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_890(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_896(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_902(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_908(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_914(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_920(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_926(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_932(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_938(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_944(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1744(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1750(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1756(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1779(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1793(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1799(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1805(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1855(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1861(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1867(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1895(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1918(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1924(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1930(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1953(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1976(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2003(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2008(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2013(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2018(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2023(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2028(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2143(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2452(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2458(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2464(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2470(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2476(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2482(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2488(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2494(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2529(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2562(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2583(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2588(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2593(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2598(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2603(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2608(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[349] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1260, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_2341, (funcp)execute_2342, (funcp)execute_2344, (funcp)execute_2345, (funcp)execute_2346, (funcp)execute_2347, (funcp)execute_2348, (funcp)execute_2349, (funcp)execute_2350, (funcp)execute_2351, (funcp)execute_2352, (funcp)execute_2353, (funcp)execute_2354, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_28, (funcp)execute_1267, (funcp)execute_1268, (funcp)execute_1269, (funcp)execute_1270, (funcp)execute_1266, (funcp)execute_37, (funcp)execute_38, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_42, (funcp)execute_43, (funcp)execute_46, (funcp)execute_1284, (funcp)execute_1285, (funcp)execute_1283, (funcp)execute_49, (funcp)execute_1287, (funcp)execute_1288, (funcp)execute_1289, (funcp)execute_1290, (funcp)execute_1291, (funcp)execute_1292, (funcp)execute_1293, (funcp)execute_1294, (funcp)execute_1286, (funcp)execute_55, (funcp)execute_56, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_1445, (funcp)execute_1446, (funcp)execute_1447, (funcp)execute_1448, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_1449, (funcp)execute_1450, (funcp)execute_1451, (funcp)execute_1452, (funcp)execute_1461, (funcp)execute_1462, (funcp)execute_1463, (funcp)execute_1466, (funcp)execute_1467, (funcp)execute_1468, (funcp)execute_1469, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_1836, (funcp)execute_1837, (funcp)execute_1838, (funcp)execute_2094, (funcp)execute_941, (funcp)execute_2095, (funcp)execute_983, (funcp)execute_2116, (funcp)execute_2117, (funcp)execute_2118, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_43, (funcp)transaction_46, (funcp)transaction_48, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_168, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_222, (funcp)transaction_223, (funcp)transaction_224, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_233, (funcp)transaction_234, (funcp)transaction_235, (funcp)transaction_253, (funcp)transaction_254, (funcp)transaction_260, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_329, (funcp)transaction_330, (funcp)transaction_331, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_361, (funcp)transaction_363, (funcp)transaction_400, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_407, (funcp)transaction_408, (funcp)transaction_409, (funcp)transaction_788, (funcp)transaction_794, (funcp)transaction_800, (funcp)transaction_806, (funcp)transaction_830, (funcp)transaction_836, (funcp)transaction_842, (funcp)transaction_848, (funcp)transaction_854, (funcp)transaction_860, (funcp)transaction_866, (funcp)transaction_872, (funcp)transaction_878, (funcp)transaction_884, (funcp)transaction_890, (funcp)transaction_896, (funcp)transaction_902, (funcp)transaction_908, (funcp)transaction_914, (funcp)transaction_920, (funcp)transaction_926, (funcp)transaction_932, (funcp)transaction_938, (funcp)transaction_944, (funcp)transaction_1744, (funcp)transaction_1750, (funcp)transaction_1756, (funcp)transaction_1779, (funcp)transaction_1793, (funcp)transaction_1799, (funcp)transaction_1805, (funcp)transaction_1855, (funcp)transaction_1861, (funcp)transaction_1867, (funcp)transaction_1895, (funcp)transaction_1918, (funcp)transaction_1924, (funcp)transaction_1930, (funcp)transaction_1953, (funcp)transaction_1976, (funcp)transaction_2003, (funcp)transaction_2008, (funcp)transaction_2013, (funcp)transaction_2018, (funcp)transaction_2023, (funcp)transaction_2028, (funcp)transaction_2143, (funcp)transaction_2149, (funcp)transaction_2155, (funcp)transaction_2161, (funcp)transaction_2167, (funcp)transaction_2173, (funcp)transaction_2179, (funcp)transaction_2185, (funcp)transaction_2203, (funcp)transaction_2452, (funcp)transaction_2458, (funcp)transaction_2464, (funcp)transaction_2470, (funcp)transaction_2476, (funcp)transaction_2482, (funcp)transaction_2488, (funcp)transaction_2494, (funcp)transaction_2529, (funcp)transaction_2562, (funcp)transaction_2583, (funcp)transaction_2588, (funcp)transaction_2593, (funcp)transaction_2598, (funcp)transaction_2603, (funcp)transaction_2608}; +const int NumRelocateId= 349; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_func_synth/xsim.reloc", (void **)funcTab, 349); + iki_vhdl_file_variable_register(dp + 1118456); + iki_vhdl_file_variable_register(dp + 1118512); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123864, dp + 1666144, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123920, dp + 1666536, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123976, dp + 1666648, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124208, dp + 1666760, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124128, dp + 1666872, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124168, dp + 1666424, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124488, dp + 1666312, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..f0103bf Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.dbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.dbg new file mode 100644 index 0000000..9f4c18c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.mem b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.mem new file mode 100644 index 0000000..e8fab5a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.reloc b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.reloc new file mode 100644 index 0000000..a61473a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rlx b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rlx new file mode 100644 index 0000000..90c74bb --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 17879923451979115244 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_func_synth xil_defaultlib.project_tb xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_func_synth/xsimk\" \"xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rtti b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rtti new file mode 100644 index 0000000..e50585f Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.svtype b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.svtype new file mode 100644 index 0000000..57a1c98 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.type b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.type new file mode 100644 index 0000000..7e485ec Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.xdbg new file mode 100644 index 0000000..b68520c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimSettings.ini new file mode 100644 index 0000000..f7d4ebb --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=240 +OBJECT_VALUE_COLUMN_WIDTH=5823 +OBJECT_DATA_TYPE_COLUMN_WIDTH=96 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimk b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimk new file mode 100755 index 0000000..16a0352 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimkernel.log new file mode 100644 index 0000000..46a05fc --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_func_synth/xsimk -simmode gui -wdb project_tb_func_synth.wdb -simrunnum 0 -socket 33153 +Design successfully loaded +Design Loading Memory Usage: 199644 KB (Peak: 199644 KB) +Design Loading CPU Usage: 710 ms +Simulation completed +Simulation Memory Usage: 288764 KB (Peak: 338912 KB) +Simulation CPU Usage: 720 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/Compile_Options.txt new file mode 100644 index 0000000..607e0d7 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_timing_func_synth" "xil_defaultlib.project_tb_timing" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..51da7b7 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.c new file mode 100644 index 0000000..dc98d9c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.c @@ -0,0 +1,478 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1260(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2344(char*, char *); +IKI_DLLESPEC extern void execute_2345(char*, char *); +IKI_DLLESPEC extern void execute_2347(char*, char *); +IKI_DLLESPEC extern void execute_2348(char*, char *); +IKI_DLLESPEC extern void execute_2349(char*, char *); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2351(char*, char *); +IKI_DLLESPEC extern void execute_2352(char*, char *); +IKI_DLLESPEC extern void execute_2353(char*, char *); +IKI_DLLESPEC extern void execute_2354(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_2407(char*, char *); +IKI_DLLESPEC extern void execute_2408(char*, char *); +IKI_DLLESPEC extern void execute_2409(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_1270(char*, char *); +IKI_DLLESPEC extern void execute_1271(char*, char *); +IKI_DLLESPEC extern void execute_1272(char*, char *); +IKI_DLLESPEC extern void execute_1273(char*, char *); +IKI_DLLESPEC extern void execute_1269(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_42(char*, char *); +IKI_DLLESPEC extern void execute_43(char*, char *); +IKI_DLLESPEC extern void execute_46(char*, char *); +IKI_DLLESPEC extern void execute_1287(char*, char *); +IKI_DLLESPEC extern void execute_1288(char*, char *); +IKI_DLLESPEC extern void execute_1286(char*, char *); +IKI_DLLESPEC extern void execute_49(char*, char *); +IKI_DLLESPEC extern void execute_1290(char*, char *); +IKI_DLLESPEC extern void execute_1291(char*, char *); +IKI_DLLESPEC extern void execute_1292(char*, char *); +IKI_DLLESPEC extern void execute_1293(char*, char *); +IKI_DLLESPEC extern void execute_1294(char*, char *); +IKI_DLLESPEC extern void execute_1295(char*, char *); +IKI_DLLESPEC extern void execute_1296(char*, char *); +IKI_DLLESPEC extern void execute_1297(char*, char *); +IKI_DLLESPEC extern void execute_1289(char*, char *); +IKI_DLLESPEC extern void execute_55(char*, char *); +IKI_DLLESPEC extern void execute_56(char*, char *); +IKI_DLLESPEC extern void execute_196(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_198(char*, char *); +IKI_DLLESPEC extern void execute_1448(char*, char *); +IKI_DLLESPEC extern void execute_1449(char*, char *); +IKI_DLLESPEC extern void execute_1450(char*, char *); +IKI_DLLESPEC extern void execute_1451(char*, char *); +IKI_DLLESPEC extern void execute_200(char*, char *); +IKI_DLLESPEC extern void execute_201(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_1452(char*, char *); +IKI_DLLESPEC extern void execute_1453(char*, char *); +IKI_DLLESPEC extern void execute_1454(char*, char *); +IKI_DLLESPEC extern void execute_1455(char*, char *); +IKI_DLLESPEC extern void execute_1464(char*, char *); +IKI_DLLESPEC extern void execute_1465(char*, char *); +IKI_DLLESPEC extern void execute_1466(char*, char *); +IKI_DLLESPEC extern void execute_1469(char*, char *); +IKI_DLLESPEC extern void execute_1470(char*, char *); +IKI_DLLESPEC extern void execute_1471(char*, char *); +IKI_DLLESPEC extern void execute_1472(char*, char *); +IKI_DLLESPEC extern void execute_737(char*, char *); +IKI_DLLESPEC extern void execute_738(char*, char *); +IKI_DLLESPEC extern void execute_739(char*, char *); +IKI_DLLESPEC extern void execute_1839(char*, char *); +IKI_DLLESPEC extern void execute_1840(char*, char *); +IKI_DLLESPEC extern void execute_1841(char*, char *); +IKI_DLLESPEC extern void execute_2097(char*, char *); +IKI_DLLESPEC extern void execute_941(char*, char *); +IKI_DLLESPEC extern void execute_2098(char*, char *); +IKI_DLLESPEC extern void execute_983(char*, char *); +IKI_DLLESPEC extern void execute_2119(char*, char *); +IKI_DLLESPEC extern void execute_2120(char*, char *); +IKI_DLLESPEC extern void execute_2121(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_785(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_791(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_797(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_803(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_827(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_833(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_839(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_845(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_851(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_857(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_863(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_869(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_875(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_881(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_887(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_893(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_899(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_905(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_911(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_917(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_923(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_929(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_935(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_941(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1741(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1747(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1753(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1776(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1790(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1796(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1802(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1852(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1858(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1864(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1892(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1915(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1921(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1950(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1973(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2000(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2005(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2010(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2015(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2020(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2025(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2449(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2455(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2461(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2467(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2473(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2479(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2485(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2526(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2559(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2580(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2585(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2590(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2595(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2600(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2605(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[349] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1260, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_2344, (funcp)execute_2345, (funcp)execute_2347, (funcp)execute_2348, (funcp)execute_2349, (funcp)execute_2350, (funcp)execute_2351, (funcp)execute_2352, (funcp)execute_2353, (funcp)execute_2354, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_2407, (funcp)execute_2408, (funcp)execute_2409, (funcp)execute_28, (funcp)execute_1270, (funcp)execute_1271, (funcp)execute_1272, (funcp)execute_1273, (funcp)execute_1269, (funcp)execute_37, (funcp)execute_38, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_42, (funcp)execute_43, (funcp)execute_46, (funcp)execute_1287, (funcp)execute_1288, (funcp)execute_1286, (funcp)execute_49, (funcp)execute_1290, (funcp)execute_1291, (funcp)execute_1292, (funcp)execute_1293, (funcp)execute_1294, (funcp)execute_1295, (funcp)execute_1296, (funcp)execute_1297, (funcp)execute_1289, (funcp)execute_55, (funcp)execute_56, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_1448, (funcp)execute_1449, (funcp)execute_1450, (funcp)execute_1451, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_1452, (funcp)execute_1453, (funcp)execute_1454, (funcp)execute_1455, (funcp)execute_1464, (funcp)execute_1465, (funcp)execute_1466, (funcp)execute_1469, (funcp)execute_1470, (funcp)execute_1471, (funcp)execute_1472, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_1839, (funcp)execute_1840, (funcp)execute_1841, (funcp)execute_2097, (funcp)execute_941, (funcp)execute_2098, (funcp)execute_983, (funcp)execute_2119, (funcp)execute_2120, (funcp)execute_2121, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_54, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_165, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_360, (funcp)transaction_397, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_785, (funcp)transaction_791, (funcp)transaction_797, (funcp)transaction_803, (funcp)transaction_827, (funcp)transaction_833, (funcp)transaction_839, (funcp)transaction_845, (funcp)transaction_851, (funcp)transaction_857, (funcp)transaction_863, (funcp)transaction_869, (funcp)transaction_875, (funcp)transaction_881, (funcp)transaction_887, (funcp)transaction_893, (funcp)transaction_899, (funcp)transaction_905, (funcp)transaction_911, (funcp)transaction_917, (funcp)transaction_923, (funcp)transaction_929, (funcp)transaction_935, (funcp)transaction_941, (funcp)transaction_1741, (funcp)transaction_1747, (funcp)transaction_1753, (funcp)transaction_1776, (funcp)transaction_1790, (funcp)transaction_1796, (funcp)transaction_1802, (funcp)transaction_1852, (funcp)transaction_1858, (funcp)transaction_1864, (funcp)transaction_1892, (funcp)transaction_1915, (funcp)transaction_1921, (funcp)transaction_1927, (funcp)transaction_1950, (funcp)transaction_1973, (funcp)transaction_2000, (funcp)transaction_2005, (funcp)transaction_2010, (funcp)transaction_2015, (funcp)transaction_2020, (funcp)transaction_2025, (funcp)transaction_2140, (funcp)transaction_2146, (funcp)transaction_2152, (funcp)transaction_2158, (funcp)transaction_2164, (funcp)transaction_2170, (funcp)transaction_2176, (funcp)transaction_2182, (funcp)transaction_2200, (funcp)transaction_2449, (funcp)transaction_2455, (funcp)transaction_2461, (funcp)transaction_2467, (funcp)transaction_2473, (funcp)transaction_2479, (funcp)transaction_2485, (funcp)transaction_2491, (funcp)transaction_2526, (funcp)transaction_2559, (funcp)transaction_2580, (funcp)transaction_2585, (funcp)transaction_2590, (funcp)transaction_2595, (funcp)transaction_2600, (funcp)transaction_2605}; +const int NumRelocateId= 349; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_timing_func_synth/xsim.reloc", (void **)funcTab, 349); + iki_vhdl_file_variable_register(dp + 1090920); + iki_vhdl_file_variable_register(dp + 1090976); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_timing_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096328, dp + 1638296, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096384, dp + 1638688, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096440, dp + 1638800, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096672, dp + 1638912, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096592, dp + 1639024, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096632, dp + 1638576, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1097288, dp + 1638464, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_timing_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_timing_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_timing_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_timing_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..995818a Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.dbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.dbg new file mode 100644 index 0000000..d6665f5 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.mem b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.mem new file mode 100644 index 0000000..2054262 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.reloc b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.reloc new file mode 100644 index 0000000..388106c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rlx b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rlx new file mode 100644 index 0000000..2c95435 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 6507029321917424264 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_timing_func_synth xil_defaultlib.project_tb_timing xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_timing_func_synth/xsimk\" \"xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rtti b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rtti new file mode 100644 index 0000000..434854d Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.svtype b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.svtype new file mode 100644 index 0000000..57a1c98 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.type b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.type new file mode 100644 index 0000000..21945ef Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.xdbg new file mode 100644 index 0000000..7287025 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimSettings.ini new file mode 100644 index 0000000..e7fdd4a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=168 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109 +OBJECT_NAME_COLUMN_WIDTH=191 +OBJECT_VALUE_COLUMN_WIDTH=5823 +OBJECT_DATA_TYPE_COLUMN_WIDTH=96 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimk b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimk new file mode 100755 index 0000000..3757426 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimkernel.log new file mode 100644 index 0000000..7d00b70 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_timing_func_synth/xsimk -simmode gui -wdb project_tb_timing_func_synth.wdb -simrunnum 0 -socket 53731 +Design successfully loaded +Design Loading Memory Usage: 199620 KB (Peak: 199620 KB) +Design Loading CPU Usage: 700 ms +Simulation completed +Simulation Memory Usage: 288740 KB (Peak: 338888 KB) +Simulation CPU Usage: 740 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..dcd9b33 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb new file mode 100644 index 0000000..f8184de Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb.vdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb.vdb new file mode 100644 index 0000000..6b76ca7 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb new file mode 100644 index 0000000..0a421b7 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb new file mode 100644 index 0000000..abb2154 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/project_tb_timing.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..4790ff5 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,8 @@ +0.7 +2020.2 +Nov 14 2025 +12:36:23 +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v,1781272095,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,, diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.ini b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvhdl.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvhdl.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvhdl.pb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvhdl.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvhdl.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.log new file mode 100644 index 0000000..3cd0469 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.log @@ -0,0 +1,3 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_reti_logiche +INFO: [VRFC 10-311] analyzing module glbl diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.pb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.pb new file mode 100644 index 0000000..8909131 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xvlog.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.log new file mode 100644 index 0000000..26dd174 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.log @@ -0,0 +1,5 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_reti_logiche +INFO: [VRFC 10-311] analyzing module glbl +INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'project_tb_edge' diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.sh b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.sh new file mode 100755 index 0000000..48a2478 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/compile.sh @@ -0,0 +1,32 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : compile.sh +# Simulator : AMD Vivado Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Thu Jun 11 14:51:00 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# compile Verilog/System Verilog design sources +echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj" +xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log + +# compile VHDL design sources +echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj" +xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log + +echo "Waiting for jobs to finish..." +echo "No pending jobs, compilation finished." diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.log new file mode 100644 index 0000000..ca92735 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.log @@ -0,0 +1,38 @@ +Vivado Simulator v2025.2 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT". +INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT". +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling package vl.vl_types +Compiling module xil_defaultlib.glbl +Compiling module simprims_ver.x_lut2_mux4 +Compiling module simprims_ver.LUT2 +Compiling module simprims_ver.LUT5 +Compiling module simprims_ver.LUT4 +Compiling module simprims_ver.x_lut1_mux2 +Compiling module simprims_ver.LUT1 +Compiling module simprims_ver.x_lut3_mux8 +Compiling module simprims_ver.LUT3 +Compiling module simprims_ver.LUT6 +Compiling module simprims_ver.FDPE_default +Compiling module simprims_ver.FDCE_default +Compiling module simprims_ver.CARRY4 +Compiling module simprims_ver.FDRE_default +Compiling module simprims_ver.BUFG +Compiling module simprims_ver.IBUF +Compiling module simprims_ver.OBUF +Compiling module xil_defaultlib.project_reti_logiche +Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge +Built simulation snapshot project_tb_edge_time_synth diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.sh b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.sh new file mode 100755 index 0000000..b355ec0 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Thu Jun 11 14:51:01 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge.tcl b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.sdf b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.sdf new file mode 100644 index 0000000..a909f02 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.sdf @@ -0,0 +1,6313 @@ +(DELAYFILE +(SDFVERSION "3.0" ) +(DESIGN "project_reti_logiche") +(DATE "Thu Jun 11 14:51:00 2026") +(VENDOR "XILINX") +(PROGRAM "Vivado") +(VERSION "2025.2") +(DIVIDER /) +(TIMESCALE 1ps) +(CELL + (CELLTYPE "LUT2") + (INSTANCE FSM_onehot_state\[10\]_i_1) + (DELAY + (PATHPULSE (50.0)) + (ABSOLUTE + (IOPATH I1 O (100.0:124.0:124.0) (100.0:124.0:124.0)) + (IOPATH I0 O (100.0:124.0:124.0) (100.0:124.0:124.0)) + ) + ) +) +(CELL + (CELLTYPE "LUT2") + (INSTANCE FSM_onehot_state\[11\]_i_1) + (DELAY + (PATHPULSE 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FSM_onehot_state_reg\[12\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[13\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[14\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[15\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[16\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[17\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[18\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[19\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[1\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[20\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[21\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[22\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[23\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[2\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[3\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[4\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[5\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[6\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[7\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[8\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_1/O FSM_onehot_state_reg\[9\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_2/O FSM_onehot_state\[23\]_i_1/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_3/O current_task_addr\[15\]_i_16/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_3/O FSM_onehot_state\[23\]_i_1/I1 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_4/O FSM_onehot_state\[23\]_i_1/I5 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_5/O FSM_onehot_state\[23\]_i_4/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_6/O FSM_onehot_state\[23\]_i_4/I5 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[23\]_i_7/O FSM_onehot_state\[23\]_i_6/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[3\]_i_1/O FSM_onehot_state_reg\[3\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT FSM_onehot_state\[4\]_i_1/O FSM_onehot_state_reg\[4\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT FSM_onehot_state\[6\]_i_1/O FSM_onehot_state_reg\[6\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT FSM_onehot_state\[7\]_i_1/O FSM_onehot_state_reg\[7\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_1/O FSM_onehot_state_reg\[8\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_1/O o_mem_en_i_1/I5 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O FSM_onehot_state\[1\]_i_5/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O FSM_onehot_state\[8\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O current_number_of_task\[4\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O o_mem_data\[7\]_i_4/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O current_number_of_task\[5\]_i_1/I3 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O o_mem_data\[5\]_i_2/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT FSM_onehot_state\[8\]_i_2/O o_mem_data\[6\]_i_6/I3 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q FSM_onehot_state\[23\]_i_2/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q o_done_i_1/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q o_mem_en_i_2/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q current_number_of_task\[7\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q current_task_id\[5\]_i_2/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q o_mem_we_i_1/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q FSM_onehot_state\[1\]_i_4/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[0\]/Q current_task_id\[5\]_i_1/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q FSM_onehot_state\[12\]_i_1/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q FSM_onehot_state\[11\]_i_1/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[0\]_i_1/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_task_addr\[7\]_i_5/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q o_mem_data\[0\]_i_2/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q o_mem_data\[1\]_i_4/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q o_mem_en_i_2/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q FSM_onehot_state\[23\]_i_4/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[1\]_i_1/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[4\]_i_1/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[7\]_i_1/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q o_mem_we_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[2\]_i_1/I4 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[6\]_i_1/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_task_addr\[15\]_i_6/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[3\]_i_1/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[5\]_i_1/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q current_number_of_task\[7\]_i_2/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[10\]/Q o_mem_data\[2\]_i_2/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[11\]/Q FSM_onehot_state\[1\]_i_4/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[11\]/Q current_task_addr\[15\]_i_16/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[11\]/Q FSM_onehot_state\[23\]_i_4/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q FSM_onehot_state_reg\[13\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[13\]_i_3/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q o_mem_data\[6\]_i_1/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q o_mem_data\[7\]_i_3/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[14\]_i_5/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q o_mem_data\[5\]_i_3/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[2\]_i_3/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[7\]_i_4/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q FSM_onehot_state\[23\]_i_6/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[0\]_i_4/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q o_mem_data\[1\]_i_3/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q o_mem_we_i_2/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[15\]_i_10/I5 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]/Q current_task_addr\[5\]_i_3/I5 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] FSM_onehot_state\[11\]_i_1/I0 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] current_task_addr\[7\]_i_5/I0 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_data\[6\]_i_3/I0 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] FSM_onehot_state\[12\]_i_1/I1 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] FSM_onehot_state\[6\]_i_1/I1 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_en_i_2/I1 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] current_number_of_task\[7\]_i_1/I2 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_we_i_1/I2 (748.5:819.0:819.0) (748.5:819.0:819.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_we_i_2/I3 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] FSM_onehot_state\[1\]_i_4/I4 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_data\[1\]_i_4/I4 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_data\[2\]_i_2/I4 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] current_task_addr\[15\]_i_6/I5 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_data\[0\]_i_2/I5 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_2/CO[1] o_mem_data\[5\]_i_3/I5 (464.4:520.0:520.0) (464.4:520.0:520.0)) + (INTERCONNECT FSM_onehot_state_reg\[12\]_i_3/CO[3] FSM_onehot_state_reg\[12\]_i_2/CI (8.6:9.0:9.0) (8.6:9.0:9.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q FSM_onehot_state\[10\]_i_1/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q FSM_onehot_state\[23\]_i_7/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[0\]_i_4/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[11\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[13\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[1\]_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[3\]_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[4\]_i_8/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[5\]_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[10\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[12\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[15\]_i_10/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[6\]_i_3/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[8\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[9\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[2\]_i_3/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[7\]_i_4/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q current_task_addr\[14\]_i_3/I5 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[13\]/Q o_mem_en_i_3/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[14\]/Q FSM_onehot_state\[15\]_i_3/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[14\]/Q FSM_onehot_state\[23\]_i_7/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[14\]/Q FSM_onehot_state\[1\]_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[14\]/Q current_task_addr\[15\]_i_7/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[15\]/Q FSM_onehot_state_reg\[16\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[15\]/Q FSM_onehot_state\[23\]_i_3/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[16\]/Q FSM_onehot_state\[17\]_i_3/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[16\]/Q FSM_onehot_state\[1\]_i_1/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[16\]/Q FSM_onehot_state\[23\]_i_6/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[16\]/Q current_task_addr\[15\]_i_7/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[17\]/Q FSM_onehot_state_reg\[18\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[17\]/Q FSM_onehot_state\[23\]_i_3/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q current_task_addr\[0\]_i_1/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q FSM_onehot_state\[23\]_i_6/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q current_task_addr\[15\]_i_12/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q FSM_onehot_state\[19\]_i_2/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q FSM_onehot_state\[21\]_i_1/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q current_task_addr\[14\]_i_3/I3 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q o_mem_data\[1\]_i_1/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q o_mem_data\[6\]_i_5/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[18\]/Q o_mem_we_i_2/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q FSM_onehot_state_reg\[20\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[1\]_i_1/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[2\]_i_1/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[3\]_i_1/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[4\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[0\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[1\]_i_3/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[2\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[3\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[6\]_i_4/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[7\]_i_5/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[5\]_i_1/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[6\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[7\]_i_2/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_data\[5\]_i_2/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[0\]_i_1/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_en_i_2/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q FSM_onehot_state\[23\]_i_4/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q current_number_of_task\[7\]_i_1/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[19\]/Q o_mem_we_i_1/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[1\]/Q FSM_onehot_state_reg\[2\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[1\]/Q o_task_id\[5\]_i_1/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[1\]/Q o_done_i_1/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[1\]/Q FSM_onehot_state\[23\]_i_5/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[1\]/Q current_task_addr\[15\]_i_16/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[20\]/Q FSM_onehot_state\[23\]_i_7/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[20\]/Q current_task_addr\[15\]_i_16/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[20\]/Q FSM_onehot_state\[1\]_i_4/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[10\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[12\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[15\]_i_10/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[6\]_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[8\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[9\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[0\]_i_4/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[2\]_i_3/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[7\]_i_4/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q FSM_onehot_state\[17\]_i_1/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q FSM_onehot_state\[23\]_i_1/I2 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[11\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[13\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[1\]_i_3/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[3\]_i_3/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[4\]_i_8/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[5\]_i_3/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q o_mem_en_i_3/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[21\]/Q current_task_addr\[14\]_i_5/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[22\]/Q FSM_onehot_state_reg\[23\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[22\]/Q FSM_onehot_state\[23\]_i_5/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[22\]/Q o_mem_en_i_3/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[22\]/Q current_number_of_task\[7\]_i_1/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[22\]/Q o_mem_we_i_1/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[23\]/Q FSM_onehot_state\[1\]_i_4/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[23\]/Q current_task_addr\[7\]_i_6/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[23\]/Q FSM_onehot_state\[23\]_i_4/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[23\]/Q current_task_addr\[15\]_i_6/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q FSM_onehot_state\[23\]_i_2/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q FSM_onehot_state\[3\]_i_1/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q FSM_onehot_state\[7\]_i_1/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q current_task_addr\[7\]_i_6/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q current_task_id\[5\]_i_1/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q FSM_onehot_state\[14\]_i_1/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q FSM_onehot_state\[22\]_i_1/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q current_task_addr\[15\]_i_6/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[2\]/Q current_task_id\[5\]_i_2/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[3\]/Q o_mem_en_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT FSM_onehot_state_reg\[3\]/Q FSM_onehot_state\[4\]_i_1/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[3\]/Q current_task_addr\[0\]_i_5/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[3\]/Q FSM_onehot_state\[23\]_i_1/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[4\]/Q FSM_onehot_state_reg\[5\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[4\]/Q FSM_onehot_state\[23\]_i_3/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q FSM_onehot_state\[6\]_i_1/I0 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q o_mem_data\[6\]_i_3/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q current_task_addr\[7\]_i_6/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q o_mem_we_i_2/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q FSM_onehot_state\[23\]_i_7/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q current_task_addr\[15\]_i_6/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q o_mem_data\[0\]_i_2/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q o_mem_data\[5\]_i_3/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q FSM_onehot_state\[1\]_i_4/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[5\]/Q o_mem_data\[1\]_i_4/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[6\]/Q FSM_onehot_state\[23\]_i_5/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT FSM_onehot_state_reg\[6\]/Q FSM_onehot_state\[4\]_i_1/I0 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FSM_onehot_state\[8\]_i_1/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT FSM_onehot_state_reg\[8\]/Q FSM_onehot_state_reg\[9\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT FSM_onehot_state_reg\[8\]/Q FSM_onehot_state\[23\]_i_3/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q current_task_addr\[15\]_i_12/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q FSM_onehot_state\[10\]_i_1/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q current_task_addr\[14\]_i_4/I1 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q o_mem_en_i_3/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q FSM_onehot_state\[23\]_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT FSM_onehot_state_reg\[9\]/Q current_task_id\[5\]_i_1/I4 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT 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current_number_of_task\[3\]_i_1/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[1\]/Q current_number_of_task\[5\]_i_2/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[1\]/Q current_number_of_task\[7\]_i_3/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[1\]/Q o_mem_data\[3\]_i_2/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q FSM_onehot_state\[12\]_i_9/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[7\]_i_4/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_task_addr\[15\]_i_9/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q FSM_onehot_state\[12\]_i_11/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[2\]_i_1/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[4\]_i_2/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q o_mem_data\[2\]_i_2/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[3\]_i_1/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[5\]_i_2/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_number_of_task\[7\]_i_3/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q o_mem_data\[3\]_i_2/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q FSM_onehot_state\[8\]_i_2/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q current_task_addr\[2\]_i_1/I3 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q FSM_onehot_state\[12\]_i_10/I4 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[2\]/Q o_mem_data\[4\]_i_2/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q FSM_onehot_state\[12\]_i_11/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q FSM_onehot_state\[12\]_i_10/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_number_of_task\[3\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_number_of_task\[7\]_i_4/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q o_mem_data\[3\]_i_2/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q FSM_onehot_state\[8\]_i_2/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_task_addr\[15\]_i_9/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_task_addr\[3\]_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q o_mem_data\[4\]_i_2/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_number_of_task\[4\]_i_2/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_number_of_task\[5\]_i_2/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[3\]/Q current_number_of_task\[7\]_i_3/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q FSM_onehot_state\[12\]_i_10/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[4\]_i_1/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[5\]_i_2/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[7\]_i_3/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_task_addr\[0\]_i_6/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q o_mem_data\[6\]_i_6/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q FSM_onehot_state\[1\]_i_5/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q FSM_onehot_state\[8\]_i_1/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_task_addr\[15\]_i_8/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_task_addr\[4\]_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[5\]_i_1/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_task_addr\[15\]_i_9/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q o_mem_data\[5\]_i_2/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q o_mem_data\[7\]_i_4/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[4\]_i_2/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q current_number_of_task\[7\]_i_4/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[4\]/Q o_mem_data\[4\]_i_2/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_number_of_task\[5\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_number_of_task\[7\]_i_3/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_task_addr\[0\]_i_6/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q FSM_onehot_state\[1\]_i_5/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q FSM_onehot_state\[8\]_i_1/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_number_of_task\[5\]_i_1/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q o_mem_data\[5\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q o_mem_data\[6\]_i_6/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_task_addr\[15\]_i_8/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_task_addr\[5\]_i_1/I3 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q o_mem_data\[7\]_i_4/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_number_of_task\[7\]_i_4/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[5\]/Q current_task_addr\[15\]_i_9/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q o_mem_data\[6\]_i_6/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q current_task_addr\[15\]_i_8/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q o_mem_data\[7\]_i_4/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q current_number_of_task\[6\]_i_1/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q current_task_addr\[0\]_i_6/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q o_mem_data\[6\]_i_4/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q o_mem_data\[7\]_i_5/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q FSM_onehot_state\[1\]_i_5/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q FSM_onehot_state\[8\]_i_1/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q current_number_of_task\[7\]_i_2/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q current_task_addr\[6\]_i_1/I3 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[6\]/Q FSM_onehot_state\[12\]_i_7/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q current_task_addr\[15\]_i_8/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q o_mem_data\[7\]_i_4/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q FSM_onehot_state\[12\]_i_7/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q current_number_of_task\[7\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q current_task_addr\[0\]_i_6/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q current_task_addr\[7\]_i_1/I3 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q o_mem_data\[7\]_i_5/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q FSM_onehot_state\[1\]_i_5/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_number_of_task_reg\[7\]/Q FSM_onehot_state\[8\]_i_1/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr\[0\]_i_1/O current_task_addr_reg\[0\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[0\]_i_2/O current_task_addr\[0\]_i_1/I3 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[0\]_i_3/O current_task_addr\[0\]_i_2/I1 (1055.4:1111.0:1111.0) (1055.4:1111.0:1111.0)) + (INTERCONNECT current_task_addr\[0\]_i_4/O current_task_addr\[0\]_i_2/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[0\]_i_5/O current_task_addr\[0\]_i_2/I5 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[0\]_i_6/O current_task_addr\[0\]_i_3/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[10\]_i_1/O current_task_addr_reg\[10\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[10\]_i_2/O current_task_addr\[10\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[11\]_i_1/O current_task_addr_reg\[11\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[11\]_i_10/O current_task_addr_reg\[11\]_i_4/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[11\]_i_11/O current_task_addr_reg\[11\]_i_6/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[11\]_i_12/O current_task_addr_reg\[11\]_i_6/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[11\]_i_13/O current_task_addr_reg\[11\]_i_6/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[11\]_i_14/O current_task_addr_reg\[11\]_i_6/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[11\]_i_2/O current_task_addr\[11\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[11\]_i_7/O current_task_addr_reg\[11\]_i_4/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[11\]_i_8/O current_task_addr_reg\[11\]_i_4/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[11\]_i_9/O current_task_addr_reg\[11\]_i_4/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[12\]_i_1/O current_task_addr_reg\[12\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[12\]_i_2/O current_task_addr\[12\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[12\]_i_5/O current_task_addr_reg\[12\]_i_3/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[12\]_i_6/O current_task_addr_reg\[12\]_i_3/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[12\]_i_7/O current_task_addr_reg\[12\]_i_3/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[12\]_i_8/O current_task_addr_reg\[12\]_i_3/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[13\]_i_1/O current_task_addr_reg\[13\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[13\]_i_2/O current_task_addr\[13\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[1\]_i_1/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[3\]_i_1/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[4\]_i_1/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[6\]_i_1/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[10\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[11\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[12\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[13\]_i_1/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[8\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_3/O current_task_addr\[9\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[13\]_i_5/O current_task_addr_reg\[13\]_i_4/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[13\]_i_6/O current_task_addr_reg\[13\]_i_4/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[13\]_i_7/O current_task_addr_reg\[13\]_i_4/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[13\]_i_8/O current_task_addr_reg\[13\]_i_4/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[14\]_i_1/O current_task_addr_reg\[14\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[10\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[11\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[12\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[13\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[8\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[9\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[14\]_i_2/O current_task_addr\[14\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[14\]_i_3/O current_task_addr\[14\]_i_1/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[14\]_i_4/O current_task_addr\[14\]_i_3/I0 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[14\]_i_5/O current_task_addr\[14\]_i_3/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[0\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[10\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[11\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[12\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[13\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[14\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[15\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[1\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[2\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[3\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[4\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[5\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[6\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[7\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[8\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O current_task_addr_reg\[9\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[0\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[1\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[2\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[3\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[4\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[5\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[6\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_data_reg\[7\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_en_reg/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_mem_we_reg/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[0\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[1\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[2\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[3\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[4\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_1/O o_task_id_reg\[5\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_addr\[15\]_i_10/O current_task_addr\[15\]_i_4/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[7\]_i_3/I1 (1055.4:1111.0:1111.0) (1055.4:1111.0:1111.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[10\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[11\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[12\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[13\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[15\]_i_4/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[1\]_i_3/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[2\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[3\]_i_3/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[4\]_i_8/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[5\]_i_2/I4 (1055.4:1111.0:1111.0) (1055.4:1111.0:1111.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[6\]_i_3/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[8\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_12/O current_task_addr\[9\]_i_2/I4 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_13/O current_task_addr_reg\[15\]_i_5/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[15\]_i_14/O current_task_addr_reg\[15\]_i_5/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[15\]_i_15/O current_task_addr_reg\[15\]_i_5/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[15\]_i_16/O current_task_addr\[15\]_i_6/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_16/O current_task_addr\[0\]_i_5/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_16/O current_task_addr\[7\]_i_5/I3 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_2/O current_task_addr_reg\[15\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[15\]_i_3/O current_task_addr\[15\]_i_2/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_4/O current_task_addr\[15\]_i_2/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_6/O current_task_addr\[15\]_i_3/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_6/O current_task_addr\[14\]_i_2/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[0\]_i_2/I0 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[7\]_i_3/I0 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[14\]_i_2/I1 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[15\]_i_3/I1 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[1\]_i_2/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[3\]_i_2/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[4\]_i_3/I3 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[6\]_i_2/I3 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[2\]_i_2/I5 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[15\]_i_7/O current_task_addr\[5\]_i_2/I5 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[15\]_i_8/O current_task_addr\[15\]_i_4/I0 (1055.4:1111.0:1111.0) (1055.4:1111.0:1111.0)) + (INTERCONNECT current_task_addr\[15\]_i_9/O current_task_addr\[15\]_i_4/I1 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[15\]_i_9/O current_task_addr\[0\]_i_3/I3 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[1\]_i_1/O current_task_addr_reg\[1\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[1\]_i_2/O current_task_addr\[1\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[1\]_i_3/O current_task_addr\[1\]_i_2/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[2\]_i_1/O current_task_addr_reg\[2\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[2\]_i_2/O current_task_addr\[2\]_i_1/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[2\]_i_3/O current_task_addr\[2\]_i_2/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[3\]_i_1/O current_task_addr_reg\[3\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[3\]_i_2/O current_task_addr\[3\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[3\]_i_3/O current_task_addr\[3\]_i_2/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT current_task_addr\[3\]_i_6/O current_task_addr_reg\[3\]_i_4/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[3\]_i_7/O current_task_addr_reg\[3\]_i_5/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[3\]_i_8/O current_task_addr_reg\[3\]_i_5/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[3\]_i_9/O current_task_addr_reg\[3\]_i_5/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[4\]_i_1/O current_task_addr_reg\[4\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[4\]_i_3/O current_task_addr\[4\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[4\]_i_4/O current_task_addr_reg\[4\]_i_2/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[4\]_i_5/O current_task_addr_reg\[4\]_i_2/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[4\]_i_6/O current_task_addr_reg\[4\]_i_2/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[4\]_i_7/O current_task_addr_reg\[4\]_i_2/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[4\]_i_8/O current_task_addr\[4\]_i_3/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[5\]_i_1/O current_task_addr_reg\[5\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[5\]_i_2/O current_task_addr\[5\]_i_1/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[5\]_i_3/O current_task_addr\[5\]_i_2/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[6\]_i_1/O current_task_addr_reg\[6\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[6\]_i_2/O current_task_addr\[6\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[6\]_i_3/O current_task_addr\[6\]_i_2/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_1/O current_task_addr_reg\[7\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[2\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[5\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[7\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[1\]_i_1/I4 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[3\]_i_1/I4 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[4\]_i_1/I4 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[6\]_i_1/I4 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_2/O current_task_addr\[0\]_i_1/I5 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_3/O current_task_addr\[7\]_i_1/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_4/O current_task_addr\[7\]_i_3/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[1\]_i_2/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[2\]_i_2/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[3\]_i_2/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[4\]_i_3/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[5\]_i_2/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[6\]_i_2/I1 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_5/O current_task_addr\[7\]_i_3/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT current_task_addr\[7\]_i_6/O current_task_addr\[0\]_i_5/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[7\]_i_6/O current_task_addr\[7\]_i_5/I2 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT current_task_addr\[8\]_i_1/O current_task_addr_reg\[8\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[8\]_i_2/O current_task_addr\[8\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr\[8\]_i_5/O current_task_addr_reg\[8\]_i_3/S[3] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[8\]_i_6/O current_task_addr_reg\[8\]_i_3/S[2] (18.0:22.0:22.0) (18.0:22.0:22.0)) + (INTERCONNECT current_task_addr\[8\]_i_7/O current_task_addr_reg\[8\]_i_3/S[1] (16.0:20.0:20.0) (16.0:20.0:20.0)) + (INTERCONNECT current_task_addr\[8\]_i_8/O current_task_addr_reg\[8\]_i_3/S[0] (19.0:24.0:24.0) (19.0:24.0:24.0)) + (INTERCONNECT current_task_addr\[9\]_i_1/O current_task_addr_reg\[9\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT current_task_addr\[9\]_i_2/O current_task_addr\[9\]_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr_reg\[2\]_i_4/CYINIT (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr_reg\[4\]_i_2/CYINIT (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q o_mem_addr_OBUF\[0\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[0\]/Q FSM_onehot_state\[21\]_i_4/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr\[0\]_i_3/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr\[0\]_i_1/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr\[0\]_i_5/I2 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr\[0\]_i_2/I4 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr\[0\]_i_4/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q o_mem_data\[1\]_i_2/I4 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q FSM_onehot_state\[12\]_i_9/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr_reg\[3\]_i_4/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[0\]/Q current_task_addr_reg\[3\]_i_5/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr_reg\[12\]_i_3/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr_reg\[11\]_i_4/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q o_mem_addr_OBUF\[10\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr\[11\]_i_8/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr\[12\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q FSM_onehot_state\[12\]_i_6/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr\[10\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q FSM_onehot_state\[21\]_i_3/I3 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr_reg\[12\]_i_4/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[10\]/Q current_task_addr_reg\[11\]_i_3/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr_reg\[12\]_i_3/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr_reg\[11\]_i_4/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q o_mem_addr_OBUF\[11\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr\[11\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr\[12\]_i_6/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr\[11\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q FSM_onehot_state\[12\]_i_6/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q FSM_onehot_state\[21\]_i_3/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr_reg\[12\]_i_4/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[11\]/Q current_task_addr_reg\[11\]_i_3/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_3/CO[3] current_task_addr_reg\[14\]_i_6/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_3/O[3] current_task_addr\[11\]_i_2/I1 (548.0:604.0:604.0) (548.0:604.0:604.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_3/O[2] current_task_addr\[10\]_i_2/I3 (571.4:629.0:629.0) (571.4:629.0:629.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_3/O[1] current_task_addr\[9\]_i_2/I3 (443.4:494.0:494.0) (443.4:494.0:494.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_3/O[0] current_task_addr\[8\]_i_2/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_4/CO[3] current_task_addr_reg\[13\]_i_4/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_4/O[3] current_task_addr\[11\]_i_2/I3 (735.1:801.0:801.0) (735.1:801.0:801.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_4/O[2] current_task_addr\[10\]_i_2/I1 (542.9:599.0:599.0) (542.9:599.0:599.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_4/O[1] current_task_addr\[9\]_i_2/I1 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_4/O[0] current_task_addr\[8\]_i_2/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_5/CO[3] current_task_addr_reg\[11\]_i_3/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_5/O[3] current_task_addr\[7\]_i_4/I5 (735.1:801.0:801.0) (735.1:801.0:801.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_5/O[2] current_task_addr\[6\]_i_3/I3 (571.4:629.0:629.0) (571.4:629.0:629.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_5/O[1] current_task_addr\[5\]_i_3/I1 (716.0:781.0:781.0) (716.0:781.0:781.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_5/O[0] current_task_addr\[4\]_i_8/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_6/CO[3] current_task_addr_reg\[11\]_i_4/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_6/O[3] current_task_addr\[7\]_i_4/I0 (718.0:783.0:783.0) (718.0:783.0:783.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_6/O[2] current_task_addr\[6\]_i_3/I1 (542.9:599.0:599.0) (542.9:599.0:599.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_6/O[1] current_task_addr\[5\]_i_3/I3 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[11\]_i_6/O[0] current_task_addr\[4\]_i_8/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr_reg\[13\]_i_4/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr_reg\[12\]_i_3/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q o_mem_addr_OBUF\[12\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[12\]/Q FSM_onehot_state\[21\]_i_5/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr\[12\]_i_5/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr\[13\]_i_8/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q FSM_onehot_state\[12\]_i_5/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr\[12\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr_reg\[14\]_i_6/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[12\]/Q current_task_addr_reg\[12\]_i_4/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_3/CO[3] current_task_addr_reg\[15\]_i_5/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_3/O[3] current_task_addr\[12\]_i_1/I3 (915.6:991.0:991.0) (915.6:991.0:991.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_3/O[2] current_task_addr\[11\]_i_1/I3 (776.6:845.0:845.0) (776.6:845.0:845.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_3/O[1] current_task_addr\[10\]_i_1/I3 (828.1:899.0:899.0) (828.1:899.0:899.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_3/O[0] current_task_addr\[9\]_i_1/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_4/CO[3] current_task_addr_reg\[15\]_i_11/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_4/O[3] current_task_addr\[12\]_i_2/I5 (718.0:783.0:783.0) (718.0:783.0:783.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_4/O[2] current_task_addr\[11\]_i_2/I5 (1001.8:1082.0:1082.0) (1001.8:1082.0:1082.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_4/O[1] current_task_addr\[10\]_i_2/I5 (716.0:781.0:781.0) (716.0:781.0:781.0)) + (INTERCONNECT current_task_addr_reg\[12\]_i_4/O[0] current_task_addr\[9\]_i_2/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr_reg\[15\]_i_5/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr_reg\[13\]_i_4/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q o_mem_addr_OBUF\[13\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr\[13\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr\[15\]_i_15/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q FSM_onehot_state\[21\]_i_5/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr\[13\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q FSM_onehot_state\[12\]_i_5/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr_reg\[15\]_i_11/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[13\]/Q current_task_addr_reg\[14\]_i_6/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[13\]_i_4/O[3] current_task_addr\[15\]_i_10/I1 (718.0:783.0:783.0) (718.0:783.0:783.0)) + (INTERCONNECT current_task_addr_reg\[13\]_i_4/O[2] current_task_addr\[14\]_i_5/I2 (571.4:629.0:629.0) (571.4:629.0:629.0)) + (INTERCONNECT current_task_addr_reg\[13\]_i_4/O[1] current_task_addr\[13\]_i_2/I3 (443.4:494.0:494.0) (443.4:494.0:494.0)) + (INTERCONNECT current_task_addr_reg\[13\]_i_4/O[0] current_task_addr\[12\]_i_2/I1 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr_reg\[15\]_i_5/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr_reg\[13\]_i_4/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q o_mem_addr_OBUF\[14\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[14\]/Q FSM_onehot_state\[12\]_i_5/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr\[13\]_i_6/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr\[15\]_i_14/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q FSM_onehot_state\[21\]_i_5/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr\[14\]_i_1/I3 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr_reg\[15\]_i_11/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[14\]/Q current_task_addr_reg\[14\]_i_6/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[14\]_i_6/O[3] current_task_addr\[15\]_i_10/I3 (548.0:604.0:604.0) (548.0:604.0:604.0)) + (INTERCONNECT current_task_addr_reg\[14\]_i_6/O[2] current_task_addr\[14\]_i_3/I4 (542.9:599.0:599.0) (542.9:599.0:599.0)) + (INTERCONNECT current_task_addr_reg\[14\]_i_6/O[1] current_task_addr\[13\]_i_2/I1 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[14\]_i_6/O[0] current_task_addr\[12\]_i_2/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q o_mem_addr_OBUF\[15\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[15\]/Q FSM_onehot_state\[12\]_i_4/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr\[13\]_i_5/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr\[15\]_i_13/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr\[15\]_i_2/I2 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q FSM_onehot_state\[21\]_i_5/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr\[15\]_i_8/I5 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr_reg\[15\]_i_11/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[15\]/Q current_task_addr_reg\[14\]_i_6/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_11/O[2] current_task_addr\[15\]_i_4/I3 (542.9:599.0:599.0) (542.9:599.0:599.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_11/O[1] current_task_addr\[14\]_i_3/I2 (716.0:781.0:781.0) (716.0:781.0:781.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_11/O[0] current_task_addr\[13\]_i_2/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_5/O[2] current_task_addr\[15\]_i_10/I4 (571.4:629.0:629.0) (571.4:629.0:629.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_5/O[2] current_task_addr\[15\]_i_2/I5 (1001.8:1082.0:1082.0) (1001.8:1082.0:1082.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_5/O[1] current_task_addr\[14\]_i_5/I0 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_5/O[1] current_task_addr\[14\]_i_1/I5 (716.0:781.0:781.0) (716.0:781.0:781.0)) + (INTERCONNECT current_task_addr_reg\[15\]_i_5/O[0] current_task_addr\[13\]_i_1/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr_reg\[4\]_i_2/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr_reg\[3\]_i_4/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr_reg\[3\]_i_5/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q o_mem_addr_OBUF\[1\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[1\]/Q FSM_onehot_state\[17\]_i_2/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr\[1\]_i_2/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr\[3\]_i_6/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr\[3\]_i_9/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr\[4\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q FSM_onehot_state\[12\]_i_9/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q FSM_onehot_state\[21\]_i_4/I2 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q o_mem_data\[1\]_i_2/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[1\]/Q current_task_addr_reg\[2\]_i_4/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr_reg\[4\]_i_2/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr_reg\[3\]_i_5/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q o_mem_addr_OBUF\[2\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr\[2\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr\[3\]_i_8/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr\[4\]_i_6/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q FSM_onehot_state\[12\]_i_9/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q FSM_onehot_state\[17\]_i_2/I2 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q o_mem_data\[1\]_i_2/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q FSM_onehot_state\[21\]_i_4/I3 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr_reg\[2\]_i_4/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[2\]/Q current_task_addr_reg\[3\]_i_4/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[2\]_i_4/CO[3] current_task_addr_reg\[8\]_i_4/CI (8.6:9.0:9.0) (8.6:9.0:9.0)) + (INTERCONNECT current_task_addr_reg\[2\]_i_4/O[3] current_task_addr\[4\]_i_8/I5 (718.0:783.0:783.0) (718.0:783.0:783.0)) + (INTERCONNECT current_task_addr_reg\[2\]_i_4/O[2] current_task_addr\[3\]_i_3/I5 (1001.8:1082.0:1082.0) (1001.8:1082.0:1082.0)) + (INTERCONNECT current_task_addr_reg\[2\]_i_4/O[1] current_task_addr\[2\]_i_2/I3 (1094.2:1179.0:1179.0) (1094.2:1179.0:1179.0)) + (INTERCONNECT current_task_addr_reg\[2\]_i_4/O[0] current_task_addr\[1\]_i_3/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr_reg\[4\]_i_2/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr_reg\[3\]_i_5/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q o_mem_addr_OBUF\[3\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr\[3\]_i_2/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr\[3\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr\[4\]_i_5/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q FSM_onehot_state\[17\]_i_2/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q o_mem_data\[1\]_i_2/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q FSM_onehot_state\[12\]_i_8/I4 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q FSM_onehot_state\[21\]_i_4/I4 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr_reg\[2\]_i_4/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[3\]/Q current_task_addr_reg\[3\]_i_4/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_4/CO[3] current_task_addr_reg\[11\]_i_5/CI (8.6:9.0:9.0) (8.6:9.0:9.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_4/O[3] current_task_addr\[3\]_i_3/I1 (548.0:604.0:604.0) (548.0:604.0:604.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_4/O[2] current_task_addr\[2\]_i_3/I5 (571.4:629.0:629.0) (571.4:629.0:629.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_4/O[1] current_task_addr\[1\]_i_3/I1 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_4/O[0] current_task_addr\[0\]_i_4/I2 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_5/CO[3] current_task_addr_reg\[11\]_i_6/CI (8.6:9.0:9.0) (8.6:9.0:9.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_5/O[3] current_task_addr\[3\]_i_3/I3 (735.1:801.0:801.0) (735.1:801.0:801.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_5/O[2] current_task_addr\[2\]_i_3/I0 (1001.8:1082.0:1082.0) (1001.8:1082.0:1082.0)) + (INTERCONNECT current_task_addr_reg\[3\]_i_5/O[1] current_task_addr\[1\]_i_3/I3 (443.4:494.0:494.0) (443.4:494.0:494.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr_reg\[11\]_i_6/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr_reg\[4\]_i_2/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q o_mem_addr_OBUF\[4\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr\[11\]_i_14/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr\[4\]_i_3/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr\[4\]_i_4/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q FSM_onehot_state\[21\]_i_6/I1 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q FSM_onehot_state\[12\]_i_8/I2 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr_reg\[11\]_i_5/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[4\]/Q current_task_addr_reg\[2\]_i_4/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/CO[3] current_task_addr_reg\[8\]_i_3/CI (8.6:9.0:9.0) (8.6:9.0:9.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/O[3] current_task_addr\[4\]_i_1/I1 (915.6:991.0:991.0) (915.6:991.0:991.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/O[2] current_task_addr\[3\]_i_1/I1 (776.6:845.0:845.0) (776.6:845.0:845.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/O[1] current_task_addr\[2\]_i_3/I3 (727.5:793.0:793.0) (727.5:793.0:793.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/O[1] current_task_addr\[2\]_i_1/I5 (1094.2:1179.0:1179.0) (1094.2:1179.0:1179.0)) + (INTERCONNECT current_task_addr_reg\[4\]_i_2/O[0] current_task_addr\[1\]_i_1/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr_reg\[8\]_i_3/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr_reg\[11\]_i_6/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q o_mem_addr_OBUF\[5\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[5\]/Q FSM_onehot_state\[21\]_i_6/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr\[11\]_i_13/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr\[5\]_i_2/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr\[8\]_i_8/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q FSM_onehot_state\[12\]_i_8/I1 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr_reg\[8\]_i_4/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[5\]/Q current_task_addr_reg\[11\]_i_5/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr_reg\[8\]_i_3/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr_reg\[11\]_i_6/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q o_mem_addr_OBUF\[6\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr\[11\]_i_12/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr\[6\]_i_2/I0 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr\[8\]_i_7/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q FSM_onehot_state\[21\]_i_6/I3 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q FSM_onehot_state\[12\]_i_7/I5 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr_reg\[8\]_i_4/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_addr_reg\[6\]/Q current_task_addr_reg\[11\]_i_5/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr_reg\[8\]_i_3/DI[2] (456.2:506.0:506.0) (456.2:506.0:506.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr_reg\[11\]_i_6/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q o_mem_addr_OBUF\[7\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[7\]/Q FSM_onehot_state\[12\]_i_7/I0 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr\[11\]_i_11/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr\[8\]_i_6/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q FSM_onehot_state\[21\]_i_6/I2 (584.5:641.0:641.0) (584.5:641.0:641.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr\[7\]_i_3/I5 (1054.8:1136.0:1136.0) (1054.8:1136.0:1136.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr_reg\[8\]_i_4/S[2] (1181.3:1291.0:1291.0) (1181.3:1291.0:1291.0)) + (INTERCONNECT current_task_addr_reg\[7\]/Q current_task_addr_reg\[11\]_i_5/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr_reg\[11\]_i_4/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr_reg\[8\]_i_3/DI[3] (751.7:817.0:817.0) (751.7:817.0:817.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q o_mem_addr_OBUF\[8\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[8\]/Q FSM_onehot_state\[21\]_i_3/I0 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr\[11\]_i_10/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr\[8\]_i_5/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q FSM_onehot_state\[12\]_i_7/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr\[8\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr_reg\[11\]_i_3/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[8\]/Q current_task_addr_reg\[8\]_i_4/S[3] (1189.8:1300.0:1300.0) (1189.8:1300.0:1300.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/CO[3] current_task_addr_reg\[12\]_i_3/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[3] current_task_addr\[8\]_i_1/I3 (915.6:991.0:991.0) (915.6:991.0:991.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[2] current_task_addr\[7\]_i_4/I3 (542.9:599.0:599.0) (542.9:599.0:599.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[2] current_task_addr\[7\]_i_1/I5 (1001.8:1082.0:1082.0) (1001.8:1082.0:1082.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[1] current_task_addr\[6\]_i_1/I1 (828.1:899.0:899.0) (828.1:899.0:899.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[0] current_task_addr\[5\]_i_3/I4 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_3/O[0] current_task_addr\[5\]_i_1/I5 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_4/CO[3] current_task_addr_reg\[12\]_i_4/CI (0.0:0.0:0.0) (0.0:0.0:0.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_4/O[3] current_task_addr\[8\]_i_2/I5 (718.0:783.0:783.0) (718.0:783.0:783.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_4/O[2] current_task_addr\[7\]_i_3/I2 (776.6:845.0:845.0) (776.6:845.0:845.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_4/O[1] current_task_addr\[6\]_i_3/I5 (716.0:781.0:781.0) (716.0:781.0:781.0)) + (INTERCONNECT current_task_addr_reg\[8\]_i_4/O[0] current_task_addr\[5\]_i_2/I3 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr_reg\[12\]_i_3/DI[0] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr_reg\[11\]_i_4/DI[1] (455.3:505.0:505.0) (455.3:505.0:505.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q o_mem_addr_OBUF\[9\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT current_task_addr_reg\[9\]/Q FSM_onehot_state\[12\]_i_6/I0 (842.0:912.0:912.0) (842.0:912.0:912.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr\[11\]_i_9/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr\[12\]_i_8/I0 (433.5:482.0:482.0) (433.5:482.0:482.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q FSM_onehot_state\[21\]_i_3/I1 (770.7:837.0:837.0) (770.7:837.0:837.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr\[9\]_i_1/I1 (903.7:977.0:977.0) (903.7:977.0:977.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr_reg\[12\]_i_4/S[0] (889.7:985.0:985.0) (889.7:985.0:985.0)) + (INTERCONNECT current_task_addr_reg\[9\]/Q current_task_addr_reg\[11\]_i_3/S[1] (884.8:979.0:979.0) (884.8:979.0:979.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[0\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[1\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[2\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[3\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[4\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_1/O current_task_id_reg\[5\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[0\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[1\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[2\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[3\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[4\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id\[5\]_i_2/O current_task_id_reg\[5\]/CE (599.4:659.0:659.0) (599.4:659.0:659.0)) + (INTERCONNECT current_task_id_reg\[0\]/Q o_task_id_reg\[0\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT current_task_id_reg\[1\]/Q o_task_id_reg\[1\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT current_task_id_reg\[2\]/Q o_task_id_reg\[2\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT current_task_id_reg\[3\]/Q o_task_id_reg\[3\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT current_task_id_reg\[4\]/Q o_task_id_reg\[4\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT current_task_id_reg\[5\]/Q o_task_id_reg\[5\]/D (618.3:707.0:707.0) (618.3:707.0:707.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[10\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[11\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[12\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[13\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[14\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[15\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[16\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[17\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[18\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[19\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[20\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[21\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[22\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[23\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[8\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O FSM_onehot_state_reg\[9\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_number_of_task_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[10\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[11\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[12\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[13\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[14\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[15\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[8\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_addr_reg\[9\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O current_task_id_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_done_reg/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[6\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_data_reg\[7\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_en_reg/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_mem_we_reg/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[0\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[1\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[2\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[3\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[4\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_BUFG_inst/O o_task_id_reg\[5\]/C (439.0:584.0:584.0) (439.0:584.0:584.0)) + (INTERCONNECT i_clk_IBUF_inst/O i_clk_IBUF_BUFG_inst/I (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_we_i_2/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[0\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O FSM_onehot_state\[21\]_i_2/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[1\]_i_4/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[5\]_i_3/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[0\]_i_2/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[6\]_i_3/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[6\]_i_7/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[0\]_inst/O o_mem_data\[6\]_i_2/I5 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[1\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O FSM_onehot_state\[21\]_i_2/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_we_i_2/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[6\]_i_3/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[1\]_i_4/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[5\]_i_3/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[1\]_i_3/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[6\]_i_2/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[1\]_inst/O o_mem_data\[6\]_i_7/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[2\]_inst/O current_task_id_reg\[0\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[2\]_inst/O FSM_onehot_state\[1\]_i_7/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[2\]_inst/O o_mem_data\[2\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[2\]_inst/O o_mem_data\[6\]_i_2/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[3\]_inst/O current_task_id_reg\[1\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[3\]_inst/O o_mem_data\[3\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[3\]_inst/O FSM_onehot_state\[1\]_i_7/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[3\]_inst/O o_mem_data\[6\]_i_2/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[4\]_inst/O current_task_id_reg\[2\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[4\]_inst/O o_mem_data\[6\]_i_2/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[4\]_inst/O o_mem_data\[4\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[4\]_inst/O FSM_onehot_state\[1\]_i_7/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[5\]_inst/O current_task_id_reg\[3\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[5\]_inst/O o_mem_data\[6\]_i_2/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[5\]_inst/O FSM_onehot_state\[1\]_i_6/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[5\]_inst/O o_mem_data\[5\]_i_1/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[6\]_inst/O current_task_id_reg\[4\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[6\]_inst/O o_mem_data\[6\]_i_5/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[6\]_inst/O FSM_onehot_state\[1\]_i_6/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[6\]_inst/O o_mem_data\[6\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[6\]_inst/O o_mem_data\[7\]_i_2/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[7\]_inst/O current_task_id_reg\[5\]/D (909.7:985.7:985.7) (909.7:985.7:985.7)) + (INTERCONNECT i_mem_data_IBUF\[7\]_inst/O o_mem_data\[7\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[7\]_inst/O FSM_onehot_state\[1\]_i_6/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_mem_data_IBUF\[7\]_inst/O o_mem_data\[7\]_i_2/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[0\]_inst/O FSM_onehot_state\[14\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[0\]_inst/O FSM_onehot_state\[22\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[0\]_inst/O FSM_onehot_state\[3\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[0\]_inst/O FSM_onehot_state\[7\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[1\]_inst/O FSM_onehot_state\[14\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[1\]_inst/O FSM_onehot_state\[22\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[1\]_inst/O FSM_onehot_state\[3\]_i_1/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_op_IBUF\[1\]_inst/O FSM_onehot_state\[7\]_i_1/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[10\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[11\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[12\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[13\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[14\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[15\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[16\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[17\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[18\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[19\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[1\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[20\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[21\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[22\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[23\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[2\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[3\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[4\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[5\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[6\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[7\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[8\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[9\]/CLR (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O current_number_of_task\[7\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O current_task_addr\[15\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O current_task_id\[5\]_i_2/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O o_task_id\[5\]_i_1/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O current_task_id\[5\]_i_1/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_rst_IBUF_inst/O FSM_onehot_state_reg\[0\]/PRE (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_rst_IBUF_inst/O o_done_reg/PRE (835.7:893.7:893.7) (835.7:893.7:893.7)) + (INTERCONNECT i_start_IBUF_inst/O current_task_id\[5\]_i_1/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_start_IBUF_inst/O o_task_id\[5\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_start_IBUF_inst/O FSM_onehot_state\[23\]_i_2/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_start_IBUF_inst/O FSM_onehot_state\[23\]_i_5/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_start_IBUF_inst/O o_done_i_1/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_start_IBUF_inst/O current_task_id\[5\]_i_2/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[0\]_inst/O FSM_onehot_state\[1\]_i_7/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[0\]_inst/O o_mem_data\[2\]_i_1/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[0\]_inst/O FSM_onehot_state\[1\]_i_3/I5 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[1\]_inst/O FSM_onehot_state\[1\]_i_7/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[1\]_inst/O o_mem_data\[3\]_i_1/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[1\]_inst/O FSM_onehot_state\[1\]_i_3/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[2\]_inst/O FSM_onehot_state\[1\]_i_3/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[2\]_inst/O o_mem_data\[4\]_i_1/I4 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[2\]_inst/O FSM_onehot_state\[1\]_i_7/I5 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[3\]_inst/O o_mem_data\[5\]_i_1/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[3\]_inst/O FSM_onehot_state\[1\]_i_3/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[3\]_inst/O FSM_onehot_state\[1\]_i_6/I5 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[4\]_inst/O FSM_onehot_state\[1\]_i_3/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[4\]_inst/O FSM_onehot_state\[1\]_i_6/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[4\]_inst/O o_mem_data\[6\]_i_5/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[5\]_inst/O o_mem_data\[7\]_i_2/I1 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[5\]_inst/O FSM_onehot_state\[1\]_i_3/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_id_IBUF\[5\]_inst/O FSM_onehot_state\[1\]_i_6/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[0\]_inst/O o_mem_data\[6\]_i_7/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[0\]_inst/O FSM_onehot_state\[21\]_i_2/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[0\]_inst/O o_mem_data\[0\]_i_1/I3 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[1\]_inst/O FSM_onehot_state\[21\]_i_2/I0 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[1\]_inst/O o_mem_data\[1\]_i_1/I2 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT i_task_priority_IBUF\[1\]_inst/O o_mem_data\[6\]_i_7/I5 (759.7:799.7:799.7) (759.7:799.7:799.7)) + (INTERCONNECT o_done_i_1/O o_done_reg/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_done_reg/Q o_done_OBUF_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data\[0\]_i_1/O o_mem_data_reg\[0\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[0\]_i_2/O o_mem_data\[0\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[1\]_i_1/O o_mem_data_reg\[1\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[1\]_i_2/O o_mem_data\[1\]_i_1/I1 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[1\]_i_3/O o_mem_data\[1\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT o_mem_data\[1\]_i_4/O o_mem_data\[1\]_i_1/I5 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[1\]_i_5/O o_mem_data\[1\]_i_4/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[2\]_i_1/O o_mem_data_reg\[2\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[2\]_i_2/O o_mem_data\[2\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[3\]_i_1/O o_mem_data_reg\[3\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[3\]_i_2/O o_mem_data\[3\]_i_1/I2 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[4\]_i_1/O o_mem_data_reg\[4\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[4\]_i_2/O o_mem_data\[4\]_i_1/I3 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[5\]_i_1/O o_mem_data_reg\[5\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[5\]_i_2/O o_mem_data\[5\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[5\]_i_3/O o_mem_data\[2\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[5\]_i_3/O o_mem_data\[3\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[5\]_i_3/O o_mem_data\[4\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[5\]_i_3/O o_mem_data\[5\]_i_1/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[6\]_i_1/O o_mem_data_reg\[6\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[6\]_i_2/O o_mem_data\[6\]_i_1/I2 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT o_mem_data\[6\]_i_2/O o_mem_data\[7\]_i_2/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT o_mem_data\[6\]_i_3/O o_mem_data\[6\]_i_1/I3 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[6\]_i_3/O o_mem_data\[7\]_i_2/I5 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[6\]_i_4/O o_mem_data\[6\]_i_1/I4 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT o_mem_data\[6\]_i_5/O o_mem_data\[6\]_i_1/I5 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[6\]_i_6/O o_mem_data\[6\]_i_5/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT o_mem_data\[6\]_i_7/O o_mem_data\[6\]_i_5/I5 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[7\]_i_1/O o_mem_data_reg\[7\]/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_data\[7\]_i_2/O o_mem_data\[7\]_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_data\[7\]_i_3/O o_mem_data\[0\]_i_1/I0 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_data\[7\]_i_3/O o_mem_data\[7\]_i_1/I2 (856.9:902.0:902.0) (856.9:902.0:902.0)) + (INTERCONNECT o_mem_data\[7\]_i_4/O o_mem_data\[7\]_i_1/I4 (1055.4:1111.0:1111.0) (1055.4:1111.0:1111.0)) + (INTERCONNECT o_mem_data\[7\]_i_5/O o_mem_data\[7\]_i_1/I5 (631.8:665.0:665.0) (631.8:665.0:665.0)) + (INTERCONNECT o_mem_data_reg\[0\]/Q o_mem_data_OBUF\[0\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[1\]/Q o_mem_data_OBUF\[1\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[2\]/Q o_mem_data_OBUF\[2\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[3\]/Q o_mem_data_OBUF\[3\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[4\]/Q o_mem_data_OBUF\[4\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[5\]/Q o_mem_data_OBUF\[5\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[6\]/Q o_mem_data_OBUF\[6\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_data_reg\[7\]/Q o_mem_data_OBUF\[7\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_en_i_1/O o_mem_en_reg/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_en_i_2/O o_mem_en_i_1/I2 (398.0:419.0:419.0) (398.0:419.0:419.0)) + (INTERCONNECT o_mem_en_i_3/O o_mem_en_i_1/I3 (915.8:964.0:964.0) (915.8:964.0:964.0)) + (INTERCONNECT o_mem_en_reg/Q o_mem_en_OBUF_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_mem_we_i_1/O o_mem_we_reg/D (88.0:109.0:109.0) (88.0:109.0:109.0)) + (INTERCONNECT o_mem_we_i_2/O o_mem_we_i_1/I0 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_we_i_2/O o_mem_en_i_1/I4 (426.5:449.0:449.0) (426.5:449.0:449.0)) + (INTERCONNECT o_mem_we_reg/Q o_mem_we_OBUF_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[0\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[1\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[2\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[3\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[4\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id\[5\]_i_1/O o_task_id_reg\[5\]/R (816.2:874.0:874.0) (816.2:874.0:874.0)) + (INTERCONNECT o_task_id_reg\[0\]/Q o_task_id_OBUF\[0\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id_reg\[1\]/Q o_task_id_OBUF\[1\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id_reg\[2\]/Q o_task_id_OBUF\[2\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id_reg\[3\]/Q o_task_id_OBUF\[3\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id_reg\[4\]/Q o_task_id_OBUF\[4\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) + (INTERCONNECT o_task_id_reg\[5\]/Q o_task_id_OBUF\[5\]_inst/I (901.7:975.7:975.7) (901.7:975.7:975.7)) +) diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v new file mode 100644 index 0000000..c7774bb --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v @@ -0,0 +1,2905 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Thu Jun 11 14:50:59 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or +// synthesized. Please ensure that this netlist is used with the corresponding SDF file. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps +`define XIL_TIMING + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[1]_i_6_n_0 ; + wire \FSM_onehot_state[1]_i_7_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[23]_i_7_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire [7:0]current_number_of_task; + wire \current_number_of_task[0]_i_1_n_0 ; + wire \current_number_of_task[1]_i_1_n_0 ; + wire \current_number_of_task[2]_i_1_n_0 ; + wire \current_number_of_task[3]_i_1_n_0 ; + wire \current_number_of_task[4]_i_1_n_0 ; + wire \current_number_of_task[4]_i_2_n_0 ; + wire \current_number_of_task[5]_i_1_n_0 ; + wire \current_number_of_task[5]_i_2_n_0 ; + wire \current_number_of_task[6]_i_1_n_0 ; + wire \current_number_of_task[7]_i_1_n_0 ; + wire \current_number_of_task[7]_i_2_n_0 ; + wire \current_number_of_task[7]_i_3_n_0 ; + wire \current_number_of_task[7]_i_4_n_0 ; + wire \current_task_addr[0]_i_1_n_0 ; + wire \current_task_addr[0]_i_2_n_0 ; + wire \current_task_addr[0]_i_3_n_0 ; + wire \current_task_addr[0]_i_4_n_0 ; + wire \current_task_addr[0]_i_5_n_0 ; + wire \current_task_addr[0]_i_6_n_0 ; + wire \current_task_addr[10]_i_1_n_0 ; + wire \current_task_addr[10]_i_2_n_0 ; + wire \current_task_addr[11]_i_10_n_0 ; + wire \current_task_addr[11]_i_11_n_0 ; + wire \current_task_addr[11]_i_12_n_0 ; + wire \current_task_addr[11]_i_13_n_0 ; + wire \current_task_addr[11]_i_14_n_0 ; + wire \current_task_addr[11]_i_1_n_0 ; + wire \current_task_addr[11]_i_2_n_0 ; + wire \current_task_addr[11]_i_7_n_0 ; + wire \current_task_addr[11]_i_8_n_0 ; + wire \current_task_addr[11]_i_9_n_0 ; + wire \current_task_addr[12]_i_1_n_0 ; + wire \current_task_addr[12]_i_2_n_0 ; + wire \current_task_addr[12]_i_5_n_0 ; + wire \current_task_addr[12]_i_6_n_0 ; + wire \current_task_addr[12]_i_7_n_0 ; + wire \current_task_addr[12]_i_8_n_0 ; + wire \current_task_addr[13]_i_1_n_0 ; + wire \current_task_addr[13]_i_2_n_0 ; + wire \current_task_addr[13]_i_3_n_0 ; + wire \current_task_addr[13]_i_5_n_0 ; + wire \current_task_addr[13]_i_6_n_0 ; + wire \current_task_addr[13]_i_7_n_0 ; + wire \current_task_addr[13]_i_8_n_0 ; + wire \current_task_addr[14]_i_1_n_0 ; + wire \current_task_addr[14]_i_2_n_0 ; + wire \current_task_addr[14]_i_3_n_0 ; + wire \current_task_addr[14]_i_4_n_0 ; + wire \current_task_addr[14]_i_5_n_0 ; + wire \current_task_addr[15]_i_10_n_0 ; + wire \current_task_addr[15]_i_12_n_0 ; + wire \current_task_addr[15]_i_13_n_0 ; + wire \current_task_addr[15]_i_14_n_0 ; + wire \current_task_addr[15]_i_15_n_0 ; + wire \current_task_addr[15]_i_16_n_0 ; + wire \current_task_addr[15]_i_1_n_0 ; + wire \current_task_addr[15]_i_2_n_0 ; + wire \current_task_addr[15]_i_3_n_0 ; + wire \current_task_addr[15]_i_4_n_0 ; + wire \current_task_addr[15]_i_6_n_0 ; + wire \current_task_addr[15]_i_7_n_0 ; + wire \current_task_addr[15]_i_8_n_0 ; + wire \current_task_addr[15]_i_9_n_0 ; + wire \current_task_addr[1]_i_1_n_0 ; + wire \current_task_addr[1]_i_2_n_0 ; + wire \current_task_addr[1]_i_3_n_0 ; + wire \current_task_addr[2]_i_1_n_0 ; + wire \current_task_addr[2]_i_2_n_0 ; + wire \current_task_addr[2]_i_3_n_0 ; + wire \current_task_addr[3]_i_1_n_0 ; + wire \current_task_addr[3]_i_2_n_0 ; + wire \current_task_addr[3]_i_3_n_0 ; + wire \current_task_addr[3]_i_6_n_0 ; + wire \current_task_addr[3]_i_7_n_0 ; + wire \current_task_addr[3]_i_8_n_0 ; + wire \current_task_addr[3]_i_9_n_0 ; + wire \current_task_addr[4]_i_1_n_0 ; + wire \current_task_addr[4]_i_3_n_0 ; + wire \current_task_addr[4]_i_4_n_0 ; + wire \current_task_addr[4]_i_5_n_0 ; + wire \current_task_addr[4]_i_6_n_0 ; + wire \current_task_addr[4]_i_7_n_0 ; + wire \current_task_addr[4]_i_8_n_0 ; + wire \current_task_addr[5]_i_1_n_0 ; + wire \current_task_addr[5]_i_2_n_0 ; + wire \current_task_addr[5]_i_3_n_0 ; + wire \current_task_addr[6]_i_1_n_0 ; + wire \current_task_addr[6]_i_2_n_0 ; + wire \current_task_addr[6]_i_3_n_0 ; + wire \current_task_addr[7]_i_1_n_0 ; + wire \current_task_addr[7]_i_2_n_0 ; + wire \current_task_addr[7]_i_3_n_0 ; + wire \current_task_addr[7]_i_4_n_0 ; + wire \current_task_addr[7]_i_5_n_0 ; + wire \current_task_addr[7]_i_6_n_0 ; + wire \current_task_addr[8]_i_1_n_0 ; + wire \current_task_addr[8]_i_2_n_0 ; + wire \current_task_addr[8]_i_5_n_0 ; + wire \current_task_addr[8]_i_6_n_0 ; + wire \current_task_addr[8]_i_7_n_0 ; + wire \current_task_addr[8]_i_8_n_0 ; + wire \current_task_addr[9]_i_1_n_0 ; + wire \current_task_addr[9]_i_2_n_0 ; + wire \current_task_addr_reg[11]_i_3_n_0 ; + wire \current_task_addr_reg[11]_i_3_n_1 ; + wire \current_task_addr_reg[11]_i_3_n_2 ; + wire \current_task_addr_reg[11]_i_3_n_3 ; + wire \current_task_addr_reg[11]_i_4_n_0 ; + wire \current_task_addr_reg[11]_i_4_n_1 ; + wire \current_task_addr_reg[11]_i_4_n_2 ; + wire \current_task_addr_reg[11]_i_4_n_3 ; + wire \current_task_addr_reg[11]_i_5_n_0 ; + wire \current_task_addr_reg[11]_i_5_n_1 ; + wire \current_task_addr_reg[11]_i_5_n_2 ; + wire \current_task_addr_reg[11]_i_5_n_3 ; + wire \current_task_addr_reg[11]_i_6_n_0 ; + wire \current_task_addr_reg[11]_i_6_n_1 ; + wire \current_task_addr_reg[11]_i_6_n_2 ; + wire \current_task_addr_reg[11]_i_6_n_3 ; + wire \current_task_addr_reg[12]_i_3_n_0 ; + wire \current_task_addr_reg[12]_i_3_n_1 ; + wire \current_task_addr_reg[12]_i_3_n_2 ; + wire \current_task_addr_reg[12]_i_3_n_3 ; + wire \current_task_addr_reg[12]_i_4_n_0 ; + wire \current_task_addr_reg[12]_i_4_n_1 ; + wire \current_task_addr_reg[12]_i_4_n_2 ; + wire \current_task_addr_reg[12]_i_4_n_3 ; + wire \current_task_addr_reg[13]_i_4_n_1 ; + wire \current_task_addr_reg[13]_i_4_n_2 ; + wire \current_task_addr_reg[13]_i_4_n_3 ; + wire \current_task_addr_reg[14]_i_6_n_1 ; + wire \current_task_addr_reg[14]_i_6_n_2 ; + wire \current_task_addr_reg[14]_i_6_n_3 ; + wire \current_task_addr_reg[15]_i_11_n_2 ; + wire \current_task_addr_reg[15]_i_11_n_3 ; + wire \current_task_addr_reg[15]_i_5_n_2 ; + wire \current_task_addr_reg[15]_i_5_n_3 ; + wire \current_task_addr_reg[2]_i_4_n_0 ; + wire \current_task_addr_reg[2]_i_4_n_1 ; + wire \current_task_addr_reg[2]_i_4_n_2 ; + wire \current_task_addr_reg[2]_i_4_n_3 ; + wire \current_task_addr_reg[3]_i_4_n_0 ; + wire \current_task_addr_reg[3]_i_4_n_1 ; + wire \current_task_addr_reg[3]_i_4_n_2 ; + wire \current_task_addr_reg[3]_i_4_n_3 ; + wire \current_task_addr_reg[3]_i_5_n_0 ; + wire \current_task_addr_reg[3]_i_5_n_1 ; + wire \current_task_addr_reg[3]_i_5_n_2 ; + wire \current_task_addr_reg[3]_i_5_n_3 ; + wire \current_task_addr_reg[4]_i_2_n_0 ; + wire \current_task_addr_reg[4]_i_2_n_1 ; + wire \current_task_addr_reg[4]_i_2_n_2 ; + wire \current_task_addr_reg[4]_i_2_n_3 ; + wire \current_task_addr_reg[8]_i_3_n_0 ; + wire \current_task_addr_reg[8]_i_3_n_1 ; + wire \current_task_addr_reg[8]_i_3_n_2 ; + wire \current_task_addr_reg[8]_i_3_n_3 ; + wire \current_task_addr_reg[8]_i_4_n_0 ; + wire \current_task_addr_reg[8]_i_4_n_1 ; + wire \current_task_addr_reg[8]_i_4_n_2 ; + wire \current_task_addr_reg[8]_i_4_n_3 ; + wire [5:0]current_task_id; + wire \current_task_id[5]_i_1_n_0 ; + wire \current_task_id[5]_i_2_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in24; + wire [15:1]in27; + wire [15:1]in28; + wire [15:0]in32; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[1]_i_5_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[6]_i_6_n_0 ; + wire \o_mem_data[6]_i_7_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_task_addr_reg[13]_i_4_CO_UNCONNECTED ; + wire [3:3]\NLW_current_task_addr_reg[14]_i_6_CO_UNCONNECTED ; + wire [3:2]\NLW_current_task_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:3]\NLW_current_task_addr_reg[15]_i_11_O_UNCONNECTED ; + wire [3:2]\NLW_current_task_addr_reg[15]_i_5_CO_UNCONNECTED ; + wire [3:3]\NLW_current_task_addr_reg[15]_i_5_O_UNCONNECTED ; + wire [0:0]\NLW_current_task_addr_reg[3]_i_5_O_UNCONNECTED ; + +initial begin + $sdf_annotate("project_tb_edge_time_synth.sdf",,,,"tool_control"); +end + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_number_of_task[4]), + .I1(current_number_of_task[3]), + .I2(current_number_of_task[1]), + .I3(current_number_of_task[0]), + .I4(current_number_of_task[2]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_number_of_task[3]), + .I1(current_number_of_task[2]), + .I2(current_number_of_task[0]), + .I3(current_number_of_task[1]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[14]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[13]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h0021210042000021)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_number_of_task[7]), + .I3(\current_number_of_task[7]_i_3_n_0 ), + .I4(current_number_of_task[6]), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\current_number_of_task[5]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(o_mem_addr_OBUF[4]), + .I3(\FSM_onehot_state[12]_i_10_n_0 ), + .I4(o_mem_addr_OBUF[3]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_number_of_task[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_number_of_task[1]), + .I4(current_number_of_task[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'hF4)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFEFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(\FSM_onehot_state[21]_i_3_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'h51FF)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state[21]_i_3_n_0 ), + .I2(\FSM_onehot_state[21]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFF8F88FFFFFFFF)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state[1]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[14] ), + .I4(\FSM_onehot_state[1]_i_4_n_0 ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state[1]_i_6_n_0 ), + .I1(\FSM_onehot_state[1]_i_7_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[1]_i_3 + (.I0(i_task_id_IBUF[4]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[5]), + .I3(i_task_id_IBUF[3]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[0] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[5] ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFDFFFFFFFF)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state[8]_i_2_n_0 ), + .I1(current_number_of_task[5]), + .I2(current_number_of_task[4]), + .I3(current_number_of_task[6]), + .I4(current_number_of_task[7]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[1]_i_6 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[1]_i_6_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[1]_i_7 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[1]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'h5100)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state[21]_i_3_n_0 ), + .I2(\FSM_onehot_state[21]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT4 #( + .INIT(16'hBB2B)) + \FSM_onehot_state[21]_i_2 + (.I0(i_task_priority_IBUF[1]), + .I1(i_mem_data_IBUF[1]), + .I2(i_mem_data_IBUF[0]), + .I3(i_task_priority_IBUF[0]), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT5 #( + .INIT(32'h00000001)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[8]), + .I1(o_mem_addr_OBUF[9]), + .I2(o_mem_addr_OBUF[11]), + .I3(o_mem_addr_OBUF[10]), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(\FSM_onehot_state[21]_i_6_n_0 ), + .I1(o_mem_addr_OBUF[0]), + .I2(o_mem_addr_OBUF[1]), + .I3(o_mem_addr_OBUF[2]), + .I4(o_mem_addr_OBUF[3]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[14]), + .I3(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state[23]_i_4_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT3 #( + .INIT(8'hEA)) + \FSM_onehot_state[23]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[17] ), + .I1(\FSM_onehot_state_reg_n_0_[4] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state[23]_i_5_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state[23]_i_6_n_0 ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state_reg_n_0_[16] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state[23]_i_7_n_0 ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[14] ), + .I2(\FSM_onehot_state_reg_n_0_[20] ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .O(\FSM_onehot_state[23]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFD00000000)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state[8]_i_2_n_0 ), + .I1(current_number_of_task[5]), + .I2(current_number_of_task[4]), + .I3(current_number_of_task[6]), + .I4(current_number_of_task[7]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[8]_i_2 + (.I0(current_number_of_task[1]), + .I1(current_number_of_task[0]), + .I2(current_number_of_task[3]), + .I3(current_number_of_task[2]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT3 #( + .INIT(8'h54)) + \current_number_of_task[0]_i_1 + (.I0(current_number_of_task[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_number_of_task[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_number_of_task[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[0]), + .I2(current_number_of_task[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_number_of_task[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[2]), + .I2(current_number_of_task[1]), + .I3(current_number_of_task[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_number_of_task[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[3]), + .I2(current_number_of_task[2]), + .I3(current_number_of_task[0]), + .I4(current_number_of_task[1]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hBEAA)) + \current_number_of_task[4]_i_1 + (.I0(\current_number_of_task[4]_i_2_n_0 ), + .I1(current_number_of_task[4]), + .I2(\FSM_onehot_state[8]_i_2_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_number_of_task[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[2]), + .I2(current_number_of_task[0]), + .I3(current_number_of_task[1]), + .I4(current_number_of_task[3]), + .I5(current_number_of_task[4]), + .O(\current_number_of_task[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF4F44FF444444444)) + \current_number_of_task[5]_i_1 + (.I0(\current_number_of_task[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_number_of_task[5]), + .I3(\FSM_onehot_state[8]_i_2_n_0 ), + .I4(current_number_of_task[4]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_number_of_task[5]_i_2 + (.I0(current_number_of_task[5]), + .I1(current_number_of_task[4]), + .I2(current_number_of_task[2]), + .I3(current_number_of_task[0]), + .I4(current_number_of_task[1]), + .I5(current_number_of_task[3]), + .O(\current_number_of_task[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h4FF84848)) + \current_number_of_task[6]_i_1 + (.I0(\current_number_of_task[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_number_of_task[6]), + .I3(\current_number_of_task[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_number_of_task[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[0] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[22] ), + .O(\current_number_of_task[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF8CFF8F048C048C0)) + \current_number_of_task[7]_i_2 + (.I0(\current_number_of_task[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_number_of_task[7]), + .I3(current_number_of_task[6]), + .I4(\current_number_of_task[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_number_of_task[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8000000000000000)) + \current_number_of_task[7]_i_3 + (.I0(current_number_of_task[5]), + .I1(current_number_of_task[4]), + .I2(current_number_of_task[2]), + .I3(current_number_of_task[0]), + .I4(current_number_of_task[1]), + .I5(current_number_of_task[3]), + .O(\current_number_of_task[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_number_of_task[7]_i_4 + (.I0(current_number_of_task[2]), + .I1(current_number_of_task[3]), + .I2(current_number_of_task[0]), + .I3(current_number_of_task[1]), + .I4(current_number_of_task[5]), + .I5(current_number_of_task[4]), + .O(\current_number_of_task[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[0]_i_1_n_0 ), + .Q(current_number_of_task[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[1]_i_1_n_0 ), + .Q(current_number_of_task[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[2]_i_1_n_0 ), + .Q(current_number_of_task[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[3]_i_1_n_0 ), + .Q(current_number_of_task[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[4]_i_1_n_0 ), + .Q(current_number_of_task[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[5]_i_1_n_0 ), + .Q(current_number_of_task[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[6]_i_1_n_0 ), + .Q(current_number_of_task[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_number_of_task_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_number_of_task[7]_i_1_n_0 ), + .D(\current_number_of_task[7]_i_2_n_0 ), + .Q(current_number_of_task[7]), + .R(1'b0)); + LUT6 #( + .INIT(64'hFF0EFF0EFFFFFF0E)) + \current_task_addr[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[0]), + .I3(\current_task_addr[0]_i_2_n_0 ), + .I4(current_number_of_task[0]), + .I5(\current_task_addr[7]_i_2_n_0 ), + .O(\current_task_addr[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFDFCFC)) + \current_task_addr[0]_i_2 + (.I0(\current_task_addr[15]_i_7_n_0 ), + .I1(\current_task_addr[0]_i_3_n_0 ), + .I2(\current_task_addr[0]_i_4_n_0 ), + .I3(\FSM_onehot_state[12]_i_1_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\current_task_addr[0]_i_5_n_0 ), + .O(\current_task_addr[0]_i_2_n_0 )); + LUT4 #( + .INIT(16'hA8AA)) + \current_task_addr[0]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(o_mem_addr_OBUF[0]), + .I2(\current_task_addr[0]_i_6_n_0 ), + .I3(\current_task_addr[15]_i_9_n_0 ), + .O(\current_task_addr[0]_i_3_n_0 )); + LUT5 #( + .INIT(32'hEAEAFFC0)) + \current_task_addr[0]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in32[0]), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(o_mem_addr_OBUF[0]), + .O(\current_task_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFEFFFEFFFEFFFE0)) + \current_task_addr[0]_i_5 + (.I0(\current_task_addr[7]_i_6_n_0 ), + .I1(\current_task_addr[15]_i_16_n_0 ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[3] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_task_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'hFFFE)) + \current_task_addr[0]_i_6 + (.I0(current_number_of_task[5]), + .I1(current_number_of_task[4]), + .I2(current_number_of_task[6]), + .I3(current_number_of_task[7]), + .O(\current_task_addr[0]_i_6_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[10]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\current_task_addr[10]_i_2_n_0 ), + .I3(in27[10]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[10]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[10]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[10]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[10]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[10]), + .O(\current_task_addr[10]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[11]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\current_task_addr[11]_i_2_n_0 ), + .I3(in27[11]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_task_addr[11]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_11 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_task_addr[11]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_12 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_task_addr[11]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_13 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_task_addr[11]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_14 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_task_addr[11]_i_14_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[11]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[11]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[11]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[11]), + .O(\current_task_addr[11]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_task_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_task_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_task_addr[11]_i_9_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[12]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\current_task_addr[12]_i_2_n_0 ), + .I3(in27[12]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[12]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[12]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[12]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[12]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[12]), + .O(\current_task_addr[12]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[12]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_task_addr[12]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[12]_i_6 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_task_addr[12]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[12]_i_7 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_task_addr[12]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[12]_i_8 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_task_addr[12]_i_8_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[13]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\current_task_addr[13]_i_2_n_0 ), + .I3(in27[13]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[13]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[13]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[13]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[13]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[13]), + .O(\current_task_addr[13]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT3 #( + .INIT(8'h15)) + \current_task_addr[13]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_task_addr[13]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[13]_i_5 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_task_addr[13]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[13]_i_6 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_task_addr[13]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[13]_i_7 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_task_addr[13]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[13]_i_8 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_task_addr[13]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFF8F88FFFF0F00)) + \current_task_addr[14]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\current_task_addr[14]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[14]), + .I4(\current_task_addr[14]_i_3_n_0 ), + .I5(in27[14]), + .O(\current_task_addr[14]_i_1_n_0 )); + LUT3 #( + .INIT(8'h08)) + \current_task_addr[14]_i_2 + (.I0(\FSM_onehot_state[1]_i_5_n_0 ), + .I1(\current_task_addr[15]_i_7_n_0 ), + .I2(\current_task_addr[15]_i_6_n_0 ), + .O(\current_task_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFCDCFCDCFCDC)) + \current_task_addr[14]_i_3 + (.I0(\current_task_addr[14]_i_4_n_0 ), + .I1(\current_task_addr[14]_i_5_n_0 ), + .I2(in24[14]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(in28[14]), + .I5(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_task_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT2 #( + .INIT(4'h1)) + \current_task_addr[14]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_task_addr[14]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hF888)) + \current_task_addr[14]_i_5 + (.I0(in27[14]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(in32[14]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_task_addr[14]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_task_addr[15]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_task_addr[15]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[15]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[15]), + .I4(in27[15]), + .I5(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_task_addr[15]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT3 #( + .INIT(8'h01)) + \current_task_addr[15]_i_12 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_task_addr[15]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_task_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_task_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_task_addr[15]_i_15_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \current_task_addr[15]_i_16 + (.I0(\FSM_onehot_state[23]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[20] ), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\current_task_addr[15]_i_16_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888FFFFF000)) + \current_task_addr[15]_i_2 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[15]), + .I3(\current_task_addr[15]_i_3_n_0 ), + .I4(\current_task_addr[15]_i_4_n_0 ), + .I5(in27[15]), + .O(\current_task_addr[15]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT2 #( + .INIT(4'hB)) + \current_task_addr[15]_i_3 + (.I0(\current_task_addr[15]_i_6_n_0 ), + .I1(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[15]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[15]_i_4 + (.I0(\current_task_addr[15]_i_8_n_0 ), + .I1(\current_task_addr[15]_i_9_n_0 ), + .I2(\current_task_addr[15]_i_10_n_0 ), + .I3(in24[15]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .O(\current_task_addr[15]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFEFFFFFFFE)) + \current_task_addr[15]_i_6 + (.I0(\current_task_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_task_addr[15]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h7077)) + \current_task_addr[15]_i_7 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[16] ), + .I2(\FSM_onehot_state[1]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[14] ), + .O(\current_task_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFEFFFFFFFFFFFF)) + \current_task_addr[15]_i_8 + (.I0(current_number_of_task[7]), + .I1(current_number_of_task[6]), + .I2(current_number_of_task[4]), + .I3(current_number_of_task[5]), + .I4(\FSM_onehot_state_reg_n_0_[7] ), + .I5(o_mem_addr_OBUF[15]), + .O(\current_task_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000000001010001)) + \current_task_addr[15]_i_9 + (.I0(current_number_of_task[2]), + .I1(current_number_of_task[0]), + .I2(current_number_of_task[1]), + .I3(current_number_of_task[3]), + .I4(current_number_of_task[4]), + .I5(current_number_of_task[5]), + .O(\current_task_addr[15]_i_9_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[1]_i_1 + (.I0(\current_task_addr[13]_i_3_n_0 ), + .I1(in27[1]), + .I2(\current_task_addr[1]_i_2_n_0 ), + .I3(current_number_of_task[1]), + .I4(\current_task_addr[7]_i_2_n_0 ), + .O(\current_task_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT4 #( + .INIT(16'hF8FA)) + \current_task_addr[1]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[1]_i_3_n_0 ), + .I3(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[1]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[1]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[1]), + .O(\current_task_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFF8F88FFFF0F00)) + \current_task_addr[2]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\current_task_addr[7]_i_2_n_0 ), + .I3(current_number_of_task[2]), + .I4(\current_task_addr[2]_i_2_n_0 ), + .I5(in27[2]), + .O(\current_task_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF8F8FFF8FAFAFFFA)) + \current_task_addr[2]_i_2 + (.I0(o_mem_addr_OBUF[2]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[2]_i_3_n_0 ), + .I3(in24[2]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_task_addr[2]_i_3 + (.I0(in32[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in27[2]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in28[2]), + .O(\current_task_addr[2]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[3]_i_1 + (.I0(\current_task_addr[13]_i_3_n_0 ), + .I1(in27[3]), + .I2(\current_task_addr[3]_i_2_n_0 ), + .I3(current_number_of_task[3]), + .I4(\current_task_addr[7]_i_2_n_0 ), + .O(\current_task_addr[3]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF8FA)) + \current_task_addr[3]_i_2 + (.I0(o_mem_addr_OBUF[3]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[3]_i_3_n_0 ), + .I3(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[3]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[3]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[3]), + .O(\current_task_addr[3]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[3]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_task_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[3]_i_7 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_task_addr[3]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[3]_i_8 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_task_addr[3]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_task_addr[3]_i_9_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[4]_i_1 + (.I0(\current_task_addr[13]_i_3_n_0 ), + .I1(in27[4]), + .I2(\current_task_addr[4]_i_3_n_0 ), + .I3(current_number_of_task[4]), + .I4(\current_task_addr[7]_i_2_n_0 ), + .O(\current_task_addr[4]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF8FA)) + \current_task_addr[4]_i_3 + (.I0(o_mem_addr_OBUF[4]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[4]_i_8_n_0 ), + .I3(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[4]_i_3_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[4]_i_4 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_task_addr[4]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[4]_i_5 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_task_addr[4]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_task_addr[4]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_task_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[4]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[4]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[4]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[4]), + .O(\current_task_addr[4]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFF8F88FFFF0F00)) + \current_task_addr[5]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\current_task_addr[7]_i_2_n_0 ), + .I3(current_number_of_task[5]), + .I4(\current_task_addr[5]_i_2_n_0 ), + .I5(in27[5]), + .O(\current_task_addr[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF8F8FFF8FAFAFFFA)) + \current_task_addr[5]_i_2 + (.I0(o_mem_addr_OBUF[5]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[5]_i_3_n_0 ), + .I3(in24[5]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_task_addr[5]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(in28[5]), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in32[5]), + .I4(in27[5]), + .I5(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_task_addr[5]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[6]_i_1 + (.I0(\current_task_addr[13]_i_3_n_0 ), + .I1(in27[6]), + .I2(\current_task_addr[6]_i_2_n_0 ), + .I3(current_number_of_task[6]), + .I4(\current_task_addr[7]_i_2_n_0 ), + .O(\current_task_addr[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'hF8FA)) + \current_task_addr[6]_i_2 + (.I0(o_mem_addr_OBUF[6]), + .I1(\current_task_addr[7]_i_5_n_0 ), + .I2(\current_task_addr[6]_i_3_n_0 ), + .I3(\current_task_addr[15]_i_7_n_0 ), + .O(\current_task_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[6]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[6]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[6]), + .O(\current_task_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFF8F88FFFF0F00)) + \current_task_addr[7]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\current_task_addr[7]_i_2_n_0 ), + .I3(current_number_of_task[7]), + .I4(\current_task_addr[7]_i_3_n_0 ), + .I5(in27[7]), + .O(\current_task_addr[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT3 #( + .INIT(8'h0D)) + \current_task_addr[7]_i_2 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\current_task_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFF75FF30FF30)) + \current_task_addr[7]_i_3 + (.I0(\current_task_addr[15]_i_7_n_0 ), + .I1(\current_task_addr[15]_i_12_n_0 ), + .I2(in24[7]), + .I3(\current_task_addr[7]_i_4_n_0 ), + .I4(\current_task_addr[7]_i_5_n_0 ), + .I5(o_mem_addr_OBUF[7]), + .O(\current_task_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_task_addr[7]_i_4 + (.I0(in32[7]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in28[7]), + .O(\current_task_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'hFFF4FFFF)) + \current_task_addr[7]_i_5 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\current_task_addr[7]_i_6_n_0 ), + .I3(\current_task_addr[15]_i_16_n_0 ), + .I4(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\current_task_addr[7]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'hFE)) + \current_task_addr[7]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(\FSM_onehot_state_reg_n_0_[5] ), + .O(\current_task_addr[7]_i_6_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[8]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\current_task_addr[8]_i_2_n_0 ), + .I3(in27[8]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[8]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[8]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[8]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[8]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[8]), + .O(\current_task_addr[8]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[8]_i_5 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_task_addr[8]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[8]_i_6 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_task_addr[8]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_task_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_task_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_task_addr[8]_i_8_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \current_task_addr[9]_i_1 + (.I0(\current_task_addr[14]_i_2_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\current_task_addr[9]_i_2_n_0 ), + .I3(in27[9]), + .I4(\current_task_addr[13]_i_3_n_0 ), + .O(\current_task_addr[9]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF888FFFFF888F888)) + \current_task_addr[9]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[21] ), + .I1(in32[9]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in28[9]), + .I4(\current_task_addr[15]_i_12_n_0 ), + .I5(in24[9]), + .O(\current_task_addr[9]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[11]_i_3 + (.CI(\current_task_addr_reg[11]_i_5_n_0 ), + .CO({\current_task_addr_reg[11]_i_3_n_0 ,\current_task_addr_reg[11]_i_3_n_1 ,\current_task_addr_reg[11]_i_3_n_2 ,\current_task_addr_reg[11]_i_3_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in28[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[11]_i_4 + (.CI(\current_task_addr_reg[11]_i_6_n_0 ), + .CO({\current_task_addr_reg[11]_i_4_n_0 ,\current_task_addr_reg[11]_i_4_n_1 ,\current_task_addr_reg[11]_i_4_n_2 ,\current_task_addr_reg[11]_i_4_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in32[11:8]), + .S({\current_task_addr[11]_i_7_n_0 ,\current_task_addr[11]_i_8_n_0 ,\current_task_addr[11]_i_9_n_0 ,\current_task_addr[11]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[11]_i_5 + (.CI(\current_task_addr_reg[3]_i_4_n_0 ), + .CO({\current_task_addr_reg[11]_i_5_n_0 ,\current_task_addr_reg[11]_i_5_n_1 ,\current_task_addr_reg[11]_i_5_n_2 ,\current_task_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in28[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[11]_i_6 + (.CI(\current_task_addr_reg[3]_i_5_n_0 ), + .CO({\current_task_addr_reg[11]_i_6_n_0 ,\current_task_addr_reg[11]_i_6_n_1 ,\current_task_addr_reg[11]_i_6_n_2 ,\current_task_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in32[7:4]), + .S({\current_task_addr[11]_i_11_n_0 ,\current_task_addr[11]_i_12_n_0 ,\current_task_addr[11]_i_13_n_0 ,\current_task_addr[11]_i_14_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[12]_i_3 + (.CI(\current_task_addr_reg[8]_i_3_n_0 ), + .CO({\current_task_addr_reg[12]_i_3_n_0 ,\current_task_addr_reg[12]_i_3_n_1 ,\current_task_addr_reg[12]_i_3_n_2 ,\current_task_addr_reg[12]_i_3_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in27[12:9]), + .S({\current_task_addr[12]_i_5_n_0 ,\current_task_addr[12]_i_6_n_0 ,\current_task_addr[12]_i_7_n_0 ,\current_task_addr[12]_i_8_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[12]_i_4 + (.CI(\current_task_addr_reg[8]_i_4_n_0 ), + .CO({\current_task_addr_reg[12]_i_4_n_0 ,\current_task_addr_reg[12]_i_4_n_1 ,\current_task_addr_reg[12]_i_4_n_2 ,\current_task_addr_reg[12]_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in24[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[13]_i_4 + (.CI(\current_task_addr_reg[11]_i_4_n_0 ), + .CO({\NLW_current_task_addr_reg[13]_i_4_CO_UNCONNECTED [3],\current_task_addr_reg[13]_i_4_n_1 ,\current_task_addr_reg[13]_i_4_n_2 ,\current_task_addr_reg[13]_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in32[15:12]), + .S({\current_task_addr[13]_i_5_n_0 ,\current_task_addr[13]_i_6_n_0 ,\current_task_addr[13]_i_7_n_0 ,\current_task_addr[13]_i_8_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[14]_i_6 + (.CI(\current_task_addr_reg[11]_i_3_n_0 ), + .CO({\NLW_current_task_addr_reg[14]_i_6_CO_UNCONNECTED [3],\current_task_addr_reg[14]_i_6_n_1 ,\current_task_addr_reg[14]_i_6_n_2 ,\current_task_addr_reg[14]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in28[15:12]), + .S(o_mem_addr_OBUF[15:12])); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[15]_i_11 + (.CI(\current_task_addr_reg[12]_i_4_n_0 ), + .CO({\NLW_current_task_addr_reg[15]_i_11_CO_UNCONNECTED [3:2],\current_task_addr_reg[15]_i_11_n_2 ,\current_task_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_task_addr_reg[15]_i_11_O_UNCONNECTED [3],in24[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[15]_i_5 + (.CI(\current_task_addr_reg[12]_i_3_n_0 ), + .CO({\NLW_current_task_addr_reg[15]_i_5_CO_UNCONNECTED [3:2],\current_task_addr_reg[15]_i_5_n_2 ,\current_task_addr_reg[15]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_task_addr_reg[15]_i_5_O_UNCONNECTED [3],in27[15:13]}), + .S({1'b0,\current_task_addr[15]_i_13_n_0 ,\current_task_addr[15]_i_14_n_0 ,\current_task_addr[15]_i_15_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[2]_i_4 + (.CI(1'b0), + .CO({\current_task_addr_reg[2]_i_4_n_0 ,\current_task_addr_reg[2]_i_4_n_1 ,\current_task_addr_reg[2]_i_4_n_2 ,\current_task_addr_reg[2]_i_4_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in24[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[3]_i_4 + (.CI(1'b0), + .CO({\current_task_addr_reg[3]_i_4_n_0 ,\current_task_addr_reg[3]_i_4_n_1 ,\current_task_addr_reg[3]_i_4_n_2 ,\current_task_addr_reg[3]_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in28[3:1],in32[0]}), + .S({o_mem_addr_OBUF[3:2],\current_task_addr[3]_i_6_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[3]_i_5 + (.CI(1'b0), + .CO({\current_task_addr_reg[3]_i_5_n_0 ,\current_task_addr_reg[3]_i_5_n_1 ,\current_task_addr_reg[3]_i_5_n_2 ,\current_task_addr_reg[3]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in32[3:1],\NLW_current_task_addr_reg[3]_i_5_O_UNCONNECTED [0]}), + .S({\current_task_addr[3]_i_7_n_0 ,\current_task_addr[3]_i_8_n_0 ,\current_task_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[4]_i_2 + (.CI(1'b0), + .CO({\current_task_addr_reg[4]_i_2_n_0 ,\current_task_addr_reg[4]_i_2_n_1 ,\current_task_addr_reg[4]_i_2_n_2 ,\current_task_addr_reg[4]_i_2_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in27[4:1]), + .S({\current_task_addr[4]_i_4_n_0 ,\current_task_addr[4]_i_5_n_0 ,\current_task_addr[4]_i_6_n_0 ,\current_task_addr[4]_i_7_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[8]_i_3 + (.CI(\current_task_addr_reg[4]_i_2_n_0 ), + .CO({\current_task_addr_reg[8]_i_3_n_0 ,\current_task_addr_reg[8]_i_3_n_1 ,\current_task_addr_reg[8]_i_3_n_2 ,\current_task_addr_reg[8]_i_3_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in27[8:5]), + .S({\current_task_addr[8]_i_5_n_0 ,\current_task_addr[8]_i_6_n_0 ,\current_task_addr[8]_i_7_n_0 ,\current_task_addr[8]_i_8_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_task_addr_reg[8]_i_4 + (.CI(\current_task_addr_reg[2]_i_4_n_0 ), + .CO({\current_task_addr_reg[8]_i_4_n_0 ,\current_task_addr_reg[8]_i_4_n_1 ,\current_task_addr_reg[8]_i_4_n_2 ,\current_task_addr_reg[8]_i_4_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in24[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_task_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\current_task_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000F8)) + \current_task_id[5]_i_1 + (.I0(i_start_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(\FSM_onehot_state_reg_n_0_[0] ), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_task_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555444)) + \current_task_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[0] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_task_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_task_id[0]), + .R(\current_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_task_id[1]), + .R(\current_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_task_id[2]), + .R(\current_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_task_id[3]), + .R(\current_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_task_id[4]), + .R(\current_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_task_id[5]), + .R(\current_task_id[5]_i_1_n_0 )); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[0]_i_1 + (.I0(\o_mem_data[7]_i_3_n_0 ), + .I1(i_mem_data_IBUF[0]), + .I2(\o_mem_data[0]_i_2_n_0 ), + .I3(i_task_priority_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_number_of_task[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFF200)) + \o_mem_data[1]_i_1 + (.I0(i_mem_data_IBUF[1]), + .I1(\o_mem_data[1]_i_2_n_0 ), + .I2(i_task_priority_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\o_mem_data[1]_i_3_n_0 ), + .I5(\o_mem_data[1]_i_4_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0000000000000002)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(o_mem_addr_OBUF[1]), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'hFF282828)) + \o_mem_data[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[0]), + .I2(current_number_of_task[1]), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(i_mem_data_IBUF[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h44440FF044440000)) + \o_mem_data[1]_i_4 + (.I0(\o_mem_data[1]_i_5_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(i_mem_data_IBUF[0]), + .I3(i_mem_data_IBUF[1]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[5] ), + .O(\o_mem_data[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_5 + (.I0(current_number_of_task[0]), + .I1(current_number_of_task[1]), + .O(\o_mem_data[1]_i_5_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[5]_i_3_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[2]), + .I2(current_number_of_task[1]), + .I3(current_number_of_task[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[5]_i_3_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(i_task_id_IBUF[1]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_number_of_task[3]), + .I2(current_number_of_task[2]), + .I3(current_number_of_task[0]), + .I4(current_number_of_task[1]), + .I5(\FSM_onehot_state[11]_i_1_n_0 ), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[5]_i_3_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\current_number_of_task[4]_i_2_n_0 ), + .I3(\o_mem_data[4]_i_2_n_0 ), + .I4(i_task_id_IBUF[2]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000002)) + \o_mem_data[4]_i_2 + (.I0(\FSM_onehot_state[11]_i_1_n_0 ), + .I1(current_number_of_task[1]), + .I2(current_number_of_task[0]), + .I3(current_number_of_task[3]), + .I4(current_number_of_task[2]), + .I5(current_number_of_task[4]), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hAEFFAEAE)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[5]_i_2_n_0 ), + .I1(i_task_id_IBUF[3]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(\o_mem_data[5]_i_3_n_0 ), + .I4(i_mem_data_IBUF[5]), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4F44FF444444444)) + \o_mem_data[5]_i_2 + (.I0(\current_number_of_task[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_number_of_task[5]), + .I3(\FSM_onehot_state[8]_i_2_n_0 ), + .I4(current_number_of_task[4]), + .I5(\FSM_onehot_state[11]_i_1_n_0 ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h1111111110001111)) + \o_mem_data[5]_i_3 + (.I0(\FSM_onehot_state[21]_i_1_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(i_mem_data_IBUF[0]), + .I3(i_mem_data_IBUF[1]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFC88)) + \o_mem_data[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[6]), + .I2(\o_mem_data[6]_i_2_n_0 ), + .I3(\o_mem_data[6]_i_3_n_0 ), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h8000000000000000)) + \o_mem_data[6]_i_2 + (.I0(i_mem_data_IBUF[4]), + .I1(i_mem_data_IBUF[5]), + .I2(i_mem_data_IBUF[2]), + .I3(i_mem_data_IBUF[3]), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT4 #( + .INIT(16'h0444)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT3 #( + .INIT(8'h28)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_number_of_task[7]_i_3_n_0 ), + .I2(current_number_of_task[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAEAE0C0CFF0C0C0C)) + \o_mem_data[6]_i_5 + (.I0(i_mem_data_IBUF[6]), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_6_n_0 ), + .I3(i_task_id_IBUF[4]), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\o_mem_data[6]_i_7_n_0 ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_6 + (.I0(current_number_of_task[6]), + .I1(current_number_of_task[4]), + .I2(current_number_of_task[5]), + .I3(\FSM_onehot_state[8]_i_2_n_0 ), + .O(\o_mem_data[6]_i_6_n_0 )); + LUT6 #( + .INIT(64'h0B000000BBBB0B00)) + \o_mem_data[6]_i_7 + (.I0(\FSM_onehot_state[21]_i_4_n_0 ), + .I1(\FSM_onehot_state[21]_i_3_n_0 ), + .I2(i_task_priority_IBUF[0]), + .I3(i_mem_data_IBUF[0]), + .I4(i_mem_data_IBUF[1]), + .I5(i_task_priority_IBUF[1]), + .O(\o_mem_data[6]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFAEAEFFAE)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\o_mem_data[7]_i_3_n_0 ), + .I3(\FSM_onehot_state[11]_i_1_n_0 ), + .I4(\o_mem_data[7]_i_4_n_0 ), + .I5(\o_mem_data[7]_i_5_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFF44444444444)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .I1(i_task_id_IBUF[5]), + .I2(\o_mem_data[6]_i_2_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(i_mem_data_IBUF[7]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT2 #( + .INIT(4'h1)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .O(\o_mem_data[7]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h55555565)) + \o_mem_data[7]_i_4 + (.I0(current_number_of_task[7]), + .I1(current_number_of_task[6]), + .I2(\FSM_onehot_state[8]_i_2_n_0 ), + .I3(current_number_of_task[5]), + .I4(current_number_of_task[4]), + .O(\o_mem_data[7]_i_4_n_0 )); + LUT4 #( + .INIT(16'h2A80)) + \o_mem_data[7]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_number_of_task[7]_i_3_n_0 ), + .I2(current_number_of_task[6]), + .I3(current_number_of_task[7]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .I2(o_mem_en_i_2_n_0), + .I3(o_mem_en_i_3_n_0), + .I4(o_mem_we_i_2_n_0), + .I5(\FSM_onehot_state[8]_i_1_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'hFFEA)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg_n_0_[19] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[3] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(\FSM_onehot_state_reg_n_0_[22] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(\FSM_onehot_state_reg_n_0_[13] ), + .O(o_mem_en_i_3_n_0)); + FDRE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF), + .R(1'b0)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(\FSM_onehot_state_reg_n_0_[0] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[22] ), + .O(ctrl_mem_we)); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF0070)) + o_mem_we_i_2 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[5] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .I5(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_we_i_2_n_0)); + FDRE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF), + .R(1'b0)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_addr[15]_i_1_n_0 ), + .D(current_task_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.wdb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.wdb new file mode 100644 index 0000000..6a4b34e Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.wdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vhdl.prj b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vhdl.prj new file mode 100644 index 0000000..18ba9dd --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vhdl.prj @@ -0,0 +1,6 @@ +# compile vhdl design source files +vhdl xil_defaultlib \ +"../../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \ + +# Do not sort compile order +nosort diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vlog.prj b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vlog.prj new file mode 100644 index 0000000..a8e9d9d --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_vlog.prj @@ -0,0 +1,6 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib --include "../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \ +"project_tb_edge_time_synth.v" \ + +# Do not sort compile order +nosort diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.log new file mode 100644 index 0000000..3085892 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.log @@ -0,0 +1,18 @@ +Time resolution is 1 ps +Note: === GRUPPO 0: Reset === +Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.0 OK: reset base +Time: 180 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.1 OK: reset asincrono durante operazione +Time: 1860 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 1: Inserimento === +Time: 1860 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.0 OK: insert in lista vuota +Time: 3613737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: FAIL [1.1 count] addr=0 expected=0x3 actual=0x4 +Time: 6013737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 465 +Failure: FAIL [1.1 pos1] addr=1 expected=0x4 actual=0x0 +Time: 6013737 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 466 +INFO: xsimkernel Simulation Memory Usage: 296232 KB (Peak: 342096 KB), Simulation CPU Usage: 820 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.sh b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.sh new file mode 100755 index 0000000..7115c61 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Thu Jun 11 14:51:06 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim project_tb_edge_time_synth -key {Post-Synthesis:sim_1:Timing:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log" +xsim project_tb_edge_time_synth -key {Post-Synthesis:sim_1:Timing:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xelab.pb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xelab.pb new file mode 100644 index 0000000..105bac3 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xelab.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/Compile_Options.txt new file mode 100644 index 0000000..1216116 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "project_tb_edge_time_synth" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..6c4b97e Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..c9375c3 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o new file mode 100644 index 0000000..4598dcc Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.c b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.c new file mode 100644 index 0000000..8c43c0d --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.c @@ -0,0 +1,3006 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1221(char*, char *); +IKI_DLLESPEC extern void execute_1222(char*, char *); +IKI_DLLESPEC extern void execute_1223(char*, char *); +IKI_DLLESPEC extern void execute_1224(char*, char *); +IKI_DLLESPEC extern void execute_1225(char*, char *); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_4929(char*, char *); +IKI_DLLESPEC extern void execute_4930(char*, char *); +IKI_DLLESPEC extern void execute_4932(char*, char *); +IKI_DLLESPEC extern void execute_4933(char*, char *); +IKI_DLLESPEC extern void execute_4934(char*, char *); +IKI_DLLESPEC extern void execute_4935(char*, char *); +IKI_DLLESPEC extern void execute_4936(char*, char *); +IKI_DLLESPEC extern void execute_4937(char*, char *); +IKI_DLLESPEC extern void execute_4938(char*, char *); +IKI_DLLESPEC extern void execute_4939(char*, char *); +IKI_DLLESPEC extern void execute_4940(char*, char *); +IKI_DLLESPEC extern void execute_4941(char*, char *); +IKI_DLLESPEC extern void execute_4942(char*, char *); +IKI_DLLESPEC extern void execute_4943(char*, char *); +IKI_DLLESPEC extern void execute_4944(char*, char *); +IKI_DLLESPEC extern void execute_4945(char*, char *); +IKI_DLLESPEC extern void execute_4946(char*, char *); +IKI_DLLESPEC extern void execute_4947(char*, char *); +IKI_DLLESPEC extern void execute_4948(char*, char *); +IKI_DLLESPEC extern void execute_4949(char*, char *); +IKI_DLLESPEC extern void execute_4950(char*, char *); +IKI_DLLESPEC extern void execute_4951(char*, char *); +IKI_DLLESPEC extern void execute_4952(char*, char *); +IKI_DLLESPEC extern void execute_4953(char*, char *); +IKI_DLLESPEC extern void execute_4954(char*, char *); +IKI_DLLESPEC extern void execute_4955(char*, char *); +IKI_DLLESPEC extern void execute_4956(char*, char *); +IKI_DLLESPEC extern void execute_4957(char*, char *); +IKI_DLLESPEC extern void execute_4958(char*, char *); +IKI_DLLESPEC extern void execute_4959(char*, char *); +IKI_DLLESPEC extern void execute_4960(char*, char *); +IKI_DLLESPEC extern void execute_4961(char*, char *); +IKI_DLLESPEC extern void execute_4962(char*, char *); +IKI_DLLESPEC extern void execute_4963(char*, char *); +IKI_DLLESPEC extern void execute_4964(char*, char *); +IKI_DLLESPEC extern void execute_4965(char*, char *); +IKI_DLLESPEC extern void execute_4966(char*, char *); +IKI_DLLESPEC extern void execute_4967(char*, char *); +IKI_DLLESPEC extern void execute_4968(char*, char *); +IKI_DLLESPEC extern void execute_4969(char*, char *); +IKI_DLLESPEC extern void execute_4970(char*, char *); +IKI_DLLESPEC extern void execute_4971(char*, char *); +IKI_DLLESPEC extern void execute_4972(char*, char *); +IKI_DLLESPEC extern void execute_4973(char*, char *); +IKI_DLLESPEC extern void execute_4974(char*, char *); +IKI_DLLESPEC extern void execute_4975(char*, char *); +IKI_DLLESPEC extern void execute_4976(char*, char *); +IKI_DLLESPEC extern void execute_4977(char*, char *); +IKI_DLLESPEC extern void execute_4978(char*, char *); +IKI_DLLESPEC extern void execute_4979(char*, char *); +IKI_DLLESPEC extern void execute_4980(char*, char *); +IKI_DLLESPEC extern void execute_4981(char*, char *); +IKI_DLLESPEC extern void execute_4982(char*, char *); +IKI_DLLESPEC extern void execute_4983(char*, char *); +IKI_DLLESPEC extern void execute_4984(char*, char *); +IKI_DLLESPEC extern void execute_4985(char*, char *); +IKI_DLLESPEC extern void execute_4986(char*, char *); +IKI_DLLESPEC extern void execute_4987(char*, char *); +IKI_DLLESPEC extern void execute_4988(char*, char *); +IKI_DLLESPEC extern void execute_4989(char*, char *); +IKI_DLLESPEC extern void execute_4990(char*, char *); +IKI_DLLESPEC extern void execute_4991(char*, char *); +IKI_DLLESPEC extern void execute_4992(char*, char *); +IKI_DLLESPEC extern void execute_4993(char*, char *); +IKI_DLLESPEC extern void execute_4994(char*, char *); +IKI_DLLESPEC extern void execute_4995(char*, char *); +IKI_DLLESPEC extern void execute_4996(char*, char *); +IKI_DLLESPEC extern void execute_4997(char*, char *); +IKI_DLLESPEC extern void execute_4998(char*, char *); +IKI_DLLESPEC extern void execute_4999(char*, char *); +IKI_DLLESPEC extern void execute_5000(char*, char *); +IKI_DLLESPEC extern void execute_5001(char*, char *); +IKI_DLLESPEC extern void execute_5002(char*, char *); +IKI_DLLESPEC extern void execute_5003(char*, char *); +IKI_DLLESPEC extern void execute_5004(char*, char *); +IKI_DLLESPEC extern void execute_5005(char*, char *); +IKI_DLLESPEC extern void execute_5006(char*, char *); +IKI_DLLESPEC extern void execute_5007(char*, char *); +IKI_DLLESPEC extern void execute_5008(char*, char *); +IKI_DLLESPEC extern void execute_5009(char*, char *); +IKI_DLLESPEC extern void execute_5010(char*, char *); +IKI_DLLESPEC extern void execute_5011(char*, char *); +IKI_DLLESPEC extern void execute_5012(char*, char *); +IKI_DLLESPEC extern void execute_5013(char*, char *); +IKI_DLLESPEC extern void execute_5014(char*, char *); +IKI_DLLESPEC extern void execute_5015(char*, char *); +IKI_DLLESPEC extern void execute_5016(char*, char *); +IKI_DLLESPEC extern void execute_5017(char*, char *); +IKI_DLLESPEC extern void execute_5018(char*, char *); +IKI_DLLESPEC extern void execute_5019(char*, char *); +IKI_DLLESPEC extern void execute_5020(char*, char *); +IKI_DLLESPEC extern void execute_5021(char*, char *); +IKI_DLLESPEC extern void execute_5022(char*, char *); +IKI_DLLESPEC extern void execute_5023(char*, char *); +IKI_DLLESPEC extern void execute_5024(char*, char *); +IKI_DLLESPEC extern void execute_5025(char*, char *); +IKI_DLLESPEC extern void execute_5026(char*, char *); +IKI_DLLESPEC extern void execute_5027(char*, char *); +IKI_DLLESPEC extern void execute_5028(char*, char *); +IKI_DLLESPEC extern void execute_5029(char*, char *); +IKI_DLLESPEC extern void execute_5030(char*, char *); +IKI_DLLESPEC extern void execute_5031(char*, char *); +IKI_DLLESPEC extern void execute_5032(char*, char *); +IKI_DLLESPEC extern void execute_5033(char*, char *); +IKI_DLLESPEC extern void execute_5034(char*, char *); +IKI_DLLESPEC extern void execute_5035(char*, char *); +IKI_DLLESPEC extern void execute_5036(char*, char *); +IKI_DLLESPEC extern void execute_5037(char*, char *); +IKI_DLLESPEC extern void execute_5038(char*, char *); +IKI_DLLESPEC extern void execute_5039(char*, char *); +IKI_DLLESPEC extern void execute_5040(char*, char *); +IKI_DLLESPEC extern void execute_5041(char*, char *); +IKI_DLLESPEC extern void execute_5042(char*, char *); +IKI_DLLESPEC extern void execute_5043(char*, char *); +IKI_DLLESPEC extern void execute_5044(char*, char *); +IKI_DLLESPEC extern void execute_5045(char*, char *); +IKI_DLLESPEC extern void execute_5046(char*, char *); +IKI_DLLESPEC extern void execute_5047(char*, char *); +IKI_DLLESPEC extern void execute_5048(char*, char *); +IKI_DLLESPEC extern void execute_5049(char*, char *); +IKI_DLLESPEC extern void execute_5050(char*, char *); +IKI_DLLESPEC extern void execute_5051(char*, char *); +IKI_DLLESPEC extern void execute_5052(char*, char *); +IKI_DLLESPEC extern void execute_5053(char*, char *); +IKI_DLLESPEC extern void execute_5054(char*, char *); +IKI_DLLESPEC extern void execute_5055(char*, char *); +IKI_DLLESPEC extern void execute_5056(char*, char *); +IKI_DLLESPEC extern void execute_5057(char*, char *); +IKI_DLLESPEC extern void execute_5058(char*, char *); +IKI_DLLESPEC extern void execute_5059(char*, char *); +IKI_DLLESPEC extern void execute_5060(char*, char *); +IKI_DLLESPEC extern void execute_5061(char*, char *); +IKI_DLLESPEC extern void execute_5062(char*, char *); +IKI_DLLESPEC extern void execute_5063(char*, char *); +IKI_DLLESPEC extern void execute_5064(char*, char *); +IKI_DLLESPEC extern void execute_5065(char*, char *); +IKI_DLLESPEC extern void execute_5066(char*, char *); +IKI_DLLESPEC extern void execute_5067(char*, char *); +IKI_DLLESPEC extern void execute_5068(char*, char *); +IKI_DLLESPEC extern void execute_5069(char*, char *); +IKI_DLLESPEC extern void execute_5070(char*, char *); +IKI_DLLESPEC extern void execute_5071(char*, char *); +IKI_DLLESPEC extern void execute_5072(char*, char *); +IKI_DLLESPEC extern void execute_5073(char*, char *); +IKI_DLLESPEC extern void execute_5074(char*, char *); +IKI_DLLESPEC extern void execute_5075(char*, char *); +IKI_DLLESPEC extern void execute_5076(char*, char *); +IKI_DLLESPEC extern void execute_5077(char*, char *); +IKI_DLLESPEC extern void execute_5078(char*, char *); +IKI_DLLESPEC extern void execute_5079(char*, char *); +IKI_DLLESPEC extern void execute_5080(char*, char *); +IKI_DLLESPEC extern void execute_5081(char*, char *); +IKI_DLLESPEC extern void execute_5082(char*, char *); +IKI_DLLESPEC extern void execute_5083(char*, char *); +IKI_DLLESPEC extern void execute_5084(char*, char *); +IKI_DLLESPEC extern void execute_5085(char*, char *); +IKI_DLLESPEC extern void execute_5086(char*, char *); +IKI_DLLESPEC extern void execute_5087(char*, char *); +IKI_DLLESPEC extern void execute_5088(char*, char *); +IKI_DLLESPEC extern void execute_5089(char*, char *); +IKI_DLLESPEC extern void execute_5090(char*, char *); +IKI_DLLESPEC extern void execute_5091(char*, char *); +IKI_DLLESPEC extern void execute_5092(char*, char *); +IKI_DLLESPEC extern void execute_5093(char*, char *); +IKI_DLLESPEC extern void execute_5094(char*, char *); +IKI_DLLESPEC extern void execute_5095(char*, char *); +IKI_DLLESPEC extern void execute_5096(char*, char *); +IKI_DLLESPEC extern void execute_5097(char*, char *); +IKI_DLLESPEC extern void execute_5098(char*, char *); +IKI_DLLESPEC extern void execute_5099(char*, char *); +IKI_DLLESPEC extern void execute_5100(char*, char *); +IKI_DLLESPEC extern void execute_5101(char*, char *); +IKI_DLLESPEC extern void execute_5102(char*, char *); +IKI_DLLESPEC extern void execute_5103(char*, char *); +IKI_DLLESPEC extern void execute_5104(char*, char *); +IKI_DLLESPEC extern void execute_5105(char*, char *); +IKI_DLLESPEC extern void execute_5106(char*, char *); +IKI_DLLESPEC extern void execute_5107(char*, char *); +IKI_DLLESPEC extern void execute_5108(char*, char *); +IKI_DLLESPEC extern void execute_5109(char*, char *); +IKI_DLLESPEC extern void execute_5110(char*, char *); +IKI_DLLESPEC extern void execute_5111(char*, char *); +IKI_DLLESPEC extern void execute_5112(char*, char *); +IKI_DLLESPEC extern void execute_5113(char*, char *); +IKI_DLLESPEC extern void execute_5114(char*, char *); +IKI_DLLESPEC extern void execute_5115(char*, char *); +IKI_DLLESPEC extern void execute_5116(char*, char *); +IKI_DLLESPEC extern void execute_5117(char*, char *); +IKI_DLLESPEC extern void execute_5118(char*, char *); +IKI_DLLESPEC extern void execute_5119(char*, char *); +IKI_DLLESPEC extern void execute_5120(char*, char *); +IKI_DLLESPEC extern void execute_5121(char*, char *); +IKI_DLLESPEC extern void execute_5122(char*, char *); +IKI_DLLESPEC extern void execute_5123(char*, char *); +IKI_DLLESPEC extern void execute_5124(char*, char *); +IKI_DLLESPEC extern void execute_5125(char*, char *); +IKI_DLLESPEC extern void execute_5126(char*, char *); +IKI_DLLESPEC extern void execute_5127(char*, char *); +IKI_DLLESPEC extern void execute_5128(char*, char *); +IKI_DLLESPEC extern void execute_5129(char*, char *); +IKI_DLLESPEC extern void execute_5130(char*, char *); +IKI_DLLESPEC extern void execute_5131(char*, char *); +IKI_DLLESPEC extern void execute_5132(char*, char *); +IKI_DLLESPEC extern void execute_5133(char*, char *); +IKI_DLLESPEC extern void execute_5134(char*, char *); +IKI_DLLESPEC extern void execute_5135(char*, char *); +IKI_DLLESPEC extern void execute_5136(char*, char *); +IKI_DLLESPEC extern void execute_5137(char*, char *); +IKI_DLLESPEC extern void execute_5138(char*, char *); +IKI_DLLESPEC extern void execute_5139(char*, char *); +IKI_DLLESPEC extern void execute_5140(char*, char *); +IKI_DLLESPEC extern void execute_5141(char*, char *); +IKI_DLLESPEC extern void execute_5142(char*, char *); +IKI_DLLESPEC extern void execute_5143(char*, char *); +IKI_DLLESPEC extern void execute_5144(char*, char *); +IKI_DLLESPEC extern void execute_5145(char*, char *); +IKI_DLLESPEC extern void execute_5146(char*, char *); +IKI_DLLESPEC extern void execute_5147(char*, char *); +IKI_DLLESPEC extern void execute_5148(char*, char *); +IKI_DLLESPEC extern void execute_5149(char*, char *); +IKI_DLLESPEC extern void execute_5150(char*, char *); +IKI_DLLESPEC extern void execute_5151(char*, char *); +IKI_DLLESPEC extern void execute_5152(char*, char *); +IKI_DLLESPEC extern void execute_5153(char*, char *); +IKI_DLLESPEC extern void execute_5154(char*, char *); +IKI_DLLESPEC extern void execute_5155(char*, char *); +IKI_DLLESPEC extern void execute_5156(char*, char *); +IKI_DLLESPEC extern void execute_5157(char*, char *); +IKI_DLLESPEC extern void execute_5158(char*, char *); +IKI_DLLESPEC extern void execute_5159(char*, char *); +IKI_DLLESPEC extern void execute_5160(char*, char *); +IKI_DLLESPEC extern void execute_5161(char*, char *); +IKI_DLLESPEC extern void execute_5162(char*, char *); +IKI_DLLESPEC extern void execute_5163(char*, char *); +IKI_DLLESPEC extern void execute_5164(char*, char *); +IKI_DLLESPEC extern void execute_5165(char*, char *); +IKI_DLLESPEC extern void execute_5166(char*, char *); +IKI_DLLESPEC extern void execute_5167(char*, char *); +IKI_DLLESPEC extern void execute_5168(char*, char *); +IKI_DLLESPEC extern void execute_5169(char*, char *); +IKI_DLLESPEC extern void execute_5170(char*, char *); +IKI_DLLESPEC extern void execute_5171(char*, char *); +IKI_DLLESPEC extern void execute_5172(char*, char *); +IKI_DLLESPEC extern void execute_5173(char*, char *); +IKI_DLLESPEC extern void execute_5174(char*, char *); +IKI_DLLESPEC extern void execute_5175(char*, char *); +IKI_DLLESPEC extern void execute_5176(char*, char *); +IKI_DLLESPEC extern void execute_5177(char*, char *); +IKI_DLLESPEC extern void execute_5178(char*, char *); +IKI_DLLESPEC extern void execute_5179(char*, char *); +IKI_DLLESPEC extern void execute_5180(char*, char *); +IKI_DLLESPEC extern void execute_5181(char*, char *); +IKI_DLLESPEC extern void execute_5182(char*, char *); +IKI_DLLESPEC extern void execute_5183(char*, char *); +IKI_DLLESPEC extern void execute_5184(char*, char *); +IKI_DLLESPEC extern void execute_5185(char*, char *); +IKI_DLLESPEC extern void execute_5186(char*, char *); +IKI_DLLESPEC extern void execute_5187(char*, char *); +IKI_DLLESPEC extern void execute_5188(char*, char *); +IKI_DLLESPEC extern void execute_5189(char*, char *); +IKI_DLLESPEC extern void execute_5190(char*, char *); +IKI_DLLESPEC extern void execute_5191(char*, char *); +IKI_DLLESPEC extern void execute_5192(char*, char *); +IKI_DLLESPEC extern void execute_5193(char*, char *); +IKI_DLLESPEC extern void execute_5194(char*, char *); +IKI_DLLESPEC extern void execute_5195(char*, char *); +IKI_DLLESPEC extern void execute_5196(char*, char *); +IKI_DLLESPEC extern void execute_5197(char*, char *); +IKI_DLLESPEC extern void execute_5198(char*, char *); +IKI_DLLESPEC extern void execute_5199(char*, char *); +IKI_DLLESPEC extern void execute_5200(char*, char *); +IKI_DLLESPEC extern void execute_5201(char*, char *); +IKI_DLLESPEC extern void execute_5202(char*, char *); +IKI_DLLESPEC extern void execute_5203(char*, char *); +IKI_DLLESPEC extern void execute_5204(char*, char *); +IKI_DLLESPEC extern void execute_5205(char*, char *); +IKI_DLLESPEC extern void execute_5206(char*, char *); +IKI_DLLESPEC extern void execute_5207(char*, char *); +IKI_DLLESPEC extern void execute_5208(char*, char *); +IKI_DLLESPEC extern void execute_5209(char*, char *); +IKI_DLLESPEC extern void execute_5210(char*, char *); +IKI_DLLESPEC extern void execute_5211(char*, char *); +IKI_DLLESPEC extern void execute_5212(char*, char *); +IKI_DLLESPEC extern void execute_5213(char*, char *); +IKI_DLLESPEC extern void execute_5214(char*, char *); +IKI_DLLESPEC extern void execute_5215(char*, char *); +IKI_DLLESPEC extern void execute_5216(char*, char *); +IKI_DLLESPEC extern void execute_5217(char*, char *); +IKI_DLLESPEC extern void execute_5218(char*, char *); +IKI_DLLESPEC extern void execute_5219(char*, char *); +IKI_DLLESPEC extern void execute_5220(char*, char *); +IKI_DLLESPEC extern void execute_5221(char*, char *); +IKI_DLLESPEC extern void execute_5222(char*, char *); +IKI_DLLESPEC extern void execute_5223(char*, char *); +IKI_DLLESPEC extern void execute_5224(char*, char *); +IKI_DLLESPEC extern void execute_5225(char*, char *); +IKI_DLLESPEC extern void execute_5226(char*, char *); +IKI_DLLESPEC extern void execute_5227(char*, char *); +IKI_DLLESPEC extern void execute_5228(char*, char *); +IKI_DLLESPEC extern void execute_5229(char*, char *); +IKI_DLLESPEC extern void execute_5230(char*, char *); +IKI_DLLESPEC extern void execute_5231(char*, char *); +IKI_DLLESPEC extern void execute_5232(char*, char *); +IKI_DLLESPEC extern void execute_5233(char*, char *); +IKI_DLLESPEC extern void execute_5234(char*, char *); +IKI_DLLESPEC extern void execute_5235(char*, char *); +IKI_DLLESPEC extern void execute_5236(char*, char *); +IKI_DLLESPEC extern void execute_5237(char*, char *); +IKI_DLLESPEC extern void execute_5238(char*, char *); +IKI_DLLESPEC extern void execute_5239(char*, char *); +IKI_DLLESPEC extern void execute_5240(char*, char *); +IKI_DLLESPEC extern void execute_5241(char*, char *); +IKI_DLLESPEC extern void execute_5242(char*, char *); +IKI_DLLESPEC extern void execute_5243(char*, char *); +IKI_DLLESPEC extern void execute_5244(char*, char *); +IKI_DLLESPEC extern void execute_5245(char*, char *); +IKI_DLLESPEC extern void execute_5246(char*, char *); +IKI_DLLESPEC extern void execute_5247(char*, char *); +IKI_DLLESPEC extern void execute_5248(char*, char *); +IKI_DLLESPEC extern void execute_5249(char*, char *); +IKI_DLLESPEC extern void execute_5250(char*, char *); +IKI_DLLESPEC extern void execute_5251(char*, char *); +IKI_DLLESPEC extern void execute_5252(char*, char *); +IKI_DLLESPEC extern void execute_5253(char*, char *); +IKI_DLLESPEC extern void execute_5254(char*, char *); +IKI_DLLESPEC extern void execute_5255(char*, char *); +IKI_DLLESPEC extern void execute_5256(char*, char *); +IKI_DLLESPEC extern void execute_5257(char*, char *); +IKI_DLLESPEC extern void execute_5258(char*, char *); +IKI_DLLESPEC extern void execute_5259(char*, char *); +IKI_DLLESPEC extern void execute_5260(char*, char *); +IKI_DLLESPEC extern void execute_5261(char*, char *); +IKI_DLLESPEC extern void execute_5262(char*, char *); +IKI_DLLESPEC extern void execute_5263(char*, char *); +IKI_DLLESPEC extern void execute_5264(char*, char *); +IKI_DLLESPEC extern void execute_5265(char*, char *); +IKI_DLLESPEC extern void execute_5266(char*, char *); +IKI_DLLESPEC extern void execute_5267(char*, char *); +IKI_DLLESPEC extern void execute_5268(char*, char *); +IKI_DLLESPEC extern void execute_5269(char*, char *); +IKI_DLLESPEC extern void execute_5270(char*, char *); +IKI_DLLESPEC extern void execute_5271(char*, char *); +IKI_DLLESPEC extern void execute_5272(char*, char *); +IKI_DLLESPEC extern void execute_5273(char*, char *); +IKI_DLLESPEC extern void execute_5274(char*, char *); +IKI_DLLESPEC extern void execute_5275(char*, char *); +IKI_DLLESPEC extern void execute_5276(char*, char *); +IKI_DLLESPEC extern void execute_5277(char*, char *); +IKI_DLLESPEC extern void execute_5278(char*, char *); +IKI_DLLESPEC extern void execute_5279(char*, char *); +IKI_DLLESPEC extern void execute_5280(char*, char *); +IKI_DLLESPEC extern void execute_5281(char*, char *); +IKI_DLLESPEC extern void execute_5282(char*, char *); +IKI_DLLESPEC extern void execute_5283(char*, char *); +IKI_DLLESPEC extern void execute_5284(char*, char *); +IKI_DLLESPEC extern void execute_5285(char*, char *); +IKI_DLLESPEC extern void execute_5286(char*, char *); +IKI_DLLESPEC extern void execute_5287(char*, char *); +IKI_DLLESPEC extern void execute_5288(char*, char *); +IKI_DLLESPEC extern void execute_5289(char*, char *); +IKI_DLLESPEC extern void execute_5290(char*, char *); +IKI_DLLESPEC extern void execute_5291(char*, char *); +IKI_DLLESPEC extern void execute_5292(char*, char *); +IKI_DLLESPEC extern void execute_5293(char*, char *); +IKI_DLLESPEC extern void execute_5294(char*, char *); +IKI_DLLESPEC extern void execute_5295(char*, char *); +IKI_DLLESPEC extern void execute_5296(char*, char *); +IKI_DLLESPEC extern void execute_5297(char*, char *); +IKI_DLLESPEC extern void execute_5298(char*, char *); +IKI_DLLESPEC extern void execute_5299(char*, char *); +IKI_DLLESPEC extern void execute_5300(char*, char *); +IKI_DLLESPEC extern void execute_5301(char*, char *); +IKI_DLLESPEC extern void execute_5302(char*, char *); +IKI_DLLESPEC extern void execute_5303(char*, char *); +IKI_DLLESPEC extern void execute_5304(char*, char *); +IKI_DLLESPEC extern void execute_5305(char*, char *); +IKI_DLLESPEC extern void execute_5306(char*, char *); +IKI_DLLESPEC extern void execute_5307(char*, char *); +IKI_DLLESPEC extern void execute_5308(char*, char *); +IKI_DLLESPEC extern void execute_5309(char*, char *); +IKI_DLLESPEC extern void execute_5310(char*, char *); +IKI_DLLESPEC extern void execute_5311(char*, char *); +IKI_DLLESPEC extern void execute_5312(char*, char *); +IKI_DLLESPEC extern void execute_5313(char*, char *); +IKI_DLLESPEC extern void execute_5314(char*, char *); +IKI_DLLESPEC extern void execute_5315(char*, char *); +IKI_DLLESPEC extern void execute_5316(char*, char *); +IKI_DLLESPEC extern void execute_5317(char*, char *); +IKI_DLLESPEC extern void execute_5318(char*, char *); +IKI_DLLESPEC extern void execute_5319(char*, char *); +IKI_DLLESPEC extern void execute_5320(char*, char *); +IKI_DLLESPEC extern void execute_5321(char*, char *); +IKI_DLLESPEC extern void execute_5322(char*, char *); +IKI_DLLESPEC extern void execute_5323(char*, char *); +IKI_DLLESPEC extern void execute_5324(char*, char *); +IKI_DLLESPEC extern void execute_5325(char*, char *); +IKI_DLLESPEC extern void execute_5326(char*, char *); +IKI_DLLESPEC extern void execute_5327(char*, char *); +IKI_DLLESPEC extern void execute_5328(char*, char *); +IKI_DLLESPEC extern void execute_5329(char*, char *); +IKI_DLLESPEC extern void execute_5330(char*, char *); +IKI_DLLESPEC extern void execute_5331(char*, char *); +IKI_DLLESPEC extern void execute_5332(char*, char *); +IKI_DLLESPEC extern void execute_5333(char*, char *); +IKI_DLLESPEC extern void execute_5334(char*, char *); +IKI_DLLESPEC extern void execute_5335(char*, char *); +IKI_DLLESPEC extern void execute_5336(char*, char *); +IKI_DLLESPEC extern void execute_5337(char*, char *); +IKI_DLLESPEC extern void execute_5338(char*, char *); +IKI_DLLESPEC extern void execute_5339(char*, char *); +IKI_DLLESPEC extern void execute_5340(char*, char *); +IKI_DLLESPEC extern void execute_5341(char*, char *); +IKI_DLLESPEC extern void execute_5342(char*, char *); +IKI_DLLESPEC extern void execute_5343(char*, char *); +IKI_DLLESPEC extern void execute_5344(char*, char *); +IKI_DLLESPEC extern void execute_5345(char*, char *); +IKI_DLLESPEC extern void execute_5346(char*, char *); +IKI_DLLESPEC extern void execute_5347(char*, char *); +IKI_DLLESPEC extern void execute_5348(char*, char *); +IKI_DLLESPEC extern void execute_5349(char*, char *); +IKI_DLLESPEC extern void execute_5350(char*, char *); +IKI_DLLESPEC extern void execute_5351(char*, char *); +IKI_DLLESPEC extern void execute_5352(char*, char *); +IKI_DLLESPEC extern void execute_5353(char*, char *); +IKI_DLLESPEC extern void execute_5354(char*, char *); +IKI_DLLESPEC extern void execute_5355(char*, char *); +IKI_DLLESPEC extern void execute_5356(char*, char *); +IKI_DLLESPEC extern void execute_5357(char*, char *); +IKI_DLLESPEC extern void execute_5358(char*, char *); +IKI_DLLESPEC extern void execute_5359(char*, char *); +IKI_DLLESPEC extern void execute_5360(char*, char *); +IKI_DLLESPEC extern void execute_5361(char*, char *); +IKI_DLLESPEC extern void execute_5362(char*, char *); +IKI_DLLESPEC extern void execute_5363(char*, char *); +IKI_DLLESPEC extern void execute_5364(char*, char *); +IKI_DLLESPEC extern void execute_5365(char*, char *); +IKI_DLLESPEC extern void execute_5366(char*, char *); +IKI_DLLESPEC extern void execute_5367(char*, char *); +IKI_DLLESPEC extern void execute_5368(char*, char *); +IKI_DLLESPEC extern void execute_5369(char*, char *); +IKI_DLLESPEC extern void execute_5370(char*, char *); +IKI_DLLESPEC extern void execute_5371(char*, char *); +IKI_DLLESPEC extern void execute_5372(char*, char *); +IKI_DLLESPEC extern void execute_5373(char*, char *); +IKI_DLLESPEC extern void execute_5374(char*, char *); +IKI_DLLESPEC extern void execute_5375(char*, char *); +IKI_DLLESPEC extern void execute_5376(char*, char *); +IKI_DLLESPEC extern void execute_5377(char*, char *); +IKI_DLLESPEC extern void execute_5378(char*, char *); +IKI_DLLESPEC extern void execute_5379(char*, char *); +IKI_DLLESPEC extern void execute_5380(char*, char *); +IKI_DLLESPEC extern void execute_5381(char*, char *); +IKI_DLLESPEC extern void execute_5382(char*, char *); +IKI_DLLESPEC extern void execute_5383(char*, char *); +IKI_DLLESPEC extern void execute_5384(char*, char *); +IKI_DLLESPEC extern void execute_5385(char*, char *); +IKI_DLLESPEC extern void execute_5386(char*, char *); +IKI_DLLESPEC extern void execute_5387(char*, char *); +IKI_DLLESPEC extern void execute_5388(char*, char *); +IKI_DLLESPEC extern void execute_5389(char*, char *); +IKI_DLLESPEC extern void execute_5390(char*, char *); +IKI_DLLESPEC extern void execute_5391(char*, char *); +IKI_DLLESPEC extern void execute_5392(char*, char *); +IKI_DLLESPEC extern void execute_5393(char*, char *); +IKI_DLLESPEC extern void execute_5394(char*, char *); +IKI_DLLESPEC extern void execute_5395(char*, char *); +IKI_DLLESPEC extern void execute_5396(char*, char *); +IKI_DLLESPEC extern void execute_5397(char*, char *); +IKI_DLLESPEC extern void execute_5398(char*, char *); +IKI_DLLESPEC extern void execute_5399(char*, char *); +IKI_DLLESPEC extern void execute_5400(char*, char *); +IKI_DLLESPEC extern void execute_5401(char*, char *); +IKI_DLLESPEC extern void execute_5402(char*, char *); +IKI_DLLESPEC extern void execute_5403(char*, char *); +IKI_DLLESPEC extern void execute_5404(char*, char *); +IKI_DLLESPEC extern void execute_5405(char*, char *); +IKI_DLLESPEC extern void execute_5406(char*, char *); +IKI_DLLESPEC extern void execute_5407(char*, char *); +IKI_DLLESPEC extern void execute_5408(char*, char *); +IKI_DLLESPEC extern void execute_5409(char*, char *); +IKI_DLLESPEC extern void execute_5410(char*, char *); +IKI_DLLESPEC extern void execute_5411(char*, char *); +IKI_DLLESPEC extern void execute_5412(char*, char *); +IKI_DLLESPEC extern void execute_5413(char*, char *); +IKI_DLLESPEC extern void execute_5414(char*, char *); +IKI_DLLESPEC extern void execute_5415(char*, char *); +IKI_DLLESPEC extern void execute_5416(char*, char *); +IKI_DLLESPEC extern void execute_5417(char*, char *); +IKI_DLLESPEC extern void execute_5418(char*, char *); +IKI_DLLESPEC extern void execute_5419(char*, char *); +IKI_DLLESPEC extern void execute_5420(char*, char *); +IKI_DLLESPEC extern void execute_5421(char*, char *); +IKI_DLLESPEC extern void execute_5422(char*, char *); +IKI_DLLESPEC extern void execute_5423(char*, char *); +IKI_DLLESPEC extern void execute_5424(char*, char *); +IKI_DLLESPEC extern void execute_5425(char*, char *); +IKI_DLLESPEC extern void execute_5426(char*, char *); +IKI_DLLESPEC extern void execute_5427(char*, char *); +IKI_DLLESPEC extern void execute_5428(char*, char *); +IKI_DLLESPEC extern void execute_5429(char*, char *); +IKI_DLLESPEC extern void execute_5430(char*, char *); +IKI_DLLESPEC extern void execute_5431(char*, char *); +IKI_DLLESPEC extern void execute_5432(char*, char *); +IKI_DLLESPEC extern void execute_5433(char*, char *); +IKI_DLLESPEC extern void execute_5434(char*, char *); +IKI_DLLESPEC extern void execute_5435(char*, char *); +IKI_DLLESPEC extern void execute_5436(char*, char *); +IKI_DLLESPEC extern void execute_5437(char*, char *); +IKI_DLLESPEC extern void execute_5438(char*, char *); +IKI_DLLESPEC extern void execute_5439(char*, char *); +IKI_DLLESPEC extern void execute_5440(char*, char *); +IKI_DLLESPEC extern void execute_5441(char*, char *); +IKI_DLLESPEC extern void execute_5442(char*, char *); +IKI_DLLESPEC extern void execute_5443(char*, char *); +IKI_DLLESPEC extern void execute_5444(char*, char *); +IKI_DLLESPEC extern void execute_5445(char*, char *); +IKI_DLLESPEC extern void execute_5446(char*, char *); +IKI_DLLESPEC extern void execute_5447(char*, char *); +IKI_DLLESPEC extern void execute_5448(char*, char *); +IKI_DLLESPEC extern void execute_5449(char*, char *); +IKI_DLLESPEC extern void execute_5450(char*, char *); +IKI_DLLESPEC extern void execute_5451(char*, char *); +IKI_DLLESPEC extern void execute_5452(char*, char *); +IKI_DLLESPEC extern void execute_5453(char*, char *); +IKI_DLLESPEC extern void execute_5454(char*, char *); +IKI_DLLESPEC extern void execute_5455(char*, char *); +IKI_DLLESPEC extern void execute_5456(char*, char *); +IKI_DLLESPEC extern void execute_5457(char*, char *); +IKI_DLLESPEC extern void execute_5458(char*, char *); +IKI_DLLESPEC extern void execute_5459(char*, char *); +IKI_DLLESPEC extern void execute_5460(char*, char *); +IKI_DLLESPEC extern void execute_5461(char*, char *); +IKI_DLLESPEC extern void execute_5462(char*, char *); +IKI_DLLESPEC extern void execute_5463(char*, char *); +IKI_DLLESPEC extern void execute_5464(char*, char *); +IKI_DLLESPEC extern void execute_5465(char*, char *); +IKI_DLLESPEC extern void execute_5466(char*, char *); +IKI_DLLESPEC extern void execute_5467(char*, char *); +IKI_DLLESPEC extern void execute_5468(char*, char *); +IKI_DLLESPEC extern void execute_5469(char*, char *); +IKI_DLLESPEC extern void execute_5470(char*, char *); +IKI_DLLESPEC extern void execute_5471(char*, char *); +IKI_DLLESPEC extern void execute_5472(char*, char *); +IKI_DLLESPEC extern void execute_5473(char*, char *); +IKI_DLLESPEC extern void execute_5474(char*, char *); +IKI_DLLESPEC extern void execute_5475(char*, char *); +IKI_DLLESPEC extern void execute_5476(char*, char *); +IKI_DLLESPEC extern void execute_5477(char*, char *); +IKI_DLLESPEC extern void execute_5478(char*, char *); +IKI_DLLESPEC extern void execute_5479(char*, char *); +IKI_DLLESPEC extern void execute_5480(char*, char *); +IKI_DLLESPEC extern void execute_5481(char*, char *); +IKI_DLLESPEC extern void execute_5482(char*, char *); +IKI_DLLESPEC extern void execute_5483(char*, char *); +IKI_DLLESPEC extern void execute_5484(char*, char *); +IKI_DLLESPEC extern void execute_5485(char*, char *); +IKI_DLLESPEC extern void execute_5486(char*, char *); +IKI_DLLESPEC extern void execute_5487(char*, char *); +IKI_DLLESPEC extern void execute_5488(char*, char *); +IKI_DLLESPEC extern void execute_5489(char*, char *); +IKI_DLLESPEC extern void execute_5490(char*, char *); +IKI_DLLESPEC extern void execute_5491(char*, char *); +IKI_DLLESPEC extern void execute_5492(char*, char *); +IKI_DLLESPEC extern void execute_5493(char*, char *); +IKI_DLLESPEC extern void execute_5494(char*, char *); +IKI_DLLESPEC extern void execute_5495(char*, char *); +IKI_DLLESPEC extern void execute_5496(char*, char *); +IKI_DLLESPEC extern void execute_5497(char*, char *); +IKI_DLLESPEC extern void execute_5498(char*, char *); +IKI_DLLESPEC extern void execute_5499(char*, char *); +IKI_DLLESPEC extern void execute_5500(char*, char *); +IKI_DLLESPEC extern void execute_5501(char*, char *); +IKI_DLLESPEC extern void execute_5502(char*, char *); +IKI_DLLESPEC extern void execute_5503(char*, char *); +IKI_DLLESPEC extern void execute_5504(char*, char *); +IKI_DLLESPEC extern void execute_5505(char*, char *); +IKI_DLLESPEC extern void execute_5506(char*, char *); +IKI_DLLESPEC extern void execute_5507(char*, char *); +IKI_DLLESPEC extern void execute_5508(char*, char *); +IKI_DLLESPEC extern void execute_5509(char*, char *); +IKI_DLLESPEC extern void execute_5510(char*, char *); +IKI_DLLESPEC extern void execute_5511(char*, char *); +IKI_DLLESPEC extern void execute_5512(char*, char *); +IKI_DLLESPEC extern void execute_5513(char*, char *); +IKI_DLLESPEC extern void execute_5514(char*, char *); +IKI_DLLESPEC extern void execute_5515(char*, char *); +IKI_DLLESPEC extern void execute_5516(char*, char *); +IKI_DLLESPEC extern void execute_5517(char*, char *); +IKI_DLLESPEC extern void execute_5518(char*, char *); +IKI_DLLESPEC extern void execute_5519(char*, char *); +IKI_DLLESPEC extern void execute_5520(char*, char *); +IKI_DLLESPEC extern void execute_5521(char*, char *); +IKI_DLLESPEC extern void execute_5522(char*, char *); +IKI_DLLESPEC extern void execute_5523(char*, char *); +IKI_DLLESPEC extern void execute_5524(char*, char *); +IKI_DLLESPEC extern void execute_5525(char*, char *); +IKI_DLLESPEC extern void execute_5526(char*, char *); +IKI_DLLESPEC extern void execute_5527(char*, char *); +IKI_DLLESPEC extern void execute_5528(char*, char *); +IKI_DLLESPEC extern void execute_5529(char*, char *); +IKI_DLLESPEC extern void execute_5530(char*, char *); +IKI_DLLESPEC extern void execute_5531(char*, char *); +IKI_DLLESPEC extern void execute_5532(char*, char *); +IKI_DLLESPEC extern void execute_5533(char*, char *); +IKI_DLLESPEC extern void execute_5534(char*, char *); +IKI_DLLESPEC extern void execute_5535(char*, char *); +IKI_DLLESPEC extern void execute_5536(char*, char *); +IKI_DLLESPEC extern void execute_5537(char*, char *); +IKI_DLLESPEC extern void execute_5538(char*, char *); +IKI_DLLESPEC extern void execute_5539(char*, char *); +IKI_DLLESPEC extern void execute_5540(char*, char *); +IKI_DLLESPEC extern void execute_5541(char*, char *); +IKI_DLLESPEC extern void execute_5542(char*, char *); +IKI_DLLESPEC extern void execute_5543(char*, char *); +IKI_DLLESPEC extern void execute_5544(char*, char *); +IKI_DLLESPEC extern void execute_5545(char*, char *); +IKI_DLLESPEC extern void execute_5546(char*, char *); +IKI_DLLESPEC extern void execute_5547(char*, char *); +IKI_DLLESPEC extern void execute_5548(char*, char *); +IKI_DLLESPEC extern void execute_5549(char*, char *); +IKI_DLLESPEC extern void execute_5550(char*, char *); +IKI_DLLESPEC extern void execute_5551(char*, char *); +IKI_DLLESPEC extern void execute_5552(char*, char *); +IKI_DLLESPEC extern void execute_5553(char*, char *); +IKI_DLLESPEC extern void execute_5554(char*, char *); +IKI_DLLESPEC extern void execute_5555(char*, char *); +IKI_DLLESPEC extern void execute_5556(char*, char *); +IKI_DLLESPEC extern void execute_5557(char*, char *); +IKI_DLLESPEC extern void execute_5558(char*, char *); +IKI_DLLESPEC extern void execute_5559(char*, char *); +IKI_DLLESPEC extern void execute_5560(char*, char *); +IKI_DLLESPEC extern void execute_5561(char*, char *); +IKI_DLLESPEC extern void execute_5562(char*, char *); +IKI_DLLESPEC extern void execute_5563(char*, char *); +IKI_DLLESPEC extern void execute_5564(char*, char *); +IKI_DLLESPEC extern void execute_5565(char*, char *); +IKI_DLLESPEC extern void execute_5566(char*, char *); +IKI_DLLESPEC extern void execute_5567(char*, char *); +IKI_DLLESPEC extern void execute_5568(char*, char *); +IKI_DLLESPEC extern void execute_5569(char*, char *); +IKI_DLLESPEC extern void execute_5570(char*, char *); +IKI_DLLESPEC extern void execute_5571(char*, char *); +IKI_DLLESPEC extern void execute_5572(char*, char *); +IKI_DLLESPEC extern void execute_5573(char*, char *); +IKI_DLLESPEC extern void execute_5574(char*, char *); +IKI_DLLESPEC extern void execute_5575(char*, char *); +IKI_DLLESPEC extern void execute_5576(char*, char *); +IKI_DLLESPEC extern void execute_5577(char*, char *); +IKI_DLLESPEC extern void execute_5578(char*, char *); +IKI_DLLESPEC extern void execute_5579(char*, char *); +IKI_DLLESPEC extern void execute_5580(char*, char *); +IKI_DLLESPEC extern void execute_5581(char*, char *); +IKI_DLLESPEC extern void execute_5582(char*, char *); +IKI_DLLESPEC extern void execute_5583(char*, char *); +IKI_DLLESPEC extern void execute_5584(char*, char *); +IKI_DLLESPEC extern void execute_5585(char*, char *); +IKI_DLLESPEC extern void execute_5586(char*, char *); +IKI_DLLESPEC extern void execute_5587(char*, char *); +IKI_DLLESPEC extern void execute_5588(char*, char *); +IKI_DLLESPEC extern void execute_5589(char*, char *); +IKI_DLLESPEC extern void execute_5590(char*, char *); +IKI_DLLESPEC extern void execute_5591(char*, char *); +IKI_DLLESPEC extern void execute_5592(char*, char *); +IKI_DLLESPEC extern void execute_5593(char*, char *); +IKI_DLLESPEC extern void execute_5594(char*, char *); +IKI_DLLESPEC extern void execute_5595(char*, char *); +IKI_DLLESPEC extern void execute_5596(char*, char *); +IKI_DLLESPEC extern void execute_5597(char*, char *); +IKI_DLLESPEC extern void execute_5598(char*, char *); +IKI_DLLESPEC extern void execute_5599(char*, char *); +IKI_DLLESPEC extern void execute_5600(char*, char *); +IKI_DLLESPEC extern void execute_5601(char*, char *); +IKI_DLLESPEC extern void execute_5602(char*, char *); +IKI_DLLESPEC extern void execute_5603(char*, char *); +IKI_DLLESPEC extern void execute_5604(char*, char *); +IKI_DLLESPEC extern void execute_5605(char*, char *); +IKI_DLLESPEC extern void execute_5606(char*, char *); +IKI_DLLESPEC extern void execute_5607(char*, char *); +IKI_DLLESPEC extern void execute_5608(char*, char *); +IKI_DLLESPEC extern void execute_5609(char*, char *); +IKI_DLLESPEC extern void execute_5610(char*, char *); +IKI_DLLESPEC extern void execute_5611(char*, char *); +IKI_DLLESPEC extern void execute_5612(char*, char *); +IKI_DLLESPEC extern void execute_5613(char*, char *); +IKI_DLLESPEC extern void execute_5614(char*, char *); +IKI_DLLESPEC extern void execute_5615(char*, char *); +IKI_DLLESPEC extern void execute_5616(char*, char *); +IKI_DLLESPEC extern void execute_5617(char*, char *); +IKI_DLLESPEC extern void execute_5618(char*, char *); +IKI_DLLESPEC extern void execute_5619(char*, char *); +IKI_DLLESPEC extern void execute_5620(char*, char *); +IKI_DLLESPEC extern void execute_5621(char*, char *); +IKI_DLLESPEC extern void execute_5622(char*, char *); +IKI_DLLESPEC extern void execute_5623(char*, char *); +IKI_DLLESPEC extern void execute_5624(char*, char *); +IKI_DLLESPEC extern void execute_5625(char*, char *); +IKI_DLLESPEC extern void execute_5626(char*, char *); +IKI_DLLESPEC extern void execute_5627(char*, char *); +IKI_DLLESPEC extern void execute_5628(char*, char *); +IKI_DLLESPEC extern void execute_5629(char*, char *); +IKI_DLLESPEC extern void execute_5630(char*, char *); +IKI_DLLESPEC extern void execute_5631(char*, char *); +IKI_DLLESPEC extern void execute_5632(char*, char *); +IKI_DLLESPEC extern void execute_5633(char*, char *); +IKI_DLLESPEC extern void execute_5634(char*, char *); +IKI_DLLESPEC extern void execute_5635(char*, char *); +IKI_DLLESPEC extern void execute_5636(char*, char *); +IKI_DLLESPEC extern void execute_5637(char*, char *); +IKI_DLLESPEC extern void execute_5638(char*, char *); +IKI_DLLESPEC extern void execute_5639(char*, char *); +IKI_DLLESPEC extern void execute_5640(char*, char *); +IKI_DLLESPEC extern void execute_5641(char*, char *); +IKI_DLLESPEC extern void execute_5642(char*, char *); +IKI_DLLESPEC extern void execute_5643(char*, char *); +IKI_DLLESPEC extern void execute_5644(char*, char *); +IKI_DLLESPEC extern void execute_5645(char*, char *); +IKI_DLLESPEC extern void execute_5646(char*, char *); +IKI_DLLESPEC extern void execute_5647(char*, char *); +IKI_DLLESPEC extern void execute_5648(char*, char *); +IKI_DLLESPEC extern void execute_5649(char*, char *); +IKI_DLLESPEC extern void execute_5650(char*, char *); +IKI_DLLESPEC extern void execute_5651(char*, char *); +IKI_DLLESPEC extern void execute_5652(char*, char *); +IKI_DLLESPEC extern void execute_5653(char*, char *); +IKI_DLLESPEC extern void execute_5654(char*, char *); +IKI_DLLESPEC extern void execute_5655(char*, char *); +IKI_DLLESPEC extern void execute_5656(char*, char *); +IKI_DLLESPEC extern void execute_5657(char*, char *); +IKI_DLLESPEC extern void execute_5658(char*, char *); +IKI_DLLESPEC extern void execute_5659(char*, char *); +IKI_DLLESPEC extern void execute_5660(char*, char *); +IKI_DLLESPEC extern void execute_5661(char*, char *); +IKI_DLLESPEC extern void execute_5662(char*, char *); +IKI_DLLESPEC extern void execute_5663(char*, char *); +IKI_DLLESPEC extern void execute_5664(char*, char *); +IKI_DLLESPEC extern void execute_5665(char*, char *); +IKI_DLLESPEC extern void execute_5666(char*, char *); +IKI_DLLESPEC extern void execute_5667(char*, char *); +IKI_DLLESPEC extern void execute_5668(char*, char *); +IKI_DLLESPEC extern void execute_5669(char*, char *); +IKI_DLLESPEC extern void execute_5670(char*, char *); +IKI_DLLESPEC extern void execute_5671(char*, char *); +IKI_DLLESPEC extern void execute_5672(char*, char *); +IKI_DLLESPEC extern void execute_5673(char*, char *); +IKI_DLLESPEC extern void execute_5674(char*, char *); +IKI_DLLESPEC extern void execute_5675(char*, char *); +IKI_DLLESPEC extern void execute_5676(char*, char *); +IKI_DLLESPEC extern void execute_5677(char*, char *); +IKI_DLLESPEC extern void execute_5678(char*, char *); +IKI_DLLESPEC extern void execute_5679(char*, char *); +IKI_DLLESPEC extern void execute_5680(char*, char *); +IKI_DLLESPEC extern void execute_5681(char*, char *); +IKI_DLLESPEC extern void execute_5682(char*, char *); +IKI_DLLESPEC extern void execute_5683(char*, char *); +IKI_DLLESPEC extern void execute_5684(char*, char *); +IKI_DLLESPEC extern void execute_5685(char*, char *); +IKI_DLLESPEC extern void execute_5686(char*, char *); +IKI_DLLESPEC extern void execute_5687(char*, char *); +IKI_DLLESPEC extern void execute_5688(char*, char *); +IKI_DLLESPEC extern void execute_5689(char*, char *); +IKI_DLLESPEC extern void execute_5690(char*, char *); +IKI_DLLESPEC extern void execute_5691(char*, char *); +IKI_DLLESPEC extern void execute_5692(char*, char *); +IKI_DLLESPEC extern void execute_5693(char*, char *); +IKI_DLLESPEC extern void execute_5694(char*, char *); +IKI_DLLESPEC extern void execute_5695(char*, char *); +IKI_DLLESPEC extern void execute_5696(char*, char *); +IKI_DLLESPEC extern void execute_5697(char*, char *); +IKI_DLLESPEC extern void execute_5698(char*, char *); +IKI_DLLESPEC extern void execute_5699(char*, char *); +IKI_DLLESPEC extern void execute_5700(char*, char *); +IKI_DLLESPEC extern void execute_5701(char*, char *); +IKI_DLLESPEC extern void execute_5702(char*, char *); +IKI_DLLESPEC extern void execute_5703(char*, char *); +IKI_DLLESPEC extern void execute_5704(char*, char *); +IKI_DLLESPEC extern void execute_5705(char*, char *); +IKI_DLLESPEC extern void execute_5706(char*, char *); +IKI_DLLESPEC extern void execute_5707(char*, char *); +IKI_DLLESPEC extern void execute_5708(char*, char *); +IKI_DLLESPEC extern void execute_5709(char*, char *); +IKI_DLLESPEC extern void execute_5710(char*, char *); +IKI_DLLESPEC extern void execute_5711(char*, char *); +IKI_DLLESPEC extern void execute_5712(char*, char *); +IKI_DLLESPEC extern void execute_5713(char*, char *); +IKI_DLLESPEC extern void execute_5714(char*, char *); +IKI_DLLESPEC extern void execute_5715(char*, char *); +IKI_DLLESPEC extern void execute_5716(char*, char *); +IKI_DLLESPEC extern void execute_5717(char*, char *); +IKI_DLLESPEC extern void execute_5718(char*, char *); +IKI_DLLESPEC extern void execute_5719(char*, char *); +IKI_DLLESPEC extern void execute_5720(char*, char *); +IKI_DLLESPEC extern void execute_5721(char*, char *); +IKI_DLLESPEC extern void execute_5722(char*, char *); +IKI_DLLESPEC extern void execute_5723(char*, char *); +IKI_DLLESPEC extern void execute_5724(char*, char *); +IKI_DLLESPEC extern void execute_5725(char*, char *); +IKI_DLLESPEC extern void execute_5726(char*, char *); +IKI_DLLESPEC extern void execute_5727(char*, char *); +IKI_DLLESPEC extern void execute_5728(char*, char *); +IKI_DLLESPEC extern void execute_5729(char*, char *); +IKI_DLLESPEC extern void execute_5730(char*, char *); +IKI_DLLESPEC extern void execute_5731(char*, char *); +IKI_DLLESPEC extern void execute_5732(char*, char *); +IKI_DLLESPEC extern void execute_5733(char*, char *); +IKI_DLLESPEC extern void execute_5734(char*, char *); +IKI_DLLESPEC extern void execute_5735(char*, char *); +IKI_DLLESPEC extern void execute_5736(char*, char *); +IKI_DLLESPEC extern void execute_5737(char*, char *); +IKI_DLLESPEC extern void execute_5738(char*, char *); +IKI_DLLESPEC extern void execute_5739(char*, char *); +IKI_DLLESPEC extern void execute_5740(char*, char *); +IKI_DLLESPEC extern void execute_5741(char*, char *); +IKI_DLLESPEC extern void execute_5742(char*, char *); +IKI_DLLESPEC extern void execute_5743(char*, char *); +IKI_DLLESPEC extern void execute_5744(char*, char *); +IKI_DLLESPEC extern void execute_5745(char*, char *); +IKI_DLLESPEC extern void execute_5746(char*, char *); +IKI_DLLESPEC extern void execute_5747(char*, char *); +IKI_DLLESPEC extern void execute_5748(char*, char *); +IKI_DLLESPEC extern void execute_5749(char*, char *); +IKI_DLLESPEC extern void execute_5750(char*, char *); +IKI_DLLESPEC extern void execute_5751(char*, char *); +IKI_DLLESPEC extern void execute_5752(char*, char *); +IKI_DLLESPEC extern void execute_5753(char*, char *); +IKI_DLLESPEC extern void execute_5754(char*, char *); +IKI_DLLESPEC extern void execute_5755(char*, char *); +IKI_DLLESPEC extern void execute_5756(char*, char *); +IKI_DLLESPEC extern void execute_5757(char*, char *); +IKI_DLLESPEC extern void execute_5758(char*, char *); +IKI_DLLESPEC extern void execute_5759(char*, char *); +IKI_DLLESPEC extern void execute_5760(char*, char *); +IKI_DLLESPEC extern void execute_5761(char*, char *); +IKI_DLLESPEC extern void execute_5762(char*, char *); +IKI_DLLESPEC extern void execute_5763(char*, char *); +IKI_DLLESPEC extern void execute_5764(char*, char *); +IKI_DLLESPEC extern void execute_5765(char*, char *); +IKI_DLLESPEC extern void execute_5766(char*, char *); +IKI_DLLESPEC extern void execute_5767(char*, char *); +IKI_DLLESPEC extern void execute_5768(char*, char *); +IKI_DLLESPEC extern void execute_5769(char*, char *); +IKI_DLLESPEC extern void execute_5770(char*, char *); +IKI_DLLESPEC extern void execute_5771(char*, char *); +IKI_DLLESPEC extern void execute_5772(char*, char *); +IKI_DLLESPEC extern void execute_5773(char*, char *); +IKI_DLLESPEC extern void execute_5774(char*, char *); +IKI_DLLESPEC extern void execute_5775(char*, char *); +IKI_DLLESPEC extern void execute_5776(char*, char *); +IKI_DLLESPEC extern void execute_5777(char*, char *); +IKI_DLLESPEC extern void execute_5778(char*, char *); +IKI_DLLESPEC extern void execute_5779(char*, char *); +IKI_DLLESPEC extern void execute_5780(char*, char *); +IKI_DLLESPEC extern void execute_5781(char*, char *); +IKI_DLLESPEC extern void execute_5782(char*, char *); +IKI_DLLESPEC extern void execute_5783(char*, char *); +IKI_DLLESPEC extern void execute_5784(char*, char *); +IKI_DLLESPEC extern void execute_5785(char*, char *); +IKI_DLLESPEC extern void execute_5786(char*, char *); +IKI_DLLESPEC extern void execute_5787(char*, char *); +IKI_DLLESPEC extern void execute_5788(char*, char *); +IKI_DLLESPEC extern void execute_5789(char*, char *); +IKI_DLLESPEC extern void execute_5790(char*, char *); +IKI_DLLESPEC extern void execute_5791(char*, char *); +IKI_DLLESPEC extern void execute_5792(char*, char *); +IKI_DLLESPEC extern void execute_5793(char*, char *); +IKI_DLLESPEC extern void execute_5794(char*, char *); +IKI_DLLESPEC extern void execute_5795(char*, char *); +IKI_DLLESPEC extern void execute_5796(char*, char *); +IKI_DLLESPEC extern void execute_5797(char*, char *); +IKI_DLLESPEC extern void execute_5798(char*, char *); +IKI_DLLESPEC extern void execute_5799(char*, char *); +IKI_DLLESPEC extern void execute_5800(char*, char *); +IKI_DLLESPEC extern void execute_5801(char*, char *); +IKI_DLLESPEC extern void execute_5802(char*, char *); +IKI_DLLESPEC extern void execute_5803(char*, char *); +IKI_DLLESPEC extern void execute_5804(char*, char *); +IKI_DLLESPEC extern void execute_5805(char*, char *); +IKI_DLLESPEC extern void execute_5806(char*, char *); +IKI_DLLESPEC extern void execute_5807(char*, char *); +IKI_DLLESPEC extern void execute_5808(char*, char *); +IKI_DLLESPEC extern void execute_5809(char*, char *); +IKI_DLLESPEC extern void execute_5810(char*, char *); +IKI_DLLESPEC extern void execute_5811(char*, char *); +IKI_DLLESPEC extern void execute_5812(char*, char *); +IKI_DLLESPEC extern void execute_5813(char*, char *); +IKI_DLLESPEC extern void execute_5814(char*, char *); +IKI_DLLESPEC extern void execute_5815(char*, char *); +IKI_DLLESPEC extern void execute_5816(char*, char *); +IKI_DLLESPEC extern void execute_5817(char*, char *); +IKI_DLLESPEC extern void execute_5818(char*, char *); +IKI_DLLESPEC extern void execute_5819(char*, char *); +IKI_DLLESPEC extern void execute_5820(char*, char *); +IKI_DLLESPEC extern void execute_5821(char*, char *); +IKI_DLLESPEC extern void execute_5822(char*, char *); +IKI_DLLESPEC extern void execute_5823(char*, char *); +IKI_DLLESPEC extern void execute_5824(char*, char *); +IKI_DLLESPEC extern void execute_5825(char*, char *); +IKI_DLLESPEC extern void execute_5826(char*, char *); +IKI_DLLESPEC extern void execute_5827(char*, char *); +IKI_DLLESPEC extern void execute_5828(char*, char *); +IKI_DLLESPEC extern void execute_5829(char*, char *); +IKI_DLLESPEC extern void execute_5830(char*, char *); +IKI_DLLESPEC extern void execute_5831(char*, char *); +IKI_DLLESPEC extern void execute_5832(char*, char *); +IKI_DLLESPEC extern void execute_5833(char*, char *); +IKI_DLLESPEC extern void execute_5834(char*, char *); +IKI_DLLESPEC extern void execute_5835(char*, char *); +IKI_DLLESPEC extern void execute_5836(char*, char *); +IKI_DLLESPEC extern void execute_5837(char*, char *); +IKI_DLLESPEC extern void execute_5838(char*, char *); +IKI_DLLESPEC extern void execute_5839(char*, char *); +IKI_DLLESPEC extern void execute_5840(char*, char *); +IKI_DLLESPEC extern void execute_5841(char*, char *); +IKI_DLLESPEC extern void execute_5842(char*, char *); +IKI_DLLESPEC extern void execute_5843(char*, char *); +IKI_DLLESPEC extern void execute_5844(char*, char *); +IKI_DLLESPEC extern void execute_5845(char*, char *); +IKI_DLLESPEC extern void execute_5846(char*, char *); +IKI_DLLESPEC extern void execute_5847(char*, char *); +IKI_DLLESPEC extern void execute_5848(char*, char *); +IKI_DLLESPEC extern void execute_5849(char*, char *); +IKI_DLLESPEC extern void execute_5850(char*, char *); +IKI_DLLESPEC extern void execute_5851(char*, char *); +IKI_DLLESPEC extern void execute_5852(char*, char *); +IKI_DLLESPEC extern void execute_5853(char*, char *); +IKI_DLLESPEC extern void execute_5854(char*, char *); +IKI_DLLESPEC extern void execute_5855(char*, char *); +IKI_DLLESPEC extern void execute_5856(char*, char *); +IKI_DLLESPEC extern void execute_5857(char*, char *); +IKI_DLLESPEC extern void execute_5858(char*, char *); +IKI_DLLESPEC extern void execute_5859(char*, char *); +IKI_DLLESPEC extern void execute_5860(char*, char *); +IKI_DLLESPEC extern void execute_5861(char*, char *); +IKI_DLLESPEC extern void execute_5862(char*, char *); +IKI_DLLESPEC extern void execute_5863(char*, char *); +IKI_DLLESPEC extern void execute_5864(char*, char *); +IKI_DLLESPEC extern void execute_5865(char*, char *); +IKI_DLLESPEC extern void execute_5866(char*, char *); +IKI_DLLESPEC extern void execute_5867(char*, char *); +IKI_DLLESPEC extern void execute_5868(char*, char *); +IKI_DLLESPEC extern void execute_5869(char*, char *); +IKI_DLLESPEC extern void execute_5870(char*, char *); +IKI_DLLESPEC extern void execute_5871(char*, char *); +IKI_DLLESPEC extern void execute_5872(char*, char *); +IKI_DLLESPEC extern void execute_5873(char*, char *); +IKI_DLLESPEC extern void execute_5874(char*, char *); +IKI_DLLESPEC extern void execute_5875(char*, char *); +IKI_DLLESPEC extern void execute_5876(char*, char *); +IKI_DLLESPEC extern void execute_5877(char*, char *); +IKI_DLLESPEC extern void execute_5878(char*, char *); +IKI_DLLESPEC extern void execute_5879(char*, char *); +IKI_DLLESPEC extern void execute_5880(char*, char *); +IKI_DLLESPEC extern void execute_5881(char*, char *); +IKI_DLLESPEC extern void execute_5882(char*, char *); +IKI_DLLESPEC extern void execute_5883(char*, char *); +IKI_DLLESPEC extern void execute_5884(char*, char *); +IKI_DLLESPEC extern void execute_5885(char*, char *); +IKI_DLLESPEC extern void execute_5886(char*, char *); +IKI_DLLESPEC extern void execute_5887(char*, char *); +IKI_DLLESPEC extern void execute_5888(char*, char *); +IKI_DLLESPEC extern void execute_5889(char*, char *); +IKI_DLLESPEC extern void execute_5890(char*, char *); +IKI_DLLESPEC extern void execute_5891(char*, char *); +IKI_DLLESPEC extern void execute_5892(char*, char *); +IKI_DLLESPEC extern void execute_5893(char*, char *); +IKI_DLLESPEC extern void execute_5894(char*, char *); +IKI_DLLESPEC extern void execute_5895(char*, char *); +IKI_DLLESPEC extern void execute_5896(char*, char *); +IKI_DLLESPEC extern void execute_5897(char*, char *); +IKI_DLLESPEC extern void execute_5898(char*, char *); +IKI_DLLESPEC extern void execute_5899(char*, char *); +IKI_DLLESPEC extern void execute_5900(char*, char *); +IKI_DLLESPEC extern void execute_5901(char*, char *); +IKI_DLLESPEC extern void execute_5902(char*, char *); +IKI_DLLESPEC extern void execute_5903(char*, char *); +IKI_DLLESPEC extern void execute_5904(char*, char *); +IKI_DLLESPEC extern void execute_5905(char*, char *); +IKI_DLLESPEC extern void execute_5906(char*, char *); +IKI_DLLESPEC extern void execute_5907(char*, char *); +IKI_DLLESPEC extern void execute_5908(char*, char *); +IKI_DLLESPEC extern void execute_5909(char*, char *); +IKI_DLLESPEC extern void execute_5910(char*, char *); +IKI_DLLESPEC extern void execute_5911(char*, char *); +IKI_DLLESPEC extern void execute_5912(char*, char *); +IKI_DLLESPEC extern void execute_5913(char*, char *); +IKI_DLLESPEC extern void execute_5914(char*, char *); +IKI_DLLESPEC extern void execute_5915(char*, char *); +IKI_DLLESPEC extern void execute_5916(char*, char *); +IKI_DLLESPEC extern void execute_5917(char*, char *); +IKI_DLLESPEC extern void execute_5918(char*, char *); +IKI_DLLESPEC extern void execute_5919(char*, char *); +IKI_DLLESPEC extern void execute_5920(char*, char *); +IKI_DLLESPEC extern void execute_5921(char*, char *); +IKI_DLLESPEC extern void execute_5922(char*, char *); +IKI_DLLESPEC extern void execute_5923(char*, char *); +IKI_DLLESPEC extern void execute_5924(char*, char *); +IKI_DLLESPEC extern void execute_5925(char*, char *); +IKI_DLLESPEC extern void execute_5926(char*, char *); +IKI_DLLESPEC extern void execute_5927(char*, char *); +IKI_DLLESPEC extern void execute_5928(char*, char *); +IKI_DLLESPEC extern void execute_5929(char*, char *); +IKI_DLLESPEC extern void execute_5930(char*, char *); +IKI_DLLESPEC extern void execute_5931(char*, char *); +IKI_DLLESPEC extern void execute_5932(char*, char *); +IKI_DLLESPEC extern void execute_5933(char*, char *); +IKI_DLLESPEC extern void execute_5934(char*, char *); +IKI_DLLESPEC extern void execute_5935(char*, char *); +IKI_DLLESPEC extern void execute_5936(char*, char *); +IKI_DLLESPEC extern void execute_5937(char*, char *); +IKI_DLLESPEC extern void execute_5938(char*, char *); +IKI_DLLESPEC extern void execute_5939(char*, char *); +IKI_DLLESPEC extern void execute_5940(char*, char *); +IKI_DLLESPEC extern void execute_5941(char*, char *); +IKI_DLLESPEC extern void execute_5942(char*, char *); +IKI_DLLESPEC extern void execute_5943(char*, char *); +IKI_DLLESPEC extern void execute_5944(char*, char *); +IKI_DLLESPEC extern void execute_5945(char*, char *); +IKI_DLLESPEC extern void execute_5946(char*, char *); +IKI_DLLESPEC extern void execute_5947(char*, char *); +IKI_DLLESPEC extern void execute_5948(char*, char *); +IKI_DLLESPEC extern void execute_5949(char*, char *); +IKI_DLLESPEC extern void execute_5950(char*, char *); +IKI_DLLESPEC extern void execute_5951(char*, char *); +IKI_DLLESPEC extern void execute_5952(char*, char *); +IKI_DLLESPEC extern void execute_5953(char*, char *); +IKI_DLLESPEC extern void execute_5954(char*, char *); +IKI_DLLESPEC extern void execute_5955(char*, char *); +IKI_DLLESPEC extern void execute_5956(char*, char *); +IKI_DLLESPEC extern void execute_5957(char*, char *); +IKI_DLLESPEC extern void execute_5958(char*, char *); +IKI_DLLESPEC extern void execute_5959(char*, char *); +IKI_DLLESPEC extern void execute_5960(char*, char *); +IKI_DLLESPEC extern void execute_5961(char*, char *); +IKI_DLLESPEC extern void execute_5962(char*, char *); +IKI_DLLESPEC extern void execute_5963(char*, char *); +IKI_DLLESPEC extern void execute_5964(char*, char *); +IKI_DLLESPEC extern void execute_5965(char*, char *); +IKI_DLLESPEC extern void execute_5966(char*, char *); +IKI_DLLESPEC extern void execute_5967(char*, char *); +IKI_DLLESPEC extern void execute_5968(char*, char *); +IKI_DLLESPEC extern void execute_5969(char*, char *); +IKI_DLLESPEC extern void execute_5970(char*, char *); +IKI_DLLESPEC extern void execute_5971(char*, char *); +IKI_DLLESPEC extern void execute_5972(char*, char *); +IKI_DLLESPEC extern void execute_5973(char*, char *); +IKI_DLLESPEC extern void execute_5974(char*, char *); +IKI_DLLESPEC extern void execute_5975(char*, char *); +IKI_DLLESPEC extern void execute_5976(char*, char *); +IKI_DLLESPEC extern void execute_5977(char*, char *); +IKI_DLLESPEC extern void execute_5978(char*, char *); +IKI_DLLESPEC extern void execute_5979(char*, char *); +IKI_DLLESPEC extern void execute_5980(char*, char *); +IKI_DLLESPEC extern void execute_5981(char*, char *); +IKI_DLLESPEC extern void execute_5982(char*, char *); +IKI_DLLESPEC extern void execute_5983(char*, char *); +IKI_DLLESPEC extern void execute_5984(char*, char *); +IKI_DLLESPEC extern void execute_5985(char*, char *); +IKI_DLLESPEC extern void execute_5986(char*, char *); +IKI_DLLESPEC extern void execute_5987(char*, char *); +IKI_DLLESPEC extern void execute_5988(char*, char *); +IKI_DLLESPEC extern void execute_5989(char*, char *); +IKI_DLLESPEC extern void execute_5990(char*, char *); +IKI_DLLESPEC extern void execute_5991(char*, char *); +IKI_DLLESPEC extern void execute_5992(char*, char *); +IKI_DLLESPEC extern void execute_5993(char*, char *); +IKI_DLLESPEC extern void execute_5994(char*, char *); +IKI_DLLESPEC extern void execute_5995(char*, char *); +IKI_DLLESPEC extern void execute_5996(char*, char *); +IKI_DLLESPEC extern void execute_5997(char*, char *); +IKI_DLLESPEC extern void execute_5998(char*, char *); +IKI_DLLESPEC extern void execute_5999(char*, char *); +IKI_DLLESPEC extern void execute_6000(char*, char *); +IKI_DLLESPEC extern void execute_6001(char*, char *); +IKI_DLLESPEC extern void execute_6002(char*, char *); +IKI_DLLESPEC extern void execute_6003(char*, char *); +IKI_DLLESPEC extern void execute_6004(char*, char *); +IKI_DLLESPEC extern void execute_6005(char*, char *); +IKI_DLLESPEC extern void execute_6006(char*, char *); +IKI_DLLESPEC extern void execute_6007(char*, char *); +IKI_DLLESPEC extern void execute_6008(char*, char *); +IKI_DLLESPEC extern void execute_6009(char*, char *); +IKI_DLLESPEC extern void execute_6010(char*, char *); +IKI_DLLESPEC extern void execute_6011(char*, char *); +IKI_DLLESPEC extern void execute_6012(char*, char *); +IKI_DLLESPEC extern void execute_6013(char*, char *); +IKI_DLLESPEC extern void execute_6014(char*, char *); +IKI_DLLESPEC extern void execute_6015(char*, char *); +IKI_DLLESPEC extern void execute_6016(char*, char *); +IKI_DLLESPEC extern void execute_6017(char*, char *); +IKI_DLLESPEC extern void execute_6018(char*, char *); +IKI_DLLESPEC extern void execute_6019(char*, char *); +IKI_DLLESPEC extern void execute_6020(char*, char *); +IKI_DLLESPEC extern void execute_6021(char*, char *); +IKI_DLLESPEC extern void execute_6022(char*, char *); +IKI_DLLESPEC extern void execute_6023(char*, char *); +IKI_DLLESPEC extern void execute_6024(char*, char *); +IKI_DLLESPEC extern void execute_6025(char*, char *); +IKI_DLLESPEC extern void execute_6026(char*, char *); +IKI_DLLESPEC extern void execute_6027(char*, char *); +IKI_DLLESPEC extern void execute_6028(char*, char *); +IKI_DLLESPEC extern void execute_6029(char*, char *); +IKI_DLLESPEC extern void execute_6030(char*, char *); +IKI_DLLESPEC extern void execute_6031(char*, char *); +IKI_DLLESPEC extern void execute_6032(char*, char *); +IKI_DLLESPEC extern void execute_6033(char*, char *); +IKI_DLLESPEC extern void execute_6034(char*, char *); +IKI_DLLESPEC extern void execute_6035(char*, char *); +IKI_DLLESPEC extern void execute_6036(char*, char *); +IKI_DLLESPEC extern void execute_6037(char*, char *); +IKI_DLLESPEC extern void execute_6038(char*, char *); +IKI_DLLESPEC extern void execute_6039(char*, char *); +IKI_DLLESPEC extern void execute_6040(char*, char *); +IKI_DLLESPEC extern void execute_6041(char*, char *); +IKI_DLLESPEC extern void execute_6042(char*, char *); +IKI_DLLESPEC extern void execute_6043(char*, char *); +IKI_DLLESPEC extern void execute_6044(char*, char *); +IKI_DLLESPEC extern void execute_6045(char*, char *); +IKI_DLLESPEC extern void execute_6046(char*, char *); +IKI_DLLESPEC extern void execute_6047(char*, char *); +IKI_DLLESPEC extern void execute_6048(char*, char *); +IKI_DLLESPEC extern void execute_6049(char*, char *); +IKI_DLLESPEC extern void execute_6050(char*, char *); +IKI_DLLESPEC extern void execute_6051(char*, char *); +IKI_DLLESPEC extern void execute_6052(char*, char *); +IKI_DLLESPEC extern void execute_6053(char*, char *); +IKI_DLLESPEC extern void execute_6054(char*, char *); +IKI_DLLESPEC extern void execute_6055(char*, char *); +IKI_DLLESPEC extern void execute_6056(char*, char *); +IKI_DLLESPEC extern void execute_6057(char*, char *); +IKI_DLLESPEC extern void execute_6058(char*, char *); +IKI_DLLESPEC extern void execute_30(char*, char *); +IKI_DLLESPEC extern void execute_1236(char*, char *); +IKI_DLLESPEC extern void execute_1237(char*, char *); +IKI_DLLESPEC extern void execute_1238(char*, char *); +IKI_DLLESPEC extern void execute_1239(char*, char *); +IKI_DLLESPEC extern void execute_1235(char*, char *); +IKI_DLLESPEC extern void execute_40(char*, char *); +IKI_DLLESPEC extern void execute_41(char*, char *); +IKI_DLLESPEC extern void execute_1250(char*, char *); +IKI_DLLESPEC extern void execute_44(char*, char *); +IKI_DLLESPEC extern void execute_45(char*, char *); +IKI_DLLESPEC extern void execute_1251(char*, char *); +IKI_DLLESPEC extern void execute_48(char*, char *); +IKI_DLLESPEC extern void execute_1253(char*, char *); +IKI_DLLESPEC extern void execute_1254(char*, char *); +IKI_DLLESPEC extern void execute_1252(char*, char *); +IKI_DLLESPEC extern void execute_51(char*, char *); +IKI_DLLESPEC extern void execute_1256(char*, char *); +IKI_DLLESPEC extern void execute_1257(char*, char *); +IKI_DLLESPEC extern void execute_1258(char*, char *); +IKI_DLLESPEC extern void execute_1259(char*, char *); +IKI_DLLESPEC extern void execute_1260(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void execute_1255(char*, char *); +IKI_DLLESPEC extern void execute_57(char*, char *); +IKI_DLLESPEC extern void execute_58(char*, char *); +IKI_DLLESPEC extern void execute_1273(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_203(char*, char *); +IKI_DLLESPEC extern void execute_204(char*, char *); +IKI_DLLESPEC extern void execute_205(char*, char *); +IKI_DLLESPEC extern void execute_1390(char*, char *); +IKI_DLLESPEC extern void execute_1391(char*, char *); +IKI_DLLESPEC extern void execute_1392(char*, char *); +IKI_DLLESPEC extern void execute_1393(char*, char *); +IKI_DLLESPEC extern void execute_1394(char*, char *); +IKI_DLLESPEC extern void execute_1395(char*, char *); +IKI_DLLESPEC extern void execute_1396(char*, char *); +IKI_DLLESPEC extern void execute_1397(char*, char *); +IKI_DLLESPEC extern void execute_1398(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_1400(char*, char *); +IKI_DLLESPEC extern void execute_1401(char*, char *); +IKI_DLLESPEC extern void execute_1402(char*, char *); +IKI_DLLESPEC extern void execute_1403(char*, char *); +IKI_DLLESPEC extern void execute_1404(char*, char *); +IKI_DLLESPEC extern void execute_1405(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1(char*, char *); +IKI_DLLESPEC extern void vlog_timingcheck_execute_0(char*, char*, char*); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_2(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1315(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1316(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1317(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1318(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1319(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1320(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1321(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1322(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1323(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1324(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1325(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1326(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1327(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1328(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1329(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1330(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1331(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1332(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1333(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1334(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1335(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1336(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1337(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1338(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_27(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_28(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_29(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_30(char*, char *); +IKI_DLLESPEC extern void execute_1424(char*, char *); +IKI_DLLESPEC extern void execute_1430(char*, char *); +IKI_DLLESPEC extern void execute_1431(char*, char *); +IKI_DLLESPEC extern void execute_1432(char*, char *); +IKI_DLLESPEC extern void execute_207(char*, char *); +IKI_DLLESPEC extern void execute_208(char*, char *); +IKI_DLLESPEC extern void execute_209(char*, char *); +IKI_DLLESPEC extern void execute_210(char*, char *); +IKI_DLLESPEC extern void execute_1433(char*, char *); +IKI_DLLESPEC extern void execute_1434(char*, char *); +IKI_DLLESPEC extern void execute_1435(char*, char *); +IKI_DLLESPEC extern void execute_1436(char*, char *); +IKI_DLLESPEC extern void execute_1437(char*, char *); +IKI_DLLESPEC extern void execute_1438(char*, char *); +IKI_DLLESPEC extern void execute_1439(char*, char *); +IKI_DLLESPEC extern void execute_1440(char*, char *); +IKI_DLLESPEC extern void execute_1441(char*, char *); +IKI_DLLESPEC extern void execute_1443(char*, char *); +IKI_DLLESPEC extern void execute_1444(char*, char *); +IKI_DLLESPEC extern void execute_1445(char*, char *); +IKI_DLLESPEC extern void execute_1446(char*, char *); +IKI_DLLESPEC extern void execute_1447(char*, char *); +IKI_DLLESPEC extern void execute_1448(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_31(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_32(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_565(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_566(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_567(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_568(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_569(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_570(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_571(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_572(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_573(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_574(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_575(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_576(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_577(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_578(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_579(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_580(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_581(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_582(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_583(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_584(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_585(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_586(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_587(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_588(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_57(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_58(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_59(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_f806b384d33310e2_af79f1dc_60(char*, char *); +IKI_DLLESPEC extern void execute_1467(char*, char *); +IKI_DLLESPEC extern void execute_1473(char*, char *); +IKI_DLLESPEC extern void execute_1474(char*, char *); +IKI_DLLESPEC extern void execute_1475(char*, char *); +IKI_DLLESPEC extern void execute_1562(char*, char *); +IKI_DLLESPEC extern void execute_1563(char*, char *); +IKI_DLLESPEC extern void execute_1564(char*, char *); +IKI_DLLESPEC extern void execute_1567(char*, char *); +IKI_DLLESPEC extern void execute_1568(char*, char *); +IKI_DLLESPEC extern void execute_1569(char*, char *); +IKI_DLLESPEC extern void execute_1570(char*, char *); +IKI_DLLESPEC extern void execute_377(char*, char *); +IKI_DLLESPEC extern void execute_378(char*, char *); +IKI_DLLESPEC extern void execute_379(char*, char *); +IKI_DLLESPEC extern void execute_380(char*, char *); +IKI_DLLESPEC extern void execute_2461(char*, char *); +IKI_DLLESPEC extern void execute_2462(char*, char *); +IKI_DLLESPEC extern void execute_2463(char*, char *); +IKI_DLLESPEC extern void execute_2464(char*, char *); +IKI_DLLESPEC extern void execute_2465(char*, char *); +IKI_DLLESPEC extern void execute_2466(char*, char *); +IKI_DLLESPEC extern void execute_2467(char*, char *); +IKI_DLLESPEC extern void execute_2468(char*, char *); +IKI_DLLESPEC extern void execute_2470(char*, char *); +IKI_DLLESPEC extern void execute_2471(char*, char *); +IKI_DLLESPEC extern void execute_2472(char*, char *); +IKI_DLLESPEC extern void execute_2473(char*, char *); +IKI_DLLESPEC extern void execute_2474(char*, char *); +IKI_DLLESPEC extern void execute_2475(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_589(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_590(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1699(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1700(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1701(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1702(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1703(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1704(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1705(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1706(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1707(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1708(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1709(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1710(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1711(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1712(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1713(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1714(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1715(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1716(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1717(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1718(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1719(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1720(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1721(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_1722(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_615(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_616(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_617(char*, char *); +IKI_DLLESPEC extern void timing_checker_condition_m_bcc6547dca05b147_67151b0a_618(char*, char *); +IKI_DLLESPEC extern void execute_2494(char*, char *); +IKI_DLLESPEC extern void execute_2499(char*, char *); +IKI_DLLESPEC extern void execute_2500(char*, char *); +IKI_DLLESPEC extern void execute_2501(char*, char *); +IKI_DLLESPEC extern void execute_4039(char*, char *); +IKI_DLLESPEC extern void execute_888(char*, char *); +IKI_DLLESPEC extern void execute_4042(char*, char *); +IKI_DLLESPEC extern void execute_930(char*, char *); +IKI_DLLESPEC extern void execute_4063(char*, char *); +IKI_DLLESPEC extern void execute_4064(char*, char *); +IKI_DLLESPEC extern void execute_4065(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_73(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_74(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_75(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_76(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_84(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_85(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_86(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_87(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_88(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_89(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_90(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_91(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_92(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_93(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_94(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_95(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_96(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_97(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_98(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_99(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_100(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_101(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_103(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_104(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_106(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_107(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_109(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_110(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_111(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_112(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_113(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_114(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_115(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_116(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_126(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_127(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_128(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_129(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_130(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_131(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_132(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_133(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_134(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_135(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_136(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_137(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_138(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_139(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_141(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_142(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_143(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_145(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_147(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_148(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_151(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_153(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_154(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_156(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_157(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_159(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_160(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_162(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_163(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_166(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_169(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_178(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_183(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_186(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_189(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_191(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_192(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_209(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_210(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_211(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_212(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_213(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_214(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_215(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_216(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_217(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_218(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_222(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_223(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_224(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_225(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_226(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_227(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_233(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_234(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_235(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_236(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_237(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_238(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_239(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_240(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_241(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_242(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_243(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_244(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_245(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_246(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_247(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_248(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_249(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_252(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_255(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_256(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_260(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_263(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_270(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_330(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_331(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_332(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_333(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_334(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_335(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_336(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_337(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_338(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_339(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_340(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_341(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_342(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_343(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_344(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_345(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_346(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_347(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_349(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_350(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_351(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_352(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_353(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_354(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_361(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_362(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_363(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_364(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_365(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_366(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_367(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_368(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_369(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_370(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_371(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_372(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_373(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_374(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_375(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_376(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_377(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_378(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_379(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_380(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_381(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_382(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_383(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_384(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_385(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_386(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_387(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_388(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_389(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_390(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_391(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_392(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_393(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_394(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_395(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_396(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_398(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_399(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_408(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_409(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_410(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_411(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_412(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_413(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_414(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_415(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_416(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_417(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_418(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_419(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_420(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_421(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_422(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_423(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_424(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_425(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_426(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_427(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_428(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_429(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_430(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_431(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_432(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_433(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_434(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_435(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_436(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_437(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_438(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_439(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_440(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_441(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_442(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_443(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_444(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_445(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_446(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_447(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_448(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_449(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_450(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_451(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_452(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_453(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_454(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_455(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_456(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_457(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_458(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_459(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_460(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_461(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_462(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_463(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_464(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_465(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_466(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_467(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_468(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_469(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_470(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_471(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_472(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_473(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_474(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_475(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_476(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_477(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_478(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_479(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_480(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_481(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_482(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_483(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_484(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_485(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_486(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_487(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_488(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_489(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_490(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_492(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_493(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_494(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_495(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_496(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_497(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_498(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_499(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_500(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_501(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_502(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_503(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_504(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_505(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_506(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_507(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_508(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_509(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_510(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_511(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_512(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_513(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_514(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_515(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_516(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_517(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_518(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_519(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_520(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_521(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_522(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_523(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_524(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_525(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_526(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_527(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_528(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_529(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_530(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_531(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_532(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_533(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_534(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_535(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_536(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_537(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_538(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_539(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_540(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_541(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_542(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_543(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_544(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_545(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_546(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_547(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_548(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_549(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_550(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_551(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_552(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_553(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_554(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_555(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_556(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_557(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_558(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_559(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_560(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_561(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_562(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_563(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_564(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_565(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_566(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_567(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_568(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_569(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_570(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_571(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_572(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_573(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_574(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_575(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_576(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_577(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_578(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_579(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_580(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_581(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_582(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_583(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_584(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_585(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_586(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_587(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_588(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_589(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_590(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_591(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_592(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_593(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_594(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_595(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_596(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_597(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_598(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_599(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_600(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_601(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_602(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_603(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_604(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_605(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_606(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_607(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_608(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_609(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_610(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_611(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_612(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_613(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_614(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_615(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_616(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_617(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_618(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_619(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_620(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_621(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_622(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_623(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_624(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_625(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_626(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_627(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_628(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_629(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_630(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_631(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_632(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_633(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_634(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_635(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_636(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_637(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_638(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_639(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_640(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_641(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_642(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_643(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_644(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_645(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_646(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_647(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_648(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_649(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_650(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_651(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_652(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_653(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_654(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_655(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_656(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_657(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_658(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_659(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_660(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_661(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_662(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_663(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_664(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_665(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_666(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_667(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_668(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_669(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_670(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_671(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_672(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_673(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_674(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_675(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_676(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_677(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_678(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_679(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_680(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_681(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_682(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_683(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_684(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_685(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_686(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_687(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_688(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_689(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_690(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_691(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_692(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_693(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_694(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_695(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_696(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_697(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_698(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_699(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_700(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_701(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_702(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_703(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_704(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_705(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_706(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_707(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_708(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_709(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_710(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_711(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_712(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_713(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_714(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_715(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_716(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_717(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_718(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_719(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_720(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_721(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_722(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_723(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_724(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_725(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_726(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_727(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_728(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_729(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_730(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_731(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_732(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_733(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_734(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_735(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_736(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_737(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_738(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_739(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_740(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_741(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_742(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_743(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_744(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_745(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_746(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_747(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_748(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_749(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_750(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_751(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_752(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_753(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_754(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_755(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_756(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_757(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_758(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_759(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_760(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_761(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_762(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_763(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_764(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_765(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_766(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_767(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_768(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_769(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_770(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_771(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_772(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_773(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_774(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_775(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_776(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_777(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_778(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_779(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_780(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_781(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_782(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_783(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_784(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_785(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_786(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_787(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_788(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_789(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_790(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_791(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_792(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_793(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_794(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_795(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_796(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_797(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_798(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_799(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_800(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_801(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_802(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_803(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_804(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_805(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_806(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_807(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_808(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_809(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_810(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_811(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_812(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_813(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_814(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_815(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_816(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_817(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_818(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_819(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_820(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_821(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_822(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_823(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_824(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_825(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_826(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_827(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_828(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_829(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_830(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_831(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_832(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_833(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_834(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_835(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_836(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_837(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_838(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_839(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_840(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_841(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_842(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_843(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_844(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_845(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_846(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_847(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_848(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_849(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_850(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_851(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_852(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_853(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_854(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_855(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_856(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_857(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_858(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_859(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_860(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_861(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_862(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_863(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_864(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_865(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_866(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_867(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_868(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_869(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_870(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_871(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_872(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_873(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_874(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_875(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_876(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_877(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_878(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_879(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_880(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_881(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_882(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_883(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_884(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_885(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_886(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_887(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_888(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_889(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_890(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_891(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_892(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_893(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_894(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_895(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_896(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_897(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_898(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_899(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_900(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_901(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_902(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_903(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_904(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_905(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_906(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_907(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_908(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_909(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_910(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_911(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_912(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_913(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_914(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_915(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_916(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_917(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_918(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_919(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_920(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_921(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_922(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_923(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_924(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_925(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_926(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_927(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_928(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_929(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_930(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_931(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_932(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_933(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_934(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_935(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_936(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_937(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_938(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_939(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_940(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_941(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_942(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_943(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_944(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_945(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_946(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_947(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_948(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_949(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_950(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_951(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_952(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_953(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_954(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_955(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_956(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_957(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_958(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_959(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_960(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_961(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_962(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_963(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_964(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_965(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_966(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_967(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_968(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_969(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_970(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_971(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_972(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_973(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_974(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_975(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_976(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_977(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_978(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_979(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_980(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_981(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_982(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_983(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_984(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_985(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_986(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_987(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_988(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_989(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_990(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_991(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_992(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_993(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_994(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_995(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_996(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_997(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_998(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_999(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1000(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1001(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1002(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1003(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1004(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1005(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1006(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1007(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1008(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1009(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1010(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1011(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1012(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1013(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1014(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1015(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1016(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1017(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1018(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1019(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1020(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1021(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1022(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1023(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1024(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1025(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1026(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1027(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1028(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1029(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1030(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1031(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1032(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1033(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1034(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1035(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1036(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1037(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1038(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1039(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1040(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1041(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1042(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1043(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1044(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1045(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1046(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1047(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1048(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1049(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1050(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1051(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1052(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1053(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1054(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1055(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1056(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1057(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1058(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1059(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1060(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1061(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1062(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1063(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1064(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1065(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1066(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1067(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1068(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1069(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1070(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1071(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1072(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1073(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1074(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1075(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1076(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1077(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1078(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1079(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1080(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1081(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1082(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1083(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1084(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1085(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1086(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1087(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1088(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1089(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1090(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1091(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1092(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1093(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1094(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1095(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1096(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1097(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1098(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1099(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1100(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1101(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1102(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1103(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1104(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1105(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1106(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1107(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1108(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1109(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1110(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1111(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1112(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1113(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1114(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1115(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1116(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1126(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1127(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1128(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1129(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1130(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1131(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1132(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1133(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1134(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1135(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1136(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1137(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1138(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1139(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1141(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1142(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1143(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1144(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1145(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1147(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1148(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1151(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1153(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1154(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1156(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1157(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1159(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1160(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1162(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1163(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1166(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1169(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1177(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1178(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1180(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1181(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1183(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1184(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1186(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1187(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1188(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1189(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1190(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1191(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1192(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1202(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1204(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1205(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1206(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1207(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1208(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1209(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1210(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1211(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1212(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1213(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1214(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1215(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1216(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1217(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1218(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1222(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1223(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1224(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1225(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1226(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1227(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1233(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1234(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1235(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1236(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1237(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1238(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1239(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1240(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1241(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1242(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1243(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1244(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1245(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1246(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1247(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1248(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1249(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1252(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1253(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1255(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1256(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1260(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1261(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1262(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1263(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1267(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1268(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1269(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1270(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1329(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1330(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1331(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1332(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1333(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1334(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1335(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1336(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1337(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1338(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1339(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1340(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1341(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1342(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1343(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1344(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1345(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1346(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1347(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1348(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1349(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1350(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1351(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1352(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1353(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1354(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1359(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1361(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1362(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1363(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1364(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1365(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1366(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1367(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1368(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1369(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1370(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1371(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1372(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1373(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1374(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1375(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1376(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1377(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1378(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1379(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1380(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1381(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1382(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1383(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1384(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1385(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1386(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1387(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1388(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1389(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1390(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1391(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1392(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1393(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1394(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1395(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1396(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1398(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1399(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1408(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1409(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1410(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1411(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1412(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1413(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1414(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1415(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1416(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1417(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1418(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1419(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1420(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1421(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1422(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1423(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1424(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1425(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1426(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1427(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1428(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1429(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1430(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1431(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1432(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1433(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1434(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1435(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1436(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1437(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1438(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1439(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1440(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1441(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1442(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1443(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1444(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1446(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1447(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1919(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1920(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1928(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1929(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1930(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3506(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3507(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3514(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3515(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3516(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3523(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3524(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3531(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3532(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3533(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3568(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3569(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3570(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3577(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3578(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3613(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3614(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3615(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3650(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3651(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3686(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3687(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3688(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3695(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3696(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3697(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3760(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3761(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3796(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3797(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3798(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3799(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3800(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3807(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3808(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3809(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3810(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3811(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3846(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3847(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3848(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3967(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3968(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3969(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3976(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3977(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1816(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1844(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1872(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1900(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1946(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1974(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2002(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2030(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2058(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2086(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2114(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2142(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2226(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2338(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2366(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2394(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2422(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2450(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2478(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2608(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2636(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2664(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2692(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2720(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2748(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2776(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2804(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3431(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3459(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3487(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3549(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3594(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3631(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3667(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3713(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3741(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3777(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3827(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3864(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3892(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3920(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3948(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3993(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4042(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4069(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4096(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4150(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4177(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4218(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4519(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4547(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4575(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4603(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4631(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4659(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4687(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4737(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4780(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4823(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4850(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4877(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4904(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4931(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_4958(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[2877] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1221, (funcp)execute_1222, (funcp)execute_1223, (funcp)execute_1224, (funcp)execute_1225, (funcp)execute_27, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_4929, (funcp)execute_4930, (funcp)execute_4932, (funcp)execute_4933, (funcp)execute_4934, (funcp)execute_4935, (funcp)execute_4936, (funcp)execute_4937, (funcp)execute_4938, (funcp)execute_4939, (funcp)execute_4940, (funcp)execute_4941, (funcp)execute_4942, (funcp)execute_4943, (funcp)execute_4944, (funcp)execute_4945, (funcp)execute_4946, (funcp)execute_4947, (funcp)execute_4948, (funcp)execute_4949, (funcp)execute_4950, (funcp)execute_4951, (funcp)execute_4952, (funcp)execute_4953, (funcp)execute_4954, (funcp)execute_4955, (funcp)execute_4956, (funcp)execute_4957, (funcp)execute_4958, (funcp)execute_4959, (funcp)execute_4960, (funcp)execute_4961, (funcp)execute_4962, (funcp)execute_4963, (funcp)execute_4964, (funcp)execute_4965, (funcp)execute_4966, (funcp)execute_4967, (funcp)execute_4968, (funcp)execute_4969, (funcp)execute_4970, (funcp)execute_4971, (funcp)execute_4972, (funcp)execute_4973, (funcp)execute_4974, (funcp)execute_4975, (funcp)execute_4976, (funcp)execute_4977, (funcp)execute_4978, (funcp)execute_4979, (funcp)execute_4980, (funcp)execute_4981, (funcp)execute_4982, (funcp)execute_4983, (funcp)execute_4984, (funcp)execute_4985, (funcp)execute_4986, (funcp)execute_4987, (funcp)execute_4988, (funcp)execute_4989, (funcp)execute_4990, (funcp)execute_4991, (funcp)execute_4992, (funcp)execute_4993, (funcp)execute_4994, (funcp)execute_4995, (funcp)execute_4996, (funcp)execute_4997, (funcp)execute_4998, (funcp)execute_4999, (funcp)execute_5000, (funcp)execute_5001, (funcp)execute_5002, (funcp)execute_5003, (funcp)execute_5004, (funcp)execute_5005, (funcp)execute_5006, (funcp)execute_5007, (funcp)execute_5008, (funcp)execute_5009, (funcp)execute_5010, (funcp)execute_5011, (funcp)execute_5012, (funcp)execute_5013, (funcp)execute_5014, (funcp)execute_5015, (funcp)execute_5016, (funcp)execute_5017, (funcp)execute_5018, (funcp)execute_5019, (funcp)execute_5020, (funcp)execute_5021, (funcp)execute_5022, (funcp)execute_5023, (funcp)execute_5024, (funcp)execute_5025, (funcp)execute_5026, (funcp)execute_5027, (funcp)execute_5028, (funcp)execute_5029, (funcp)execute_5030, (funcp)execute_5031, (funcp)execute_5032, (funcp)execute_5033, (funcp)execute_5034, (funcp)execute_5035, (funcp)execute_5036, (funcp)execute_5037, (funcp)execute_5038, (funcp)execute_5039, (funcp)execute_5040, (funcp)execute_5041, (funcp)execute_5042, (funcp)execute_5043, (funcp)execute_5044, (funcp)execute_5045, (funcp)execute_5046, (funcp)execute_5047, (funcp)execute_5048, (funcp)execute_5049, (funcp)execute_5050, (funcp)execute_5051, (funcp)execute_5052, (funcp)execute_5053, (funcp)execute_5054, (funcp)execute_5055, (funcp)execute_5056, (funcp)execute_5057, (funcp)execute_5058, (funcp)execute_5059, (funcp)execute_5060, (funcp)execute_5061, (funcp)execute_5062, (funcp)execute_5063, (funcp)execute_5064, (funcp)execute_5065, (funcp)execute_5066, (funcp)execute_5067, (funcp)execute_5068, (funcp)execute_5069, (funcp)execute_5070, (funcp)execute_5071, (funcp)execute_5072, (funcp)execute_5073, (funcp)execute_5074, (funcp)execute_5075, (funcp)execute_5076, (funcp)execute_5077, (funcp)execute_5078, (funcp)execute_5079, (funcp)execute_5080, (funcp)execute_5081, (funcp)execute_5082, (funcp)execute_5083, (funcp)execute_5084, (funcp)execute_5085, (funcp)execute_5086, (funcp)execute_5087, (funcp)execute_5088, (funcp)execute_5089, (funcp)execute_5090, (funcp)execute_5091, (funcp)execute_5092, (funcp)execute_5093, (funcp)execute_5094, (funcp)execute_5095, (funcp)execute_5096, (funcp)execute_5097, (funcp)execute_5098, (funcp)execute_5099, (funcp)execute_5100, (funcp)execute_5101, (funcp)execute_5102, (funcp)execute_5103, (funcp)execute_5104, (funcp)execute_5105, (funcp)execute_5106, (funcp)execute_5107, (funcp)execute_5108, (funcp)execute_5109, (funcp)execute_5110, (funcp)execute_5111, (funcp)execute_5112, (funcp)execute_5113, (funcp)execute_5114, (funcp)execute_5115, (funcp)execute_5116, (funcp)execute_5117, (funcp)execute_5118, (funcp)execute_5119, (funcp)execute_5120, (funcp)execute_5121, (funcp)execute_5122, (funcp)execute_5123, (funcp)execute_5124, (funcp)execute_5125, (funcp)execute_5126, (funcp)execute_5127, (funcp)execute_5128, (funcp)execute_5129, (funcp)execute_5130, (funcp)execute_5131, (funcp)execute_5132, (funcp)execute_5133, (funcp)execute_5134, (funcp)execute_5135, (funcp)execute_5136, (funcp)execute_5137, (funcp)execute_5138, (funcp)execute_5139, (funcp)execute_5140, (funcp)execute_5141, (funcp)execute_5142, (funcp)execute_5143, (funcp)execute_5144, (funcp)execute_5145, (funcp)execute_5146, (funcp)execute_5147, (funcp)execute_5148, (funcp)execute_5149, (funcp)execute_5150, (funcp)execute_5151, (funcp)execute_5152, (funcp)execute_5153, (funcp)execute_5154, (funcp)execute_5155, (funcp)execute_5156, (funcp)execute_5157, (funcp)execute_5158, (funcp)execute_5159, (funcp)execute_5160, (funcp)execute_5161, (funcp)execute_5162, (funcp)execute_5163, (funcp)execute_5164, (funcp)execute_5165, (funcp)execute_5166, (funcp)execute_5167, (funcp)execute_5168, (funcp)execute_5169, (funcp)execute_5170, (funcp)execute_5171, (funcp)execute_5172, (funcp)execute_5173, (funcp)execute_5174, (funcp)execute_5175, (funcp)execute_5176, (funcp)execute_5177, (funcp)execute_5178, (funcp)execute_5179, (funcp)execute_5180, (funcp)execute_5181, (funcp)execute_5182, (funcp)execute_5183, (funcp)execute_5184, (funcp)execute_5185, (funcp)execute_5186, (funcp)execute_5187, (funcp)execute_5188, (funcp)execute_5189, (funcp)execute_5190, (funcp)execute_5191, (funcp)execute_5192, (funcp)execute_5193, (funcp)execute_5194, (funcp)execute_5195, (funcp)execute_5196, (funcp)execute_5197, (funcp)execute_5198, (funcp)execute_5199, (funcp)execute_5200, (funcp)execute_5201, (funcp)execute_5202, (funcp)execute_5203, (funcp)execute_5204, (funcp)execute_5205, (funcp)execute_5206, (funcp)execute_5207, (funcp)execute_5208, (funcp)execute_5209, (funcp)execute_5210, (funcp)execute_5211, (funcp)execute_5212, (funcp)execute_5213, (funcp)execute_5214, (funcp)execute_5215, (funcp)execute_5216, (funcp)execute_5217, (funcp)execute_5218, (funcp)execute_5219, (funcp)execute_5220, (funcp)execute_5221, (funcp)execute_5222, (funcp)execute_5223, (funcp)execute_5224, (funcp)execute_5225, (funcp)execute_5226, (funcp)execute_5227, (funcp)execute_5228, (funcp)execute_5229, (funcp)execute_5230, (funcp)execute_5231, (funcp)execute_5232, (funcp)execute_5233, (funcp)execute_5234, (funcp)execute_5235, (funcp)execute_5236, (funcp)execute_5237, (funcp)execute_5238, (funcp)execute_5239, (funcp)execute_5240, (funcp)execute_5241, (funcp)execute_5242, (funcp)execute_5243, (funcp)execute_5244, (funcp)execute_5245, (funcp)execute_5246, (funcp)execute_5247, (funcp)execute_5248, (funcp)execute_5249, (funcp)execute_5250, (funcp)execute_5251, (funcp)execute_5252, (funcp)execute_5253, (funcp)execute_5254, (funcp)execute_5255, (funcp)execute_5256, (funcp)execute_5257, (funcp)execute_5258, (funcp)execute_5259, (funcp)execute_5260, (funcp)execute_5261, (funcp)execute_5262, (funcp)execute_5263, (funcp)execute_5264, (funcp)execute_5265, (funcp)execute_5266, (funcp)execute_5267, (funcp)execute_5268, (funcp)execute_5269, (funcp)execute_5270, (funcp)execute_5271, (funcp)execute_5272, (funcp)execute_5273, (funcp)execute_5274, (funcp)execute_5275, (funcp)execute_5276, (funcp)execute_5277, (funcp)execute_5278, (funcp)execute_5279, (funcp)execute_5280, (funcp)execute_5281, (funcp)execute_5282, (funcp)execute_5283, (funcp)execute_5284, (funcp)execute_5285, (funcp)execute_5286, (funcp)execute_5287, (funcp)execute_5288, (funcp)execute_5289, (funcp)execute_5290, (funcp)execute_5291, (funcp)execute_5292, (funcp)execute_5293, (funcp)execute_5294, (funcp)execute_5295, (funcp)execute_5296, (funcp)execute_5297, (funcp)execute_5298, (funcp)execute_5299, (funcp)execute_5300, (funcp)execute_5301, (funcp)execute_5302, (funcp)execute_5303, (funcp)execute_5304, (funcp)execute_5305, (funcp)execute_5306, (funcp)execute_5307, (funcp)execute_5308, (funcp)execute_5309, (funcp)execute_5310, (funcp)execute_5311, (funcp)execute_5312, (funcp)execute_5313, (funcp)execute_5314, (funcp)execute_5315, (funcp)execute_5316, (funcp)execute_5317, (funcp)execute_5318, (funcp)execute_5319, (funcp)execute_5320, (funcp)execute_5321, (funcp)execute_5322, (funcp)execute_5323, (funcp)execute_5324, (funcp)execute_5325, (funcp)execute_5326, (funcp)execute_5327, (funcp)execute_5328, (funcp)execute_5329, (funcp)execute_5330, (funcp)execute_5331, (funcp)execute_5332, (funcp)execute_5333, (funcp)execute_5334, (funcp)execute_5335, (funcp)execute_5336, (funcp)execute_5337, (funcp)execute_5338, (funcp)execute_5339, (funcp)execute_5340, (funcp)execute_5341, (funcp)execute_5342, (funcp)execute_5343, (funcp)execute_5344, (funcp)execute_5345, (funcp)execute_5346, (funcp)execute_5347, (funcp)execute_5348, (funcp)execute_5349, (funcp)execute_5350, (funcp)execute_5351, (funcp)execute_5352, (funcp)execute_5353, (funcp)execute_5354, (funcp)execute_5355, (funcp)execute_5356, (funcp)execute_5357, (funcp)execute_5358, (funcp)execute_5359, (funcp)execute_5360, (funcp)execute_5361, (funcp)execute_5362, (funcp)execute_5363, (funcp)execute_5364, (funcp)execute_5365, (funcp)execute_5366, (funcp)execute_5367, (funcp)execute_5368, (funcp)execute_5369, (funcp)execute_5370, (funcp)execute_5371, (funcp)execute_5372, (funcp)execute_5373, (funcp)execute_5374, (funcp)execute_5375, (funcp)execute_5376, (funcp)execute_5377, (funcp)execute_5378, (funcp)execute_5379, (funcp)execute_5380, (funcp)execute_5381, (funcp)execute_5382, (funcp)execute_5383, (funcp)execute_5384, (funcp)execute_5385, (funcp)execute_5386, (funcp)execute_5387, (funcp)execute_5388, (funcp)execute_5389, (funcp)execute_5390, (funcp)execute_5391, (funcp)execute_5392, (funcp)execute_5393, (funcp)execute_5394, (funcp)execute_5395, (funcp)execute_5396, (funcp)execute_5397, (funcp)execute_5398, (funcp)execute_5399, (funcp)execute_5400, (funcp)execute_5401, (funcp)execute_5402, (funcp)execute_5403, (funcp)execute_5404, (funcp)execute_5405, (funcp)execute_5406, (funcp)execute_5407, (funcp)execute_5408, (funcp)execute_5409, (funcp)execute_5410, (funcp)execute_5411, (funcp)execute_5412, (funcp)execute_5413, (funcp)execute_5414, (funcp)execute_5415, (funcp)execute_5416, (funcp)execute_5417, (funcp)execute_5418, (funcp)execute_5419, (funcp)execute_5420, (funcp)execute_5421, (funcp)execute_5422, (funcp)execute_5423, (funcp)execute_5424, (funcp)execute_5425, (funcp)execute_5426, (funcp)execute_5427, (funcp)execute_5428, (funcp)execute_5429, (funcp)execute_5430, (funcp)execute_5431, (funcp)execute_5432, (funcp)execute_5433, (funcp)execute_5434, (funcp)execute_5435, (funcp)execute_5436, (funcp)execute_5437, (funcp)execute_5438, (funcp)execute_5439, (funcp)execute_5440, (funcp)execute_5441, (funcp)execute_5442, (funcp)execute_5443, (funcp)execute_5444, (funcp)execute_5445, (funcp)execute_5446, (funcp)execute_5447, (funcp)execute_5448, (funcp)execute_5449, (funcp)execute_5450, (funcp)execute_5451, (funcp)execute_5452, (funcp)execute_5453, (funcp)execute_5454, (funcp)execute_5455, (funcp)execute_5456, (funcp)execute_5457, (funcp)execute_5458, (funcp)execute_5459, (funcp)execute_5460, (funcp)execute_5461, (funcp)execute_5462, (funcp)execute_5463, (funcp)execute_5464, (funcp)execute_5465, (funcp)execute_5466, (funcp)execute_5467, (funcp)execute_5468, (funcp)execute_5469, (funcp)execute_5470, (funcp)execute_5471, (funcp)execute_5472, (funcp)execute_5473, (funcp)execute_5474, (funcp)execute_5475, (funcp)execute_5476, (funcp)execute_5477, (funcp)execute_5478, (funcp)execute_5479, (funcp)execute_5480, (funcp)execute_5481, (funcp)execute_5482, (funcp)execute_5483, (funcp)execute_5484, (funcp)execute_5485, (funcp)execute_5486, (funcp)execute_5487, (funcp)execute_5488, (funcp)execute_5489, (funcp)execute_5490, (funcp)execute_5491, (funcp)execute_5492, (funcp)execute_5493, (funcp)execute_5494, (funcp)execute_5495, (funcp)execute_5496, (funcp)execute_5497, (funcp)execute_5498, (funcp)execute_5499, (funcp)execute_5500, (funcp)execute_5501, (funcp)execute_5502, (funcp)execute_5503, (funcp)execute_5504, (funcp)execute_5505, (funcp)execute_5506, (funcp)execute_5507, (funcp)execute_5508, (funcp)execute_5509, (funcp)execute_5510, (funcp)execute_5511, (funcp)execute_5512, (funcp)execute_5513, (funcp)execute_5514, (funcp)execute_5515, (funcp)execute_5516, (funcp)execute_5517, (funcp)execute_5518, (funcp)execute_5519, (funcp)execute_5520, (funcp)execute_5521, (funcp)execute_5522, (funcp)execute_5523, (funcp)execute_5524, (funcp)execute_5525, (funcp)execute_5526, (funcp)execute_5527, (funcp)execute_5528, (funcp)execute_5529, (funcp)execute_5530, (funcp)execute_5531, (funcp)execute_5532, (funcp)execute_5533, (funcp)execute_5534, (funcp)execute_5535, (funcp)execute_5536, (funcp)execute_5537, (funcp)execute_5538, (funcp)execute_5539, (funcp)execute_5540, (funcp)execute_5541, (funcp)execute_5542, (funcp)execute_5543, (funcp)execute_5544, (funcp)execute_5545, (funcp)execute_5546, (funcp)execute_5547, (funcp)execute_5548, (funcp)execute_5549, (funcp)execute_5550, (funcp)execute_5551, (funcp)execute_5552, (funcp)execute_5553, (funcp)execute_5554, (funcp)execute_5555, (funcp)execute_5556, (funcp)execute_5557, (funcp)execute_5558, (funcp)execute_5559, (funcp)execute_5560, (funcp)execute_5561, (funcp)execute_5562, (funcp)execute_5563, (funcp)execute_5564, (funcp)execute_5565, (funcp)execute_5566, (funcp)execute_5567, (funcp)execute_5568, (funcp)execute_5569, (funcp)execute_5570, (funcp)execute_5571, (funcp)execute_5572, (funcp)execute_5573, (funcp)execute_5574, (funcp)execute_5575, (funcp)execute_5576, (funcp)execute_5577, (funcp)execute_5578, (funcp)execute_5579, (funcp)execute_5580, (funcp)execute_5581, (funcp)execute_5582, (funcp)execute_5583, (funcp)execute_5584, (funcp)execute_5585, (funcp)execute_5586, (funcp)execute_5587, (funcp)execute_5588, (funcp)execute_5589, (funcp)execute_5590, (funcp)execute_5591, (funcp)execute_5592, (funcp)execute_5593, (funcp)execute_5594, (funcp)execute_5595, (funcp)execute_5596, (funcp)execute_5597, (funcp)execute_5598, (funcp)execute_5599, (funcp)execute_5600, (funcp)execute_5601, (funcp)execute_5602, (funcp)execute_5603, (funcp)execute_5604, (funcp)execute_5605, (funcp)execute_5606, (funcp)execute_5607, (funcp)execute_5608, (funcp)execute_5609, (funcp)execute_5610, (funcp)execute_5611, (funcp)execute_5612, (funcp)execute_5613, (funcp)execute_5614, (funcp)execute_5615, (funcp)execute_5616, (funcp)execute_5617, (funcp)execute_5618, (funcp)execute_5619, (funcp)execute_5620, (funcp)execute_5621, (funcp)execute_5622, (funcp)execute_5623, (funcp)execute_5624, (funcp)execute_5625, (funcp)execute_5626, (funcp)execute_5627, (funcp)execute_5628, (funcp)execute_5629, (funcp)execute_5630, (funcp)execute_5631, (funcp)execute_5632, (funcp)execute_5633, (funcp)execute_5634, (funcp)execute_5635, (funcp)execute_5636, (funcp)execute_5637, (funcp)execute_5638, (funcp)execute_5639, (funcp)execute_5640, (funcp)execute_5641, (funcp)execute_5642, (funcp)execute_5643, (funcp)execute_5644, (funcp)execute_5645, (funcp)execute_5646, (funcp)execute_5647, (funcp)execute_5648, (funcp)execute_5649, (funcp)execute_5650, (funcp)execute_5651, (funcp)execute_5652, (funcp)execute_5653, (funcp)execute_5654, (funcp)execute_5655, (funcp)execute_5656, (funcp)execute_5657, (funcp)execute_5658, (funcp)execute_5659, (funcp)execute_5660, (funcp)execute_5661, (funcp)execute_5662, (funcp)execute_5663, (funcp)execute_5664, (funcp)execute_5665, (funcp)execute_5666, (funcp)execute_5667, (funcp)execute_5668, (funcp)execute_5669, (funcp)execute_5670, (funcp)execute_5671, (funcp)execute_5672, (funcp)execute_5673, (funcp)execute_5674, (funcp)execute_5675, (funcp)execute_5676, (funcp)execute_5677, (funcp)execute_5678, (funcp)execute_5679, (funcp)execute_5680, (funcp)execute_5681, (funcp)execute_5682, (funcp)execute_5683, (funcp)execute_5684, (funcp)execute_5685, (funcp)execute_5686, (funcp)execute_5687, (funcp)execute_5688, (funcp)execute_5689, (funcp)execute_5690, (funcp)execute_5691, (funcp)execute_5692, (funcp)execute_5693, (funcp)execute_5694, (funcp)execute_5695, (funcp)execute_5696, (funcp)execute_5697, (funcp)execute_5698, (funcp)execute_5699, (funcp)execute_5700, (funcp)execute_5701, (funcp)execute_5702, (funcp)execute_5703, (funcp)execute_5704, (funcp)execute_5705, (funcp)execute_5706, (funcp)execute_5707, (funcp)execute_5708, (funcp)execute_5709, (funcp)execute_5710, (funcp)execute_5711, (funcp)execute_5712, (funcp)execute_5713, (funcp)execute_5714, (funcp)execute_5715, (funcp)execute_5716, (funcp)execute_5717, (funcp)execute_5718, (funcp)execute_5719, (funcp)execute_5720, (funcp)execute_5721, (funcp)execute_5722, (funcp)execute_5723, (funcp)execute_5724, (funcp)execute_5725, (funcp)execute_5726, (funcp)execute_5727, (funcp)execute_5728, (funcp)execute_5729, (funcp)execute_5730, (funcp)execute_5731, (funcp)execute_5732, (funcp)execute_5733, (funcp)execute_5734, (funcp)execute_5735, (funcp)execute_5736, (funcp)execute_5737, (funcp)execute_5738, (funcp)execute_5739, (funcp)execute_5740, (funcp)execute_5741, (funcp)execute_5742, (funcp)execute_5743, (funcp)execute_5744, (funcp)execute_5745, (funcp)execute_5746, (funcp)execute_5747, (funcp)execute_5748, (funcp)execute_5749, (funcp)execute_5750, (funcp)execute_5751, (funcp)execute_5752, (funcp)execute_5753, (funcp)execute_5754, (funcp)execute_5755, (funcp)execute_5756, (funcp)execute_5757, (funcp)execute_5758, (funcp)execute_5759, (funcp)execute_5760, (funcp)execute_5761, (funcp)execute_5762, (funcp)execute_5763, (funcp)execute_5764, (funcp)execute_5765, (funcp)execute_5766, (funcp)execute_5767, (funcp)execute_5768, (funcp)execute_5769, (funcp)execute_5770, (funcp)execute_5771, (funcp)execute_5772, (funcp)execute_5773, (funcp)execute_5774, (funcp)execute_5775, (funcp)execute_5776, (funcp)execute_5777, (funcp)execute_5778, (funcp)execute_5779, (funcp)execute_5780, (funcp)execute_5781, (funcp)execute_5782, (funcp)execute_5783, (funcp)execute_5784, (funcp)execute_5785, (funcp)execute_5786, (funcp)execute_5787, (funcp)execute_5788, (funcp)execute_5789, (funcp)execute_5790, (funcp)execute_5791, (funcp)execute_5792, (funcp)execute_5793, (funcp)execute_5794, (funcp)execute_5795, (funcp)execute_5796, (funcp)execute_5797, (funcp)execute_5798, (funcp)execute_5799, (funcp)execute_5800, (funcp)execute_5801, (funcp)execute_5802, (funcp)execute_5803, (funcp)execute_5804, (funcp)execute_5805, (funcp)execute_5806, (funcp)execute_5807, (funcp)execute_5808, (funcp)execute_5809, (funcp)execute_5810, (funcp)execute_5811, (funcp)execute_5812, (funcp)execute_5813, (funcp)execute_5814, (funcp)execute_5815, (funcp)execute_5816, (funcp)execute_5817, (funcp)execute_5818, (funcp)execute_5819, (funcp)execute_5820, (funcp)execute_5821, (funcp)execute_5822, (funcp)execute_5823, (funcp)execute_5824, (funcp)execute_5825, (funcp)execute_5826, (funcp)execute_5827, (funcp)execute_5828, (funcp)execute_5829, (funcp)execute_5830, (funcp)execute_5831, (funcp)execute_5832, (funcp)execute_5833, (funcp)execute_5834, (funcp)execute_5835, (funcp)execute_5836, (funcp)execute_5837, (funcp)execute_5838, (funcp)execute_5839, (funcp)execute_5840, (funcp)execute_5841, (funcp)execute_5842, (funcp)execute_5843, (funcp)execute_5844, (funcp)execute_5845, (funcp)execute_5846, (funcp)execute_5847, (funcp)execute_5848, (funcp)execute_5849, (funcp)execute_5850, (funcp)execute_5851, (funcp)execute_5852, (funcp)execute_5853, (funcp)execute_5854, (funcp)execute_5855, (funcp)execute_5856, (funcp)execute_5857, (funcp)execute_5858, (funcp)execute_5859, (funcp)execute_5860, (funcp)execute_5861, (funcp)execute_5862, (funcp)execute_5863, (funcp)execute_5864, (funcp)execute_5865, (funcp)execute_5866, (funcp)execute_5867, (funcp)execute_5868, (funcp)execute_5869, (funcp)execute_5870, (funcp)execute_5871, (funcp)execute_5872, (funcp)execute_5873, (funcp)execute_5874, (funcp)execute_5875, (funcp)execute_5876, (funcp)execute_5877, (funcp)execute_5878, (funcp)execute_5879, (funcp)execute_5880, (funcp)execute_5881, (funcp)execute_5882, (funcp)execute_5883, (funcp)execute_5884, (funcp)execute_5885, (funcp)execute_5886, (funcp)execute_5887, (funcp)execute_5888, (funcp)execute_5889, (funcp)execute_5890, (funcp)execute_5891, (funcp)execute_5892, (funcp)execute_5893, (funcp)execute_5894, (funcp)execute_5895, (funcp)execute_5896, (funcp)execute_5897, (funcp)execute_5898, (funcp)execute_5899, (funcp)execute_5900, (funcp)execute_5901, (funcp)execute_5902, (funcp)execute_5903, (funcp)execute_5904, (funcp)execute_5905, (funcp)execute_5906, (funcp)execute_5907, (funcp)execute_5908, (funcp)execute_5909, (funcp)execute_5910, (funcp)execute_5911, (funcp)execute_5912, (funcp)execute_5913, (funcp)execute_5914, (funcp)execute_5915, (funcp)execute_5916, (funcp)execute_5917, (funcp)execute_5918, (funcp)execute_5919, (funcp)execute_5920, (funcp)execute_5921, (funcp)execute_5922, (funcp)execute_5923, (funcp)execute_5924, (funcp)execute_5925, (funcp)execute_5926, (funcp)execute_5927, (funcp)execute_5928, (funcp)execute_5929, (funcp)execute_5930, (funcp)execute_5931, (funcp)execute_5932, (funcp)execute_5933, (funcp)execute_5934, (funcp)execute_5935, (funcp)execute_5936, (funcp)execute_5937, (funcp)execute_5938, (funcp)execute_5939, (funcp)execute_5940, (funcp)execute_5941, (funcp)execute_5942, (funcp)execute_5943, (funcp)execute_5944, (funcp)execute_5945, (funcp)execute_5946, (funcp)execute_5947, (funcp)execute_5948, (funcp)execute_5949, (funcp)execute_5950, (funcp)execute_5951, (funcp)execute_5952, (funcp)execute_5953, (funcp)execute_5954, (funcp)execute_5955, (funcp)execute_5956, (funcp)execute_5957, (funcp)execute_5958, (funcp)execute_5959, (funcp)execute_5960, (funcp)execute_5961, (funcp)execute_5962, (funcp)execute_5963, (funcp)execute_5964, (funcp)execute_5965, (funcp)execute_5966, (funcp)execute_5967, (funcp)execute_5968, (funcp)execute_5969, (funcp)execute_5970, (funcp)execute_5971, (funcp)execute_5972, (funcp)execute_5973, (funcp)execute_5974, (funcp)execute_5975, (funcp)execute_5976, (funcp)execute_5977, (funcp)execute_5978, (funcp)execute_5979, (funcp)execute_5980, (funcp)execute_5981, (funcp)execute_5982, (funcp)execute_5983, (funcp)execute_5984, (funcp)execute_5985, (funcp)execute_5986, (funcp)execute_5987, (funcp)execute_5988, (funcp)execute_5989, (funcp)execute_5990, (funcp)execute_5991, (funcp)execute_5992, (funcp)execute_5993, (funcp)execute_5994, (funcp)execute_5995, (funcp)execute_5996, (funcp)execute_5997, (funcp)execute_5998, (funcp)execute_5999, (funcp)execute_6000, (funcp)execute_6001, (funcp)execute_6002, (funcp)execute_6003, (funcp)execute_6004, (funcp)execute_6005, (funcp)execute_6006, (funcp)execute_6007, (funcp)execute_6008, (funcp)execute_6009, (funcp)execute_6010, (funcp)execute_6011, (funcp)execute_6012, (funcp)execute_6013, (funcp)execute_6014, (funcp)execute_6015, (funcp)execute_6016, (funcp)execute_6017, (funcp)execute_6018, (funcp)execute_6019, (funcp)execute_6020, (funcp)execute_6021, (funcp)execute_6022, (funcp)execute_6023, (funcp)execute_6024, (funcp)execute_6025, (funcp)execute_6026, (funcp)execute_6027, (funcp)execute_6028, (funcp)execute_6029, (funcp)execute_6030, (funcp)execute_6031, (funcp)execute_6032, (funcp)execute_6033, (funcp)execute_6034, (funcp)execute_6035, (funcp)execute_6036, (funcp)execute_6037, (funcp)execute_6038, (funcp)execute_6039, (funcp)execute_6040, (funcp)execute_6041, (funcp)execute_6042, (funcp)execute_6043, (funcp)execute_6044, (funcp)execute_6045, (funcp)execute_6046, (funcp)execute_6047, (funcp)execute_6048, (funcp)execute_6049, (funcp)execute_6050, (funcp)execute_6051, (funcp)execute_6052, (funcp)execute_6053, (funcp)execute_6054, (funcp)execute_6055, (funcp)execute_6056, (funcp)execute_6057, (funcp)execute_6058, (funcp)execute_30, (funcp)execute_1236, (funcp)execute_1237, (funcp)execute_1238, (funcp)execute_1239, (funcp)execute_1235, (funcp)execute_40, (funcp)execute_41, (funcp)execute_1250, (funcp)execute_44, (funcp)execute_45, (funcp)execute_1251, (funcp)execute_48, (funcp)execute_1253, (funcp)execute_1254, (funcp)execute_1252, (funcp)execute_51, (funcp)execute_1256, (funcp)execute_1257, (funcp)execute_1258, (funcp)execute_1259, (funcp)execute_1260, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)execute_1255, (funcp)execute_57, (funcp)execute_58, (funcp)execute_1273, (funcp)execute_202, (funcp)execute_203, (funcp)execute_204, (funcp)execute_205, (funcp)execute_1390, (funcp)execute_1391, (funcp)execute_1392, (funcp)execute_1393, (funcp)execute_1394, (funcp)execute_1395, (funcp)execute_1396, (funcp)execute_1397, (funcp)execute_1398, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_1400, (funcp)execute_1401, (funcp)execute_1402, (funcp)execute_1403, (funcp)execute_1404, (funcp)execute_1405, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1, (funcp)vlog_timingcheck_execute_0, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_2, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1315, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1316, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1317, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1318, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1319, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1320, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1321, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1322, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1323, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1324, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1325, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1326, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1327, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1328, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1329, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1330, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1331, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1332, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1333, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1334, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1335, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1336, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1337, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_1338, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_27, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_28, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_29, (funcp)timing_checker_condition_m_5bad0dee1e5d9f23_63e0cb37_30, (funcp)execute_1424, (funcp)execute_1430, (funcp)execute_1431, (funcp)execute_1432, (funcp)execute_207, (funcp)execute_208, (funcp)execute_209, (funcp)execute_210, (funcp)execute_1433, (funcp)execute_1434, (funcp)execute_1435, (funcp)execute_1436, (funcp)execute_1437, (funcp)execute_1438, (funcp)execute_1439, (funcp)execute_1440, (funcp)execute_1441, (funcp)execute_1443, (funcp)execute_1444, (funcp)execute_1445, (funcp)execute_1446, (funcp)execute_1447, (funcp)execute_1448, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_31, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_32, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_565, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_566, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_567, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_568, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_569, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_570, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_571, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_572, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_573, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_574, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_575, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_576, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_577, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_578, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_579, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_580, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_581, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_582, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_583, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_584, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_585, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_586, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_587, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_588, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_57, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_58, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_59, (funcp)timing_checker_condition_m_f806b384d33310e2_af79f1dc_60, (funcp)execute_1467, (funcp)execute_1473, (funcp)execute_1474, (funcp)execute_1475, (funcp)execute_1562, (funcp)execute_1563, (funcp)execute_1564, (funcp)execute_1567, (funcp)execute_1568, (funcp)execute_1569, (funcp)execute_1570, (funcp)execute_377, (funcp)execute_378, (funcp)execute_379, (funcp)execute_380, (funcp)execute_2461, (funcp)execute_2462, (funcp)execute_2463, (funcp)execute_2464, (funcp)execute_2465, (funcp)execute_2466, (funcp)execute_2467, (funcp)execute_2468, (funcp)execute_2470, (funcp)execute_2471, (funcp)execute_2472, (funcp)execute_2473, (funcp)execute_2474, (funcp)execute_2475, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_589, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_590, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1699, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1700, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1701, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1702, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1703, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1704, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1705, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1706, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1707, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1708, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1709, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1710, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1711, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1712, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1713, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1714, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1715, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1716, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1717, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1718, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1719, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1720, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1721, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_1722, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_615, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_616, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_617, (funcp)timing_checker_condition_m_bcc6547dca05b147_67151b0a_618, (funcp)execute_2494, (funcp)execute_2499, (funcp)execute_2500, (funcp)execute_2501, (funcp)execute_4039, (funcp)execute_888, (funcp)execute_4042, (funcp)execute_930, (funcp)execute_4063, (funcp)execute_4064, (funcp)execute_4065, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_54, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_73, (funcp)transaction_74, (funcp)transaction_75, (funcp)transaction_76, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_84, (funcp)transaction_85, (funcp)transaction_86, (funcp)transaction_87, (funcp)transaction_88, (funcp)transaction_89, (funcp)transaction_90, (funcp)transaction_91, (funcp)transaction_92, (funcp)transaction_93, (funcp)transaction_94, (funcp)transaction_95, (funcp)transaction_96, (funcp)transaction_97, (funcp)transaction_98, (funcp)transaction_99, (funcp)transaction_100, (funcp)transaction_101, (funcp)transaction_102, (funcp)transaction_103, (funcp)transaction_104, (funcp)transaction_105, (funcp)transaction_106, (funcp)transaction_107, (funcp)transaction_108, (funcp)transaction_109, (funcp)transaction_110, (funcp)transaction_111, (funcp)transaction_112, (funcp)transaction_113, (funcp)transaction_114, (funcp)transaction_115, (funcp)transaction_116, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_126, (funcp)transaction_127, (funcp)transaction_128, (funcp)transaction_129, (funcp)transaction_130, (funcp)transaction_131, (funcp)transaction_132, (funcp)transaction_133, (funcp)transaction_134, (funcp)transaction_135, (funcp)transaction_136, (funcp)transaction_137, (funcp)transaction_138, (funcp)transaction_139, (funcp)transaction_140, (funcp)transaction_141, (funcp)transaction_142, (funcp)transaction_143, (funcp)transaction_144, (funcp)transaction_145, (funcp)transaction_146, (funcp)transaction_147, (funcp)transaction_148, (funcp)transaction_149, (funcp)transaction_150, (funcp)transaction_151, (funcp)transaction_152, (funcp)transaction_153, (funcp)transaction_154, (funcp)transaction_155, (funcp)transaction_156, (funcp)transaction_157, (funcp)transaction_158, (funcp)transaction_159, (funcp)transaction_160, (funcp)transaction_161, (funcp)transaction_162, (funcp)transaction_163, (funcp)transaction_164, (funcp)transaction_165, (funcp)transaction_166, (funcp)transaction_167, (funcp)transaction_168, (funcp)transaction_169, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_176, (funcp)transaction_177, (funcp)transaction_178, (funcp)transaction_179, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_182, (funcp)transaction_183, (funcp)transaction_184, (funcp)transaction_185, (funcp)transaction_186, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_189, (funcp)transaction_190, (funcp)transaction_191, (funcp)transaction_192, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_209, (funcp)transaction_210, (funcp)transaction_211, (funcp)transaction_212, (funcp)transaction_213, (funcp)transaction_214, (funcp)transaction_215, (funcp)transaction_216, (funcp)transaction_217, (funcp)transaction_218, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_222, (funcp)transaction_223, (funcp)transaction_224, (funcp)transaction_225, (funcp)transaction_226, (funcp)transaction_227, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_233, (funcp)transaction_234, (funcp)transaction_235, (funcp)transaction_236, (funcp)transaction_237, (funcp)transaction_238, (funcp)transaction_239, (funcp)transaction_240, (funcp)transaction_241, (funcp)transaction_242, (funcp)transaction_243, (funcp)transaction_244, (funcp)transaction_245, (funcp)transaction_246, (funcp)transaction_247, (funcp)transaction_248, (funcp)transaction_249, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_252, (funcp)transaction_253, (funcp)transaction_254, (funcp)transaction_255, (funcp)transaction_256, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_260, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_263, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_270, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_329, (funcp)transaction_330, (funcp)transaction_331, (funcp)transaction_332, (funcp)transaction_333, (funcp)transaction_334, (funcp)transaction_335, (funcp)transaction_336, (funcp)transaction_337, (funcp)transaction_338, (funcp)transaction_339, (funcp)transaction_340, (funcp)transaction_341, (funcp)transaction_342, (funcp)transaction_343, (funcp)transaction_344, (funcp)transaction_345, (funcp)transaction_346, (funcp)transaction_347, (funcp)transaction_348, (funcp)transaction_349, (funcp)transaction_350, (funcp)transaction_351, (funcp)transaction_352, (funcp)transaction_353, (funcp)transaction_354, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_361, (funcp)transaction_362, (funcp)transaction_363, (funcp)transaction_364, (funcp)transaction_365, (funcp)transaction_366, (funcp)transaction_367, (funcp)transaction_368, (funcp)transaction_369, (funcp)transaction_370, (funcp)transaction_371, (funcp)transaction_372, (funcp)transaction_373, (funcp)transaction_374, (funcp)transaction_375, (funcp)transaction_376, (funcp)transaction_377, (funcp)transaction_378, (funcp)transaction_379, (funcp)transaction_380, (funcp)transaction_381, (funcp)transaction_382, (funcp)transaction_383, (funcp)transaction_384, (funcp)transaction_385, (funcp)transaction_386, (funcp)transaction_387, (funcp)transaction_388, (funcp)transaction_389, (funcp)transaction_390, (funcp)transaction_391, (funcp)transaction_392, (funcp)transaction_393, (funcp)transaction_394, (funcp)transaction_395, (funcp)transaction_396, (funcp)transaction_397, (funcp)transaction_398, (funcp)transaction_399, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_407, (funcp)transaction_408, (funcp)transaction_409, (funcp)transaction_410, (funcp)transaction_411, (funcp)transaction_412, (funcp)transaction_413, (funcp)transaction_414, (funcp)transaction_415, (funcp)transaction_416, (funcp)transaction_417, (funcp)transaction_418, (funcp)transaction_419, (funcp)transaction_420, (funcp)transaction_421, (funcp)transaction_422, (funcp)transaction_423, (funcp)transaction_424, (funcp)transaction_425, (funcp)transaction_426, (funcp)transaction_427, (funcp)transaction_428, (funcp)transaction_429, (funcp)transaction_430, (funcp)transaction_431, (funcp)transaction_432, (funcp)transaction_433, (funcp)transaction_434, (funcp)transaction_435, (funcp)transaction_436, (funcp)transaction_437, (funcp)transaction_438, (funcp)transaction_439, (funcp)transaction_440, (funcp)transaction_441, (funcp)transaction_442, (funcp)transaction_443, (funcp)transaction_444, (funcp)transaction_445, (funcp)transaction_446, (funcp)transaction_447, (funcp)transaction_448, (funcp)transaction_449, (funcp)transaction_450, (funcp)transaction_451, (funcp)transaction_452, (funcp)transaction_453, (funcp)transaction_454, (funcp)transaction_455, (funcp)transaction_456, (funcp)transaction_457, (funcp)transaction_458, (funcp)transaction_459, (funcp)transaction_460, (funcp)transaction_461, (funcp)transaction_462, (funcp)transaction_463, (funcp)transaction_464, (funcp)transaction_465, (funcp)transaction_466, (funcp)transaction_467, (funcp)transaction_468, (funcp)transaction_469, (funcp)transaction_470, (funcp)transaction_471, (funcp)transaction_472, (funcp)transaction_473, (funcp)transaction_474, (funcp)transaction_475, (funcp)transaction_476, (funcp)transaction_477, (funcp)transaction_478, (funcp)transaction_479, (funcp)transaction_480, (funcp)transaction_481, (funcp)transaction_482, (funcp)transaction_483, (funcp)transaction_484, (funcp)transaction_485, (funcp)transaction_486, (funcp)transaction_487, (funcp)transaction_488, (funcp)transaction_489, (funcp)transaction_490, (funcp)transaction_491, (funcp)transaction_492, (funcp)transaction_493, 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(funcp)transaction_1266, (funcp)transaction_1267, (funcp)transaction_1268, (funcp)transaction_1269, (funcp)transaction_1270, (funcp)transaction_1271, (funcp)transaction_1272, (funcp)transaction_1273, (funcp)transaction_1274, (funcp)transaction_1275, (funcp)transaction_1276, (funcp)transaction_1277, (funcp)transaction_1278, (funcp)transaction_1279, (funcp)transaction_1280, (funcp)transaction_1281, (funcp)transaction_1282, (funcp)transaction_1283, (funcp)transaction_1284, (funcp)transaction_1285, (funcp)transaction_1286, (funcp)transaction_1287, (funcp)transaction_1288, (funcp)transaction_1289, (funcp)transaction_1290, (funcp)transaction_1291, (funcp)transaction_1292, (funcp)transaction_1293, (funcp)transaction_1294, (funcp)transaction_1295, (funcp)transaction_1296, (funcp)transaction_1297, (funcp)transaction_1298, (funcp)transaction_1299, (funcp)transaction_1300, (funcp)transaction_1301, (funcp)transaction_1302, (funcp)transaction_1303, (funcp)transaction_1304, (funcp)transaction_1305, (funcp)transaction_1306, (funcp)transaction_1307, (funcp)transaction_1308, (funcp)transaction_1309, (funcp)transaction_1310, (funcp)transaction_1311, (funcp)transaction_1312, (funcp)transaction_1313, (funcp)transaction_1314, (funcp)transaction_1315, (funcp)transaction_1316, (funcp)transaction_1317, (funcp)transaction_1318, (funcp)transaction_1319, (funcp)transaction_1320, (funcp)transaction_1321, (funcp)transaction_1322, (funcp)transaction_1323, (funcp)transaction_1324, (funcp)transaction_1325, (funcp)transaction_1326, (funcp)transaction_1327, (funcp)transaction_1328, (funcp)transaction_1329, (funcp)transaction_1330, (funcp)transaction_1331, (funcp)transaction_1332, (funcp)transaction_1333, (funcp)transaction_1334, (funcp)transaction_1335, (funcp)transaction_1336, (funcp)transaction_1337, (funcp)transaction_1338, (funcp)transaction_1339, (funcp)transaction_1340, (funcp)transaction_1341, (funcp)transaction_1342, (funcp)transaction_1343, (funcp)transaction_1344, (funcp)transaction_1345, (funcp)transaction_1346, (funcp)transaction_1347, (funcp)transaction_1348, (funcp)transaction_1349, (funcp)transaction_1350, (funcp)transaction_1351, (funcp)transaction_1352, (funcp)transaction_1353, (funcp)transaction_1354, (funcp)transaction_1355, (funcp)transaction_1356, (funcp)transaction_1357, (funcp)transaction_1358, (funcp)transaction_1359, (funcp)transaction_1360, (funcp)transaction_1361, (funcp)transaction_1362, (funcp)transaction_1363, (funcp)transaction_1364, (funcp)transaction_1365, (funcp)transaction_1366, (funcp)transaction_1367, (funcp)transaction_1368, (funcp)transaction_1369, (funcp)transaction_1370, (funcp)transaction_1371, (funcp)transaction_1372, (funcp)transaction_1373, (funcp)transaction_1374, (funcp)transaction_1375, (funcp)transaction_1376, (funcp)transaction_1377, (funcp)transaction_1378, (funcp)transaction_1379, (funcp)transaction_1380, (funcp)transaction_1381, (funcp)transaction_1382, (funcp)transaction_1383, (funcp)transaction_1384, (funcp)transaction_1385, (funcp)transaction_1386, (funcp)transaction_1387, (funcp)transaction_1388, (funcp)transaction_1389, (funcp)transaction_1390, (funcp)transaction_1391, (funcp)transaction_1392, (funcp)transaction_1393, (funcp)transaction_1394, (funcp)transaction_1395, (funcp)transaction_1396, (funcp)transaction_1397, (funcp)transaction_1398, (funcp)transaction_1399, (funcp)transaction_1400, (funcp)transaction_1401, (funcp)transaction_1402, (funcp)transaction_1403, (funcp)transaction_1404, (funcp)transaction_1405, (funcp)transaction_1406, (funcp)transaction_1407, (funcp)transaction_1408, (funcp)transaction_1409, (funcp)transaction_1410, (funcp)transaction_1411, (funcp)transaction_1412, (funcp)transaction_1413, (funcp)transaction_1414, (funcp)transaction_1415, (funcp)transaction_1416, (funcp)transaction_1417, (funcp)transaction_1418, (funcp)transaction_1419, (funcp)transaction_1420, (funcp)transaction_1421, (funcp)transaction_1422, (funcp)transaction_1423, (funcp)transaction_1424, (funcp)transaction_1425, (funcp)transaction_1426, (funcp)transaction_1427, (funcp)transaction_1428, (funcp)transaction_1429, (funcp)transaction_1430, (funcp)transaction_1431, (funcp)transaction_1432, (funcp)transaction_1433, (funcp)transaction_1434, (funcp)transaction_1435, (funcp)transaction_1436, (funcp)transaction_1437, (funcp)transaction_1438, (funcp)transaction_1439, (funcp)transaction_1440, (funcp)transaction_1441, (funcp)transaction_1442, (funcp)transaction_1443, (funcp)transaction_1444, (funcp)transaction_1446, (funcp)transaction_1447, (funcp)transaction_1919, (funcp)transaction_1920, (funcp)transaction_1927, (funcp)transaction_1928, (funcp)transaction_1929, (funcp)transaction_1930, (funcp)transaction_3506, (funcp)transaction_3507, (funcp)transaction_3514, (funcp)transaction_3515, (funcp)transaction_3516, (funcp)transaction_3523, (funcp)transaction_3524, (funcp)transaction_3531, (funcp)transaction_3532, (funcp)transaction_3533, (funcp)transaction_3568, (funcp)transaction_3569, (funcp)transaction_3570, (funcp)transaction_3577, (funcp)transaction_3578, (funcp)transaction_3613, (funcp)transaction_3614, (funcp)transaction_3615, (funcp)transaction_3650, (funcp)transaction_3651, (funcp)transaction_3686, (funcp)transaction_3687, (funcp)transaction_3688, (funcp)transaction_3695, (funcp)transaction_3696, (funcp)transaction_3697, (funcp)transaction_3760, (funcp)transaction_3761, (funcp)transaction_3796, (funcp)transaction_3797, (funcp)transaction_3798, (funcp)transaction_3799, (funcp)transaction_3800, (funcp)transaction_3807, (funcp)transaction_3808, (funcp)transaction_3809, (funcp)transaction_3810, (funcp)transaction_3811, (funcp)transaction_3846, (funcp)transaction_3847, (funcp)transaction_3848, (funcp)transaction_3967, (funcp)transaction_3968, (funcp)transaction_3969, (funcp)transaction_3976, (funcp)transaction_3977, (funcp)transaction_1816, (funcp)transaction_1844, (funcp)transaction_1872, (funcp)transaction_1900, (funcp)transaction_1946, (funcp)transaction_1974, (funcp)transaction_2002, (funcp)transaction_2030, (funcp)transaction_2058, (funcp)transaction_2086, (funcp)transaction_2114, (funcp)transaction_2142, (funcp)transaction_2170, (funcp)transaction_2198, (funcp)transaction_2226, (funcp)transaction_2254, (funcp)transaction_2282, (funcp)transaction_2310, (funcp)transaction_2338, (funcp)transaction_2366, (funcp)transaction_2394, (funcp)transaction_2422, (funcp)transaction_2450, (funcp)transaction_2478, (funcp)transaction_2608, (funcp)transaction_2636, (funcp)transaction_2664, (funcp)transaction_2692, (funcp)transaction_2720, (funcp)transaction_2748, (funcp)transaction_2776, (funcp)transaction_2804, (funcp)transaction_3431, (funcp)transaction_3459, (funcp)transaction_3487, (funcp)transaction_3549, (funcp)transaction_3594, (funcp)transaction_3631, (funcp)transaction_3667, (funcp)transaction_3713, (funcp)transaction_3741, (funcp)transaction_3777, (funcp)transaction_3827, (funcp)transaction_3864, (funcp)transaction_3892, (funcp)transaction_3920, (funcp)transaction_3948, (funcp)transaction_3993, (funcp)transaction_4042, (funcp)transaction_4069, (funcp)transaction_4096, (funcp)transaction_4123, (funcp)transaction_4150, (funcp)transaction_4177, (funcp)transaction_4218, (funcp)transaction_4491, (funcp)transaction_4519, (funcp)transaction_4547, (funcp)transaction_4575, (funcp)transaction_4603, (funcp)transaction_4631, (funcp)transaction_4659, (funcp)transaction_4687, (funcp)transaction_4737, (funcp)transaction_4780, (funcp)transaction_4823, (funcp)transaction_4850, (funcp)transaction_4877, (funcp)transaction_4904, (funcp)transaction_4931, (funcp)transaction_4958}; +const int NumRelocateId= 2877; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_edge_time_synth/xsim.reloc", (void **)funcTab, 2877); + iki_vhdl_file_variable_register(dp + 2603488); + iki_vhdl_file_variable_register(dp + 2603544); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_edge_time_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2608896, dp + 3150184, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2608952, dp + 3150576, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2609008, dp + 3150688, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2609240, dp + 3150800, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2609160, dp + 3150912, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2609200, dp + 3150464, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 2609856, dp + 3150352, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_time_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_time_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_time_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_edge_time_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o new file mode 100644 index 0000000..98c9f80 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.dbg b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.dbg new file mode 100644 index 0000000..b71de3c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.dbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.mem b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.mem new file mode 100644 index 0000000..a9d1372 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.mem differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.reloc b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.reloc new file mode 100644 index 0000000..7170421 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.reloc differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rlx b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rlx new file mode 100644 index 0000000..f080956 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 10190631582523672948 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_time_synth/xsimk\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rtti b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rtti new file mode 100644 index 0000000..6436c7c Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rtti differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.svtype b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.svtype new file mode 100644 index 0000000..e43e4cc Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.svtype differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.type b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.type new file mode 100644 index 0000000..00aa3b5 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.type differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.xdbg b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.xdbg new file mode 100644 index 0000000..c5a706f Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.xdbg differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimSettings.ini b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimSettings.ini new file mode 100644 index 0000000..97a6b10 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=150 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=233 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimcrash.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimk b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimk new file mode 100755 index 0000000..35507f6 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimk differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimkernel.log new file mode 100644 index 0000000..ea6792c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_edge_time_synth/xsimk -simmode gui -wdb project_tb_edge_time_synth.wdb -simrunnum 0 -socket 39331 +Design successfully loaded +Design Loading Memory Usage: 202828 KB (Peak: 202828 KB) +Design Loading CPU Usage: 730 ms +Simulation completed +Simulation Memory Usage: 296232 KB (Peak: 342096 KB) +Simulation CPU Usage: 820 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..549e5c8 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb new file mode 100644 index 0000000..dbc191d Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_reti_logiche.sdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb new file mode 100644 index 0000000..072bbc8 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/project_tb_edge.vdb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..313894b --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,6 @@ +0.7 +2020.2 +Nov 14 2025 +12:36:23 +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v,1781182260,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,, diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xsim.version b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.ini b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.log new file mode 100644 index 0000000..5aef293 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.log @@ -0,0 +1,2 @@ +INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" into library xil_defaultlib +INFO: [VRFC 10-3107] analyzing entity 'project_tb_edge' diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.pb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.pb new file mode 100644 index 0000000..d0ed683 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvhdl.pb differ diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.log b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.log new file mode 100644 index 0000000..2e9b322 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.log @@ -0,0 +1,3 @@ +INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_reti_logiche +INFO: [VRFC 10-311] analyzing module glbl diff --git a/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.pb b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.pb new file mode 100644 index 0000000..61d7c71 Binary files /dev/null and b/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.pb differ diff --git a/progetto_reti_logiche.srcs/sim_1/new/Custom.v b/progetto_reti_logiche.srcs/sim_1/new/Custom.v new file mode 100644 index 0000000..5c086ee --- /dev/null +++ b/progetto_reti_logiche.srcs/sim_1/new/Custom.v @@ -0,0 +1,620 @@ +-- ============================================================ +-- TESTBENCH EDGE CASES - Progetto Reti Logiche 2025/2026 +-- ============================================================ +-- Copre i seguenti gruppi di test: +-- +-- GRUPPO 0: Reset e inizializzazione +-- 0.0 Reset -> addr 0 = 0, DONE = 1 durante reset poi torna 0 +-- 0.1 Reset mentre operazione in corso (START=1) +-- +-- GRUPPO 1: OP=10 - Inserimento +-- 1.0 Insert in lista vuota +-- 1.1 Insert con priorità più alta di tutti (va in testa) +-- 1.2 Insert con priorità più bassa di tutti (va in fondo) +-- 1.3 Insert con priorità uguale -> va in CODA agli uguali +-- 1.4 Insert con tutti i task alla stessa priorità -> sempre in fondo +-- 1.5 Insert in lista piena (63 task) -> operazione ignorata +-- +-- GRUPPO 2: OP=01 - Rimozione +-- 2.0 Rimozione da lista vuota -> o_task_id = 000000 +-- 2.1 Rimozione con un solo task -> lista diventa vuota +-- 2.2 Rimozione da lista con tutti task alla stessa priorità +-- +-- GRUPPO 3: OP=00 - Decremento priorità +-- 3.0 Decremento con lista vuota -> nessuna scrittura, no crash +-- 3.1 Saturazione: task a priorità 3 restano a 3 +-- 3.2 Lista con TUTTI i task già a priorità 3 -> nessuna modifica +-- 3.3 Mix priorità 2 e 3: i "nuovi 3" (ex-2) vengono PRIMA dei "vecchi 3" +-- +-- GRUPPO 4: OP=11 - Svuota lista +-- 4.0 Svuota lista popolata -> addr 0 = 0 +-- 4.1 Svuota lista già vuota -> addr 0 rimane 0 +-- 4.2 Svuota poi rimuovi -> o_task_id = 000000 +-- 4.3 Svuota poi decrementa -> nessun effetto +-- +-- GRUPPO 5: Sequenze composite +-- 5.0 Insert -> Decremento -> Rimozione: verifica ID estratto corretto +-- 5.1 Sequenza di insert con priorità miste -> verifica ordinamento completo +-- +-- ============================================================ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity project_tb_edge is +end project_tb_edge; + +architecture project_tb_edge_arch of project_tb_edge is + + constant CLOCK_PERIOD : time := 20 ns; + signal tb_clk : std_logic := '0'; + signal tb_rst : std_logic; + signal tb_start : std_logic; + signal tb_done : std_logic; + signal tb_o_task_id : std_logic_vector(5 downto 0); + signal tb_task_priority : std_logic_vector(1 downto 0); + signal tb_op : std_logic_vector(1 downto 0); + signal tb_i_task_id : std_logic_vector(5 downto 0); + + signal exc_o_mem_addr : std_logic_vector(15 downto 0); + signal exc_o_mem_data : std_logic_vector(7 downto 0); + signal exc_o_mem_we : std_logic; + signal exc_o_mem_en : std_logic; + + signal init_o_mem_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal init_o_mem_data : std_logic_vector(7 downto 0) := (others => '0'); + signal init_o_mem_we : std_logic := '0'; + signal init_o_mem_en : std_logic := '0'; + + signal tb_o_mem_addr : std_logic_vector(15 downto 0); + signal tb_o_mem_data : std_logic_vector(7 downto 0); + signal tb_o_mem_we : std_logic; + signal tb_o_mem_en : std_logic; + signal tb_i_mem_data : std_logic_vector(7 downto 0); + + signal memory_control : std_logic := '0'; + + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type := (others => "00000000"); + + -- -------------------------------------------------------- + -- Utility: tipo per verifiche memoria + -- -------------------------------------------------------- + type mem_check_t is record + addr : integer; + expected : std_logic_vector(7 downto 0); + end record; + + component project_reti_logiche is + port ( + i_clk : in std_logic; + i_rst : in std_logic; + i_start : in std_logic; + i_task_id : in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op : in std_logic_vector(1 downto 0); + o_done : out std_logic; + o_task_id : out std_logic_vector(5 downto 0); + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we : out std_logic; + o_mem_en : out std_logic + ); + end component project_reti_logiche; + +begin + + UUT : project_reti_logiche + port map ( + i_clk => tb_clk, + i_rst => tb_rst, + i_start => tb_start, + i_task_id => tb_i_task_id, + i_task_priority => tb_task_priority, + i_op => tb_op, + o_done => tb_done, + o_task_id => tb_o_task_id, + o_mem_addr => exc_o_mem_addr, + i_mem_data => tb_i_mem_data, + o_mem_data => exc_o_mem_data, + o_mem_we => exc_o_mem_we, + o_mem_en => exc_o_mem_en + ); + + -- Clock + tb_clk <= not tb_clk after CLOCK_PERIOD / 2; + + -- Memoria + MEM : process (tb_clk) + begin + if tb_clk'event and tb_clk = '1' then + if tb_o_mem_en = '1' then + if tb_o_mem_we = '1' then + RAM(to_integer(unsigned(tb_o_mem_addr))) <= tb_o_mem_data after 1 ns; + tb_i_mem_data <= tb_o_mem_data after 1 ns; + else + tb_i_mem_data <= RAM(to_integer(unsigned(tb_o_mem_addr))) after 1 ns; + end if; + end if; + end if; + end process; + + -- Mux memoria: init_o / exc_o + memory_signal_swapper : process (memory_control, + init_o_mem_addr, init_o_mem_data, init_o_mem_en, init_o_mem_we, + exc_o_mem_addr, exc_o_mem_data, exc_o_mem_en, exc_o_mem_we) + begin + tb_o_mem_addr <= init_o_mem_addr; + tb_o_mem_data <= init_o_mem_data; + tb_o_mem_en <= init_o_mem_en; + tb_o_mem_we <= init_o_mem_we; + if memory_control = '1' then + tb_o_mem_addr <= exc_o_mem_addr; + tb_o_mem_data <= exc_o_mem_data; + tb_o_mem_en <= exc_o_mem_en; + tb_o_mem_we <= exc_o_mem_we; + end if; + end process; + + -- ============================================================ + -- Processo principale di test + -- ============================================================ + main_test : process + + -- -------------------------------------------------------- + -- Procedure di supporto + -- -------------------------------------------------------- + + -- Reset del componente (attende DONE=1 durante reset poi DONE=0) + procedure do_reset is + begin + tb_start <= '0'; + tb_rst <= '1'; + wait for 100 ns; + -- DONE deve essere 1 durante il reset (modulo non pronto) + assert tb_done = '1' + report "FAIL: DONE dovrebbe essere 1 durante reset" + severity failure; + tb_rst <= '0'; + -- Attende che il modulo completi l'inizializzazione (DONE->0) + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + end procedure; + + -- Lancia un'operazione e attende DONE=1 + procedure do_op ( + op : std_logic_vector(1 downto 0); + task_id : std_logic_vector(5 downto 0); + priority : std_logic_vector(1 downto 0) + ) is + begin + wait until falling_edge(tb_clk); + tb_op <= op; + tb_i_task_id <= task_id; + tb_task_priority <= priority; + tb_start <= '1'; + wait until rising_edge(tb_done); + tb_start <= '0'; + wait until falling_edge(tb_done); + end procedure; + + -- Verifica un singolo indirizzo di memoria + procedure check_mem ( + step : string; + addr : integer; + expected : std_logic_vector(7 downto 0) + ) is + begin + assert RAM(addr) = expected + report "FAIL [" & step & "] addr=" & integer'image(addr) + & " expected=0x" & integer'image(to_integer(unsigned(expected))) + & " actual=0x" & integer'image(to_integer(unsigned(RAM(addr)))) + severity failure; + end procedure; + + -- Verifica o_task_id + procedure check_task_id ( + step : string; + expected : std_logic_vector(5 downto 0) + ) is + begin + assert tb_o_task_id = expected + report "FAIL [" & step & "] o_task_id expected=" + & integer'image(to_integer(unsigned(expected))) + & " actual=" + & integer'image(to_integer(unsigned(tb_o_task_id))) + severity failure; + end procedure; + + -- Azzera la RAM (usato per isolare i gruppi di test) + procedure clear_ram is + begin + memory_control <= '0'; + for i in 0 to 70 loop + init_o_mem_addr <= std_logic_vector(to_unsigned(i, 16)); + init_o_mem_data <= "00000000"; + init_o_mem_en <= '1'; + init_o_mem_we <= '1'; + wait until rising_edge(tb_clk); + end loop; + init_o_mem_en <= '0'; + init_o_mem_we <= '0'; + memory_control <= '1'; + end procedure; + + -- Inserisce N task nella lista (usato per riempire la lista) + -- I task avranno ID da start_id a start_id+n-1, tutti con la priorità indicata + procedure fill_list (n : integer; base_id : integer; prio : std_logic_vector(1 downto 0)) is + begin + for k in 0 to n-1 loop + do_op("10", + std_logic_vector(to_unsigned(base_id + k, 6)), + prio); + end loop; + end procedure; + + begin + -- Inizializzazione segnali + tb_start <= '0'; + tb_rst <= '0'; + tb_op <= "00"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + memory_control <= '1'; + + wait for 50 ns; + + -- ============================================================ + -- GRUPPO 0: Reset e inizializzazione + -- ============================================================ + + -- 0.0: Reset base -> addr 0 deve essere 0, DONE=1 durante reset + report "=== GRUPPO 0: Reset ==="; + memory_control <= '0'; + tb_rst <= '1'; + wait for 100 ns; + assert tb_done = '1' + report "FAIL [0.0] DONE deve essere 1 durante reset" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("0.0 reset-addr0", 0, "00000000"); + memory_control <= '1'; + report "Test 0.0 OK: reset base"; + + -- 0.1: Reset mentre operazione in corso + -- Prima inseriamo un task, poi resettiamo a metà + clear_ram; + do_reset; + -- Avviamo un inserimento... + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= "000001"; + tb_task_priority <= "01"; + tb_start <= '1'; + -- Aspettiamo 2 cicli (operazione non ancora completata) + wait until rising_edge(tb_clk); + wait until rising_edge(tb_clk); + -- Reset asincrono! + tb_rst <= '1'; + tb_start <= '0'; + wait for 50 ns; + assert tb_done = '1' + report "FAIL [0.1] DONE deve essere 1 durante reset asincrono" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("0.1 reset-async", 0, "00000000"); + report "Test 0.1 OK: reset asincrono durante operazione"; + + -- ============================================================ + -- GRUPPO 1: OP=10 - Inserimento + -- ============================================================ + report "=== GRUPPO 1: Inserimento ==="; + + -- 1.0: Insert in lista vuota + clear_ram; + do_reset; + do_op("10", "000001", "10"); -- task_id=1, priority=2 + -- Memoria attesa: [0x01]=1, [1]=0b00000110 = task_id=1,prio=2 + check_mem("1.0 count", 0, "00000001"); + check_mem("1.0 task", 1, "00000110"); -- 000001 & 10 + report "Test 1.0 OK: insert in lista vuota"; + + -- 1.1: Insert con priorità più alta di tutti (va in testa) + clear_ram; + do_reset; + do_op("10", "000010", "10"); -- id=2, prio=2 + do_op("10", "000011", "10"); -- id=3, prio=2 + do_op("10", "000001", "00"); -- id=1, prio=0 -> deve andare in testa + -- Atteso: [1]=id1,prio0 [2]=id2,prio2 [3]=id3,prio2 + check_mem("1.1 count", 0, "00000011"); + check_mem("1.1 pos1", 1, "00000100"); -- 000001 & 00 + check_mem("1.1 pos2", 2, "00001010"); -- 000010 & 10 + check_mem("1.1 pos3", 3, "00001110"); -- 000011 & 10 + report "Test 1.1 OK: insert con priorità massima in testa"; + + -- 1.2: Insert con priorità più bassa di tutti (va in fondo) + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "000010", "01"); -- id=2, prio=1 + do_op("10", "000011", "11"); -- id=3, prio=3 -> deve andare in fondo + -- Atteso: [1]=id1,prio0 [2]=id2,prio1 [3]=id3,prio3 + check_mem("1.2 count", 0, "00000011"); + check_mem("1.2 pos1", 1, "00000100"); -- 000001 & 00 + check_mem("1.2 pos2", 2, "00001001"); -- 000010 & 01 + check_mem("1.2 pos3", 3, "00001111"); -- 000011 & 11 + report "Test 1.2 OK: insert con priorità minima in fondo"; + + -- 1.3: Insert con priorità uguale -> va in CODA agli uguali + clear_ram; + do_reset; + do_op("10", "000001", "01"); -- id=1, prio=1 + do_op("10", "000010", "01"); -- id=2, prio=1 + do_op("10", "000011", "01"); -- id=3, prio=1 -> va dopo id=2 + -- Atteso: [1]=id1,prio1 [2]=id2,prio1 [3]=id3,prio1 + check_mem("1.3 count", 0, "00000011"); + check_mem("1.3 pos1", 1, "00000101"); -- 000001 & 01 + check_mem("1.3 pos2", 2, "00001001"); -- 000010 & 01 + check_mem("1.3 pos3", 3, "00001101"); -- 000011 & 01 + report "Test 1.3 OK: insert stesso prio -> va in coda agli uguali"; + + -- 1.4: Insert con tutti task stessa priorità -> sempre in fondo + clear_ram; + do_reset; + do_op("10", "000001", "10"); + do_op("10", "000010", "10"); + do_op("10", "000011", "10"); + do_op("10", "000100", "10"); -- sempre in fondo + check_mem("1.4 count", 0, "00000100"); + check_mem("1.4 pos1", 1, "00000110"); -- id=1, prio=2 + check_mem("1.4 pos2", 2, "00001010"); -- id=2, prio=2 + check_mem("1.4 pos3", 3, "00001110"); -- id=3, prio=2 + check_mem("1.4 pos4", 4, "00010010"); -- id=4, prio=2 + report "Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo"; + + -- 1.5: Insert in lista piena (63 task) -> operazione ignorata + -- Riempiamo la lista con 63 task (ID da 1 a 63, tutti prio=01) + clear_ram; + do_reset; + fill_list(63, 1, "01"); + check_mem("1.5 count-pre", 0, "00111111"); -- 63 task + check_mem("1.5 first-pre", 1, "00000101"); -- id=1, prio=1 + check_mem("1.5 last-pre", 63, "11111101"); -- id=63, prio=1 + -- Tentiamo un inserimento aggiuntivo (deve essere ignorato) + do_op("10", "000000", "00"); -- id=0 sarebbe errore, ma la lista è piena + -- NB: id=0 non può esistere per specifica, ma qui verifichiamo solo + -- che il count rimanga 63 e la memoria non cambi + check_mem("1.5 count-post", 0, "00111111"); -- ancora 63 + check_mem("1.5 pos64", 64, "00000000"); -- nessuna scrittura oltre il limite + report "Test 1.5 OK: insert in lista piena ignorato"; + + -- ============================================================ + -- GRUPPO 2: OP=01 - Rimozione + -- ============================================================ + report "=== GRUPPO 2: Rimozione ==="; + + -- 2.0: Rimozione da lista vuota -> o_task_id = 000000 + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.0 empty-remove", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.0 count", 0, "00000000"); + report "Test 2.0 OK: rimozione da lista vuota -> o_task_id=0"; + + -- 2.1: Rimozione con un solo task -> lista diventa vuota + clear_ram; + do_reset; + do_op("10", "000101", "01"); -- inserisce id=5, prio=1 + check_mem("2.1 pre-count", 0, "00000001"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.1 single-remove", "000101"); -- deve restituire id=5 + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.1 post-count", 0, "00000000"); -- lista vuota + report "Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto"; + + -- 2.2: Rimozione da lista con tutti task alla stessa priorità + -- -> rimuove il primo in ordine d'inserimento (FIFO tra pari priorità) + clear_ram; + do_reset; + do_op("10", "000001", "10"); -- id=1 + do_op("10", "000010", "10"); -- id=2 + do_op("10", "000011", "10"); -- id=3 + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.2 same-prio-remove", "000001"); -- deve restituire id=1 (primo inserito) + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.2 count", 0, "00000010"); + check_mem("2.2 pos1", 1, "00001010"); -- id=2 ora in prima posizione + check_mem("2.2 pos2", 2, "00001110"); -- id=3 + report "Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato"; + + -- ============================================================ + -- GRUPPO 3: OP=00 - Decremento priorità + -- ============================================================ + report "=== GRUPPO 3: Decremento priorità ==="; + + -- 3.0: Decremento con lista vuota -> nessun crash + clear_ram; + do_reset; + do_op("00", "000000", "00"); -- decremento su lista vuota + check_mem("3.0 count", 0, "00000000"); -- invariato + report "Test 3.0 OK: decremento su lista vuota"; + + -- 3.1: Saturazione: task a priorità 3 restano a 3 + clear_ram; + do_reset; + do_op("10", "000001", "01"); -- id=1, prio=1 + do_op("10", "000010", "11"); -- id=2, prio=3 (già al minimo gerarchico) + do_op("00", "000000", "00"); -- decremento + -- id=1: 1->2 id=2: 3->3 (satura) + check_mem("3.1 count", 0, "00000010"); + check_mem("3.1 pos1", 1, "00000110"); -- id=1, prio=2 + check_mem("3.1 pos2", 2, "00001011"); -- id=2, prio=3 (saturato) + report "Test 3.1 OK: saturazione a priorità 3"; + + -- 3.2: Lista con TUTTI i task già a priorità 3 -> nessuna modifica dei valori + clear_ram; + do_reset; + do_op("10", "000001", "11"); + do_op("10", "000010", "11"); + do_op("10", "000011", "11"); + do_op("00", "000000", "00"); -- decremento: tutti saturano a 3 + check_mem("3.2 count", 0, "00000011"); + check_mem("3.2 pos1", 1, "00000111"); -- id=1, prio=3 (invariato) + check_mem("3.2 pos2", 2, "00001011"); -- id=2, prio=3 + check_mem("3.2 pos3", 3, "00001111"); -- id=3, prio=3 + report "Test 3.2 OK: tutti a prio 3 -> nessuna modifica"; + + -- 3.3: Mix priorità 2 e 3 dopo decremento: + -- i "nuovi 3" (ex-2) vengono PRIMA dei "vecchi 3" + -- (nessun riordino, basta modificare i bit di priorità) + clear_ram; + do_reset; + do_op("10", "000001", "10"); -- id=1, prio=2 -> diventa 3 (nuovo 3) + do_op("10", "000010", "10"); -- id=2, prio=2 -> diventa 3 (nuovo 3) + do_op("10", "000011", "11"); -- id=3, prio=3 -> resta 3 (vecchio 3) + do_op("10", "000100", "11"); -- id=4, prio=3 -> resta 3 (vecchio 3) + do_op("00", "000000", "00"); -- decremento + -- Dopo: ordine invariato, id=1 e id=2 prima di id=3 e id=4 + -- tutti con prio=3 nei bit, ma ordine fisico preservato + check_mem("3.3 count", 0, "00000100"); + check_mem("3.3 pos1", 1, "00000111"); -- id=1, prio=3 (ex-2) + check_mem("3.3 pos2", 2, "00001011"); -- id=2, prio=3 (ex-2) + check_mem("3.3 pos3", 3, "00001111"); -- id=3, prio=3 (vecchio) + check_mem("3.3 pos4", 4, "00010011"); -- id=4, prio=3 (vecchio) + report "Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)"; + + -- ============================================================ + -- GRUPPO 4: OP=11 - Svuota lista + -- ============================================================ + report "=== GRUPPO 4: Svuota lista ==="; + + -- 4.0: Svuota lista popolata -> addr 0 = 0 + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + do_op("10", "000011", "10"); + do_op("11", "000000", "00"); -- svuota + check_mem("4.0 count", 0, "00000000"); + report "Test 4.0 OK: svuota lista popolata"; + + -- 4.1: Svuota lista già vuota -> addr 0 rimane 0, nessun crash + clear_ram; + do_reset; + do_op("11", "000000", "00"); + check_mem("4.1 count", 0, "00000000"); + report "Test 4.1 OK: svuota lista già vuota"; + + -- 4.2: Svuota poi rimuovi -> o_task_id = 000000 + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("11", "000000", "00"); -- svuota + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("4.2 remove-after-clear", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 4.2 OK: svuota poi rimozione -> o_task_id=0"; + + -- 4.3: Svuota poi decrementa -> nessun effetto + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("11", "000000", "00"); -- svuota + do_op("00", "000000", "00"); -- decremento su lista vuota + check_mem("4.3 count", 0, "00000000"); + report "Test 4.3 OK: svuota poi decrementa -> nessun effetto"; + + -- ============================================================ + -- GRUPPO 5: Sequenze composite + -- ============================================================ + report "=== GRUPPO 5: Sequenze composite ==="; + + -- 5.0: Insert -> Decremento -> Rimozione: verifica ID estratto + -- Inseriamo: id=10 prio=0, id=20 prio=1, id=30 prio=2 + -- Decrementiamo: id=10 prio=1, id=20 prio=2, id=30 prio=3 + -- Rimuoviamo: deve uscire id=10 (ora ha prio=1, è il primo) + clear_ram; + do_reset; + do_op("10", "001010", "00"); -- id=10, prio=0 + do_op("10", "010100", "01"); -- id=20, prio=1 + do_op("10", "011110", "10"); -- id=30, prio=2 + do_op("00", "000000", "00"); -- decremento + check_mem("5.0 after-dec pos1", 1, "00101001"); -- id=10, prio=1 + check_mem("5.0 after-dec pos2", 2, "01010010"); -- id=20, prio=2 + check_mem("5.0 after-dec pos3", 3, "01111011"); -- id=30, prio=3 + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("5.0 remove-after-dec", "001010"); -- id=10 + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("5.0 count", 0, "00000010"); + check_mem("5.0 pos1", 1, "01010010"); -- id=20, prio=2 + check_mem("5.0 pos2", 2, "01111011"); -- id=30, prio=3 + report "Test 5.0 OK: insert->dec->remove, ID estratto corretto"; + + -- 5.1: Sequenza con priorità miste -> verifica ordinamento completo + -- id=5 prio=3, id=3 prio=1, id=7 prio=2, id=1 prio=0, id=9 prio=1 + -- Ordine atteso: id=1(p0), id=3(p1), id=9(p1), id=7(p2), id=5(p3) + clear_ram; + do_reset; + do_op("10", "000101", "11"); -- id=5, prio=3 + do_op("10", "000011", "01"); -- id=3, prio=1 + do_op("10", "000111", "10"); -- id=7, prio=2 + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "001001", "01"); -- id=9, prio=1 + check_mem("5.1 count", 0, "00000101"); + check_mem("5.1 pos1", 1, "00000100"); -- id=1, prio=0 + check_mem("5.1 pos2", 2, "00001101"); -- id=3, prio=1 + check_mem("5.1 pos3", 3, "00100101"); -- id=9, prio=1 + check_mem("5.1 pos4", 4, "00011110"); -- id=7, prio=2 + check_mem("5.1 pos5", 5, "00010111"); -- id=5, prio=3 + report "Test 5.1 OK: ordinamento completo con priorità miste"; + + -- ============================================================ + -- Fine + -- ============================================================ + assert false + report "======================================" & LF + & " Tutti i test edge case sono PASSATI " & LF + & "======================================" + severity failure; + + end process; + +end architecture; \ No newline at end of file diff --git a/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd b/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd new file mode 100644 index 0000000..98c8e9c --- /dev/null +++ b/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd @@ -0,0 +1,1620 @@ +-- ============================================================ +-- TESTBENCH EDGE CASES (ESTESO) - Progetto Reti Logiche 2025/2026 +-- ============================================================ +-- Copre i seguenti gruppi di test: +-- +-- GRUPPO 0: Reset e inizializzazione +-- 0.0 Reset -> addr 0 = 0, DONE = 1 durante reset poi torna 0 +-- 0.1 Reset mentre operazione in corso (START=1) +-- +-- GRUPPO 1: OP=10 - Inserimento +-- 1.0 Insert in lista vuota +-- 1.1 Insert con priorità più alta di tutti (va in testa) +-- 1.2 Insert con priorità più bassa di tutti (va in fondo) +-- 1.3 Insert con priorità uguale -> va in CODA agli uguali +-- 1.4 Insert con tutti i task alla stessa priorità -> sempre in fondo +-- 1.5 Insert con ID duplicato -> operazione ignorata +-- +-- GRUPPO 2: OP=01 - Rimozione +-- 2.0 Rimozione da lista vuota -> o_task_id = 000000 +-- 2.1 Rimozione con un solo task -> lista diventa vuota +-- 2.2 Rimozione da lista con tutti task alla stessa priorità +-- +-- GRUPPO 3: OP=00 - Decremento priorità +-- 3.0 Decremento con lista vuota -> nessuna scrittura, no crash +-- 3.1 Saturazione: task a priorità 3 restano a 3 +-- 3.2 Lista con TUTTI i task già a priorità 3 -> nessuna modifica +-- 3.3 Mix priorità 2 e 3: i "nuovi 3" (ex-2) vengono PRIMA dei "vecchi 3" +-- +-- GRUPPO 4: OP=11 - Svuota lista +-- 4.0 Svuota lista popolata -> addr 0 = 0 +-- 4.1 Svuota lista già vuota -> addr 0 rimane 0 +-- 4.2 Svuota poi rimuovi -> o_task_id = 000000 +-- 4.3 Svuota poi decrementa -> nessun effetto +-- +-- GRUPPO 5: Sequenze composite (originali) +-- 5.0 Insert -> Decremento -> Rimozione: verifica ID estratto corretto +-- 5.1 Sequenza di insert con priorità miste -> verifica ordinamento completo +-- +-- ============================================================ +-- NUOVI GRUPPI (casi limite mancanti): +-- ============================================================ +-- +-- GRUPPO 6: Rimozione multipla e ordinamento +-- 6.0 Rimozione multipla consecutiva fino a lista vuota +-- (lista con priorità miste, verifica ordine esatto degli ID estratti +-- e che il contatore scenda correttamente a ogni step) +-- 6.1 Rimozione da lista con priorità miste -> viene rimosso SEMPRE +-- il task in posizione 1 (indirizzo 1), non quello con prio numericamente +-- più bassa +-- +-- GRUPPO 7: Decremento ripetuto +-- 7.0 Decremento applicato più volte -> saturazione progressiva +-- (prio 0->1->2->3->3->3, verifica a ogni step) +-- 7.1 Decremento su lista con un solo task (edge case singolo) +-- 7.2 Decrementa -> Svuota (ordine inverso rispetto a 4.3) +-- +-- GRUPPO 8: Insert dopo rimozione parziale +-- 8.0 Insert -> Rimozione parziale -> Insert -> verifica ordinamento completo +-- 8.1 Insert con priority=0 in lista con tutti prio=0 +-- (il nuovo va sempre in fondo, indipendentemente da prio uguale) +-- 8.2 Insert con priority=3 in lista con tutti prio=3 +-- (simmetrico: il nuovo va sempre in fondo) +-- +-- GRUPPO 9: Verifica o_task_id per OP != 01 +-- 9.0 OP=10 (insert) -> o_task_id deve essere 0x00 quando DONE=1 +-- 9.1 OP=00 (decremento) -> o_task_id deve essere 0x00 quando DONE=1 +-- 9.2 OP=11 (svuota) -> o_task_id deve essere 0x00 quando DONE=1 +-- 9.3 OP=01 lista vuota -> o_task_id deve essere 0x00 quando DONE=1 +-- +-- GRUPPO 10: Protocollo START-DONE e reset +-- 10.0 Operazione immediata al primo fronte dopo DONE->0 post-reset +-- (nessun ciclo di margine tra fine reset e primo START) +-- 10.1 Sequenza lunga stress: insert x8 -> dec x3 -> remove x4 +-- -> insert x3 -> remove fino a vuota (verifica coerenza totale) +-- 10.2 Reset dopo OP=11 (svuota -> reset -> verifica lista vuota) +-- +-- GRUPPO 11: OP=10 con ID=0 (condizione di errore da specifica) +-- 11.0 Insert ID=0 in lista vuota -> ignorato, DONE arriva comunque +-- 11.1 Insert ID=0 in lista popolata (prio alta e bassa) -> lista invariata +-- +-- GRUPPO 12: Capacita' massima (63 task, errata del 24.02.2026) +-- 12.0 Insert di TUTTI i 63 ID possibili, verifica completa della memoria +-- 12.1 Inserimenti oltre il 63esimo (ogni ID e' duplicato) -> ignorati +-- 12.2 Drain completo: 63 pop con verifica dell'ordine di estrazione +-- +-- GRUPPO 13: Memoria stale e duplicati ai bordi della lista +-- 13.0 Re-insert di ID appena rimosso (copia stale oltre il count) +-- 13.1 Duplicato in PRIMA posizione -> ignorato +-- 13.2 Duplicato in ULTIMA posizione -> ignorato +-- 13.3 Clear poi re-insert dello stesso ID (cella stale) -> deve riuscire +-- +-- GRUPPO 14: Reset asincrono avanzato (spec: RESET in qualsiasi momento) +-- 14.0 Reset a meta' dello shift di OP=01 +-- 14.1 Reset nel ciclo di scrittura del count (fine OP=01) +-- 14.2 Reset a meta' della scansione di OP=00 +-- 14.3 Reset mentre DONE=1 +-- 14.4 Reset corto (7 ns, non allineato al clock) +-- +-- GRUPPO 15: Protocollo START-DONE con abbassamento lento di START +-- 15.0 Pop con START alto 1 ciclo extra -> niente doppio pop +-- 15.1 Age con START alto 1 ciclo extra -> niente doppio age +-- 15.2 Insert con START alto 2 cicli extra +-- NOTA: il gruppo 15 FALLISCE con l'RTL attuale finche' non viene +-- aggiunto uno stato S_DONE che attende START=0 prima di tornare in IDLE. +-- +-- MONITOR concorrente: nessuna scrittura in memoria quando il modulo +-- dovrebbe essere idle (RST=0, START=0, DONE=0). +-- +-- ============================================================ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity project_tb_edge is +end project_tb_edge; + +architecture project_tb_edge_arch of project_tb_edge is + + constant CLOCK_PERIOD : time := 20 ns; + signal tb_clk : std_logic := '0'; + signal tb_rst : std_logic; + signal tb_start : std_logic; + signal tb_done : std_logic; + signal tb_o_task_id : std_logic_vector(5 downto 0); + signal tb_task_priority : std_logic_vector(1 downto 0); + signal tb_op : std_logic_vector(1 downto 0); + signal tb_i_task_id : std_logic_vector(5 downto 0); + + signal exc_o_mem_addr : std_logic_vector(15 downto 0); + signal exc_o_mem_data : std_logic_vector(7 downto 0); + signal exc_o_mem_we : std_logic; + signal exc_o_mem_en : std_logic; + + signal init_o_mem_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal init_o_mem_data : std_logic_vector(7 downto 0) := (others => '0'); + signal init_o_mem_we : std_logic := '0'; + signal init_o_mem_en : std_logic := '0'; + + signal tb_o_mem_addr : std_logic_vector(15 downto 0); + signal tb_o_mem_data : std_logic_vector(7 downto 0); + signal tb_o_mem_we : std_logic; + signal tb_o_mem_en : std_logic; + signal tb_i_mem_data : std_logic_vector(7 downto 0); + + signal memory_control : std_logic := '0'; + + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type := (others => "00000000"); + + -- -------------------------------------------------------- + -- Utility: tipo per verifiche memoria + -- -------------------------------------------------------- + type mem_check_t is record + addr : integer; + expected : std_logic_vector(7 downto 0); + end record; + + component project_reti_logiche is + port ( + i_clk : in std_logic; + i_rst : in std_logic; + i_start : in std_logic; + i_task_id : in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op : in std_logic_vector(1 downto 0); + o_done : out std_logic; + o_task_id : out std_logic_vector(5 downto 0); + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we : out std_logic; + o_mem_en : out std_logic + ); + end component project_reti_logiche; + +begin + + UUT : project_reti_logiche + port map ( + i_clk => tb_clk, + i_rst => tb_rst, + i_start => tb_start, + i_task_id => tb_i_task_id, + i_task_priority => tb_task_priority, + i_op => tb_op, + o_done => tb_done, + o_task_id => tb_o_task_id, + o_mem_addr => exc_o_mem_addr, + i_mem_data => tb_i_mem_data, + o_mem_data => exc_o_mem_data, + o_mem_we => exc_o_mem_we, + o_mem_en => exc_o_mem_en + ); + + -- Clock + tb_clk <= not tb_clk after CLOCK_PERIOD / 2; + + -- Memoria + MEM : process (tb_clk) + begin + if tb_clk'event and tb_clk = '1' then + if tb_o_mem_en = '1' then + if tb_o_mem_we = '1' then + RAM(to_integer(unsigned(tb_o_mem_addr))) <= tb_o_mem_data after 1 ns; + tb_i_mem_data <= tb_o_mem_data after 1 ns; + else + tb_i_mem_data <= RAM(to_integer(unsigned(tb_o_mem_addr))) after 1 ns; + end if; + end if; + end if; + end process; + + -- Mux memoria: init_o / exc_o + memory_signal_swapper : process (memory_control, + init_o_mem_addr, init_o_mem_data, init_o_mem_en, init_o_mem_we, + exc_o_mem_addr, exc_o_mem_data, exc_o_mem_en, exc_o_mem_we) + begin + tb_o_mem_addr <= init_o_mem_addr; + tb_o_mem_data <= init_o_mem_data; + tb_o_mem_en <= init_o_mem_en; + tb_o_mem_we <= init_o_mem_we; + if memory_control = '1' then + tb_o_mem_addr <= exc_o_mem_addr; + tb_o_mem_data <= exc_o_mem_data; + tb_o_mem_en <= exc_o_mem_en; + tb_o_mem_we <= exc_o_mem_we; + end if; + end process; + + -- ============================================================ + -- MONITOR: scritture spurie + -- Se il modulo e' idle (RST=0, START=0, DONE=0) non deve scrivere + -- in memoria. Una scrittura qui indica o una ri-esecuzione indebita + -- dell'operazione (protocollo START-DONE violato) o segnali di + -- controllo memoria non azzerati. + -- Campionato sul fronte di discesa per evitare race con i registri. + -- ============================================================ + protocol_monitor : process (tb_clk) + begin + if falling_edge(tb_clk) then + if tb_rst = '0' and tb_done = '0' and tb_start = '0' then + assert not (exc_o_mem_en = '1' and exc_o_mem_we = '1') + report "FAIL [MONITOR] scrittura in memoria con modulo idle " + & "(RST=0, START=0, DONE=0): possibile ri-esecuzione " + & "dell'operazione o segnali di scrittura spuri" + severity failure; + end if; + end if; + end process; + + -- ============================================================ + -- Processo principale di test + -- ============================================================ + main_test : process + + -- -------------------------------------------------------- + -- Procedure di supporto + -- -------------------------------------------------------- + + -- Reset del componente (attende DONE=1 durante reset poi DONE=0) + procedure do_reset is + begin + tb_start <= '0'; + tb_rst <= '1'; + wait for 100 ns; + -- DONE deve essere 1 durante il reset (modulo non pronto) + assert tb_done = '1' + report "FAIL: DONE dovrebbe essere 1 durante reset" + severity failure; + tb_rst <= '0'; + -- Attende che il modulo completi l'inizializzazione (DONE->0) + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + end procedure; + + -- Lancia un'operazione e attende DONE=1 + procedure do_op ( + op : std_logic_vector(1 downto 0); + task_id : std_logic_vector(5 downto 0); + priority : std_logic_vector(1 downto 0) + ) is + begin + wait until falling_edge(tb_clk); + tb_op <= op; + tb_i_task_id <= task_id; + tb_task_priority <= priority; + tb_start <= '1'; + wait until rising_edge(tb_done); + tb_start <= '0'; + wait until falling_edge(tb_done); + end procedure; + + -- Lancia un'operazione, cattura o_task_id al momento di DONE=1, + -- e restituisce il valore campionato nel segnale out_id + procedure do_op_capture ( + op : std_logic_vector(1 downto 0); + task_id : std_logic_vector(5 downto 0); + priority : std_logic_vector(1 downto 0); + captured : out std_logic_vector(5 downto 0) + ) is + begin + wait until falling_edge(tb_clk); + tb_op <= op; + tb_i_task_id <= task_id; + tb_task_priority <= priority; + tb_start <= '1'; + wait until rising_edge(tb_done); + captured := tb_o_task_id; -- campiona al momento esatto di DONE=1 + tb_start <= '0'; + wait until falling_edge(tb_done); + end procedure; + + -- Verifica un singolo indirizzo di memoria + procedure check_mem ( + step : string; + addr : integer; + expected : std_logic_vector(7 downto 0) + ) is + begin + assert RAM(addr) = expected + report "FAIL [" & step & "] addr=" & integer'image(addr) + & " expected=0x" & integer'image(to_integer(unsigned(expected))) + & " actual=0x" & integer'image(to_integer(unsigned(RAM(addr)))) + severity failure; + end procedure; + + -- Verifica o_task_id (usata dopo do_op_capture) + procedure check_captured_id ( + step : string; + actual : std_logic_vector(5 downto 0); + expected : std_logic_vector(5 downto 0) + ) is + begin + assert actual = expected + report "FAIL [" & step & "] o_task_id expected=" + & integer'image(to_integer(unsigned(expected))) + & " actual=" + & integer'image(to_integer(unsigned(actual))) + severity failure; + end procedure; + + -- Verifica o_task_id (campionato in tempo reale) + procedure check_task_id ( + step : string; + expected : std_logic_vector(5 downto 0) + ) is + begin + assert tb_o_task_id = expected + report "FAIL [" & step & "] o_task_id expected=" + & integer'image(to_integer(unsigned(expected))) + & " actual=" + & integer'image(to_integer(unsigned(tb_o_task_id))) + severity failure; + end procedure; + + -- Azzera la RAM (usato per isolare i gruppi di test) + procedure clear_ram is + begin + memory_control <= '0'; + for i in 0 to 70 loop + init_o_mem_addr <= std_logic_vector(to_unsigned(i, 16)); + init_o_mem_data <= "00000000"; + init_o_mem_en <= '1'; + init_o_mem_we <= '1'; + wait until rising_edge(tb_clk); + end loop; + init_o_mem_en <= '0'; + init_o_mem_we <= '0'; + memory_control <= '1'; + end procedure; + + -- Inserisce N task nella lista + procedure fill_list (n : integer; base_id : integer; prio : std_logic_vector(1 downto 0)) is + begin + for k in 0 to n-1 loop + do_op("10", + std_logic_vector(to_unsigned(base_id + k, 6)), + prio); + end loop; + end procedure; + + -- Variabili locali per catturare il task_id restituito + variable captured_id : std_logic_vector(5 downto 0); + + -- Modello di riferimento per il test a capacita' massima (gruppo 12) + type int_array63_t is array (1 to 63) of integer; + variable exp_id : int_array63_t; + variable exp_prio : int_array63_t; + variable idx : integer; + variable exp_byte : std_logic_vector(7 downto 0); + + begin + -- Inizializzazione segnali + tb_start <= '0'; + tb_rst <= '0'; + tb_op <= "00"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + memory_control <= '1'; + + wait for 50 ns; + + -- ============================================================ + -- GRUPPO 0: Reset e inizializzazione + -- ============================================================ + + -- 0.0: Reset base -> addr 0 deve essere 0, DONE=1 durante reset + report "=== GRUPPO 0: Reset ==="; + memory_control <= '0'; + tb_rst <= '1'; + wait for 100 ns; + assert tb_done = '1' + report "FAIL [0.0] DONE deve essere 1 durante reset" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("0.0 reset-addr0", 0, "00000000"); + memory_control <= '1'; + report "Test 0.0 OK: reset base"; + + -- 0.1: Reset mentre operazione in corso + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= "000001"; + tb_task_priority <= "01"; + tb_start <= '1'; + wait until rising_edge(tb_clk); + wait until rising_edge(tb_clk); + tb_rst <= '1'; + tb_start <= '0'; + wait for 50 ns; + assert tb_done = '1' + report "FAIL [0.1] DONE deve essere 1 durante reset asincrono" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("0.1 reset-async", 0, "00000000"); + report "Test 0.1 OK: reset asincrono durante operazione"; + + -- ============================================================ + -- GRUPPO 1: OP=10 - Inserimento + -- ============================================================ + report "=== GRUPPO 1: Inserimento ==="; + + -- 1.0: Insert in lista vuota + clear_ram; + do_reset; + do_op("10", "000001", "10"); + check_mem("1.0 count", 0, "00000001"); + check_mem("1.0 task", 1, "00000110"); + report "Test 1.0 OK: insert in lista vuota"; + + -- 1.1: Insert con priorità più alta di tutti (va in testa) + clear_ram; + do_reset; + do_op("10", "000010", "10"); + do_op("10", "000011", "10"); + do_op("10", "000001", "00"); + check_mem("1.1 count", 0, "00000011"); + check_mem("1.1 pos1", 1, "00000100"); + check_mem("1.1 pos2", 2, "00001010"); + check_mem("1.1 pos3", 3, "00001110"); + report "Test 1.1 OK: insert con priorità massima in testa"; + + -- 1.2: Insert con priorità più bassa di tutti (va in fondo) + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + do_op("10", "000011", "11"); + check_mem("1.2 count", 0, "00000011"); + check_mem("1.2 pos1", 1, "00000100"); + check_mem("1.2 pos2", 2, "00001001"); + check_mem("1.2 pos3", 3, "00001111"); + report "Test 1.2 OK: insert con priorità minima in fondo"; + + -- 1.3: Insert con priorità uguale -> va in CODA agli uguali + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "01"); + do_op("10", "000011", "01"); + check_mem("1.3 count", 0, "00000011"); + check_mem("1.3 pos1", 1, "00000101"); + check_mem("1.3 pos2", 2, "00001001"); + check_mem("1.3 pos3", 3, "00001101"); + report "Test 1.3 OK: insert stesso prio -> va in coda agli uguali"; + + -- 1.4: Insert con tutti task stessa priorità -> sempre in fondo + clear_ram; + do_reset; + do_op("10", "000001", "10"); + do_op("10", "000010", "10"); + do_op("10", "000011", "10"); + do_op("10", "000100", "10"); + check_mem("1.4 count", 0, "00000100"); + check_mem("1.4 pos1", 1, "00000110"); + check_mem("1.4 pos2", 2, "00001010"); + check_mem("1.4 pos3", 3, "00001110"); + check_mem("1.4 pos4", 4, "00010010"); + report "Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo"; + + -- 1.5: Insert con ID duplicato -> operazione ignorata + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "01"); + do_op("10", "000011", "01"); + check_mem("1.5 count-pre", 0, "00000011"); + check_mem("1.5 pos1-pre", 1, "00000101"); + check_mem("1.5 pos2-pre", 2, "00001001"); + check_mem("1.5 pos3-pre", 3, "00001101"); + do_op("10", "000010", "00"); + check_mem("1.5 count-post", 0, "00000011"); + check_mem("1.5 pos1-post", 1, "00000101"); + check_mem("1.5 pos2-post", 2, "00001001"); + check_mem("1.5 pos3-post", 3, "00001101"); + check_mem("1.5 pos4-post", 4, "00000000"); + report "Test 1.5 OK: insert con ID duplicato ignorato"; + + -- ============================================================ + -- GRUPPO 2: OP=01 - Rimozione + -- ============================================================ + report "=== GRUPPO 2: Rimozione ==="; + + -- 2.0: Rimozione da lista vuota -> o_task_id = 000000 + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.0 empty-remove", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.0 count", 0, "00000000"); + report "Test 2.0 OK: rimozione da lista vuota -> o_task_id=0"; + + -- 2.1: Rimozione con un solo task -> lista diventa vuota + clear_ram; + do_reset; + do_op("10", "000101", "01"); + check_mem("2.1 pre-count", 0, "00000001"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.1 single-remove", "000101"); + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.1 post-count", 0, "00000000"); + report "Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto"; + + -- 2.2: Rimozione da lista con tutti task alla stessa priorità -> FIFO + clear_ram; + do_reset; + do_op("10", "000001", "10"); + do_op("10", "000010", "10"); + do_op("10", "000011", "10"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("2.2 same-prio-remove", "000001"); + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("2.2 count", 0, "00000010"); + check_mem("2.2 pos1", 1, "00001010"); + check_mem("2.2 pos2", 2, "00001110"); + report "Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato"; + + -- ============================================================ + -- GRUPPO 3: OP=00 - Decremento priorità + -- ============================================================ + report "=== GRUPPO 3: Decremento priorità ==="; + + -- 3.0: Decremento con lista vuota -> nessun crash + clear_ram; + do_reset; + do_op("00", "000000", "00"); + check_mem("3.0 count", 0, "00000000"); + report "Test 3.0 OK: decremento su lista vuota"; + + -- 3.1: Saturazione: task a priorità 3 restano a 3 + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "11"); + do_op("00", "000000", "00"); + check_mem("3.1 count", 0, "00000010"); + check_mem("3.1 pos1", 1, "00000110"); + check_mem("3.1 pos2", 2, "00001011"); + report "Test 3.1 OK: saturazione a priorità 3"; + + -- 3.2: Lista con TUTTI i task già a priorità 3 -> nessuna modifica + clear_ram; + do_reset; + do_op("10", "000001", "11"); + do_op("10", "000010", "11"); + do_op("10", "000011", "11"); + do_op("00", "000000", "00"); + check_mem("3.2 count", 0, "00000011"); + check_mem("3.2 pos1", 1, "00000111"); + check_mem("3.2 pos2", 2, "00001011"); + check_mem("3.2 pos3", 3, "00001111"); + report "Test 3.2 OK: tutti a prio 3 -> nessuna modifica"; + + -- 3.3: Mix priorità 2 e 3: gli ex-2 precedono gli ex-3 + clear_ram; + do_reset; + do_op("10", "000001", "10"); + do_op("10", "000010", "10"); + do_op("10", "000011", "11"); + do_op("10", "000100", "11"); + do_op("00", "000000", "00"); + check_mem("3.3 count", 0, "00000100"); + check_mem("3.3 pos1", 1, "00000111"); + check_mem("3.3 pos2", 2, "00001011"); + check_mem("3.3 pos3", 3, "00001111"); + check_mem("3.3 pos4", 4, "00010011"); + report "Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)"; + + -- ============================================================ + -- GRUPPO 4: OP=11 - Svuota lista + -- ============================================================ + report "=== GRUPPO 4: Svuota lista ==="; + + -- 4.0: Svuota lista popolata -> addr 0 = 0 + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + do_op("10", "000011", "10"); + do_op("11", "000000", "00"); + check_mem("4.0 count", 0, "00000000"); + report "Test 4.0 OK: svuota lista popolata"; + + -- 4.1: Svuota lista già vuota -> addr 0 rimane 0, nessun crash + clear_ram; + do_reset; + do_op("11", "000000", "00"); + check_mem("4.1 count", 0, "00000000"); + report "Test 4.1 OK: svuota lista già vuota"; + + -- 4.2: Svuota poi rimuovi -> o_task_id = 000000 + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("11", "000000", "00"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("4.2 remove-after-clear", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 4.2 OK: svuota poi rimozione -> o_task_id=0"; + + -- 4.3: Svuota poi decrementa -> nessun effetto + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("11", "000000", "00"); + do_op("00", "000000", "00"); + check_mem("4.3 count", 0, "00000000"); + report "Test 4.3 OK: svuota poi decrementa -> nessun effetto"; + + -- ============================================================ + -- GRUPPO 5: Sequenze composite (originali) + -- ============================================================ + report "=== GRUPPO 5: Sequenze composite ==="; + + -- 5.0: Insert -> Decremento -> Rimozione + clear_ram; + do_reset; + do_op("10", "001010", "00"); + do_op("10", "010100", "01"); + do_op("10", "011110", "10"); + do_op("00", "000000", "00"); + check_mem("5.0 after-dec pos1", 1, "00101001"); + check_mem("5.0 after-dec pos2", 2, "01010010"); + check_mem("5.0 after-dec pos3", 3, "01111011"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("5.0 remove-after-dec", "001010"); + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("5.0 count", 0, "00000010"); + check_mem("5.0 pos1", 1, "01010010"); + check_mem("5.0 pos2", 2, "01111011"); + report "Test 5.0 OK: insert->dec->remove, ID estratto corretto"; + + -- 5.1: Ordinamento completo con priorità miste + clear_ram; + do_reset; + do_op("10", "000101", "11"); + do_op("10", "000011", "01"); + do_op("10", "000111", "10"); + do_op("10", "000001", "00"); + do_op("10", "001001", "01"); + check_mem("5.1 count", 0, "00000101"); + check_mem("5.1 pos1", 1, "00000100"); + check_mem("5.1 pos2", 2, "00001101"); + check_mem("5.1 pos3", 3, "00100101"); + check_mem("5.1 pos4", 4, "00011110"); + check_mem("5.1 pos5", 5, "00010111"); + report "Test 5.1 OK: ordinamento completo con priorità miste"; + + + -- ============================================================ + -- GRUPPO 6: Rimozione multipla e ordinamento + -- ============================================================ + report "=== GRUPPO 6: Rimozione multipla e ordinamento ==="; + + -- 6.0: Rimozione multipla consecutiva fino a lista vuota + -- + -- Lista inserita: id=1 prio=0, id=2 prio=1, id=3 prio=1, id=4 prio=2 + -- Ordine atteso di estrazione: 1, 2, 3, 4 (la rimozione prende sempre pos 1) + -- Dopo ogni rimozione verifichiamo: l'ID estratto, il count e la struttura + -- della lista residua. + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "000010", "01"); -- id=2, prio=1 + do_op("10", "000011", "01"); -- id=3, prio=1 + do_op("10", "000100", "10"); -- id=4, prio=2 + check_mem("6.0 init-count", 0, "00000100"); + + -- Prima rimozione: deve uscire id=1 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.0 remove1-id", captured_id, "000001"); + check_mem("6.0 after-rem1 count", 0, "00000011"); + check_mem("6.0 after-rem1 pos1", 1, "00001001"); -- id=2, prio=1 + check_mem("6.0 after-rem1 pos2", 2, "00001101"); -- id=3, prio=1 + check_mem("6.0 after-rem1 pos3", 3, "00010010"); -- id=4, prio=2 + + -- Seconda rimozione: deve uscire id=2 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.0 remove2-id", captured_id, "000010"); + check_mem("6.0 after-rem2 count", 0, "00000010"); + check_mem("6.0 after-rem2 pos1", 1, "00001101"); -- id=3, prio=1 + check_mem("6.0 after-rem2 pos2", 2, "00010010"); -- id=4, prio=2 + + -- Terza rimozione: deve uscire id=3 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.0 remove3-id", captured_id, "000011"); + check_mem("6.0 after-rem3 count", 0, "00000001"); + check_mem("6.0 after-rem3 pos1", 1, "00010010"); -- id=4, prio=2 + + -- Quarta rimozione: deve uscire id=4, lista diventa vuota + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.0 remove4-id", captured_id, "000100"); + check_mem("6.0 after-rem4 count", 0, "00000000"); + + -- Quinta rimozione su lista vuota: deve restituire id=0 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.0 remove5-empty", captured_id, "000000"); + check_mem("6.0 after-rem5 count", 0, "00000000"); + + report "Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota"; + + -- 6.1: Rimozione da lista con priorità miste + -- + -- SCOPO: verificare che OP=01 rimuova SEMPRE il task in posizione 1 (addr 1), + -- NON il task con il valore di priorità numericamente più basso. + -- In questo test, il task in posizione 1 ha prio=2 (non la "migliore"), + -- perché la lista è stata costruita in un ordine specifico tramite inserimenti + -- successivi con decremento. + -- + -- Costruiamo: id=5 prio=1, id=7 prio=3, poi decrementiamo. + -- Dopo il decremento: id=5 diventa prio=2, id=7 resta prio=3 + -- La lista è: [pos1: id=5 prio=2] [pos2: id=7 prio=3] + -- La rimozione deve estrarre id=5 (posizione 1), non id=7. + clear_ram; + do_reset; + do_op("10", "000101", "01"); -- id=5, prio=1 + do_op("10", "000111", "11"); -- id=7, prio=3 + -- Lista: [id=5,p1] [id=7,p3] + do_op("00", "000000", "00"); -- decremento + -- Lista dopo dec: [id=5,p2] [id=7,p3] + check_mem("6.1 pre-pos1", 1, "00010110"); -- id=5, prio=2 + check_mem("6.1 pre-pos2", 2, "00011111"); -- id=7, prio=3 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("6.1 remove-from-mixed", captured_id, "000101"); -- deve uscire id=5 (pos 1) + check_mem("6.1 post-count", 0, "00000001"); + check_mem("6.1 post-pos1", 1, "00011111"); -- rimane id=7 + report "Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1"; + + + -- ============================================================ + -- GRUPPO 7: Decremento ripetuto + -- ============================================================ + report "=== GRUPPO 7: Decremento ripetuto ==="; + + -- 7.0: Decremento applicato 4 volte su un task partendo da prio=0 + -- Sequenza attesa: 0 -> 1 -> 2 -> 3 -> 3 (satura) + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + check_mem("7.0 init", 1, "00000100"); -- id=1, prio=0 + + do_op("00", "000000", "00"); -- 1° decremento: prio 0->1 + check_mem("7.0 dec1", 1, "00000101"); -- id=1, prio=1 + check_mem("7.0 dec1-count", 0, "00000001"); + + do_op("00", "000000", "00"); -- 2° decremento: prio 1->2 + check_mem("7.0 dec2", 1, "00000110"); -- id=1, prio=2 + + do_op("00", "000000", "00"); -- 3° decremento: prio 2->3 + check_mem("7.0 dec3", 1, "00000111"); -- id=1, prio=3 + + do_op("00", "000000", "00"); -- 4° decremento: prio 3->3 (saturazione) + check_mem("7.0 dec4-sat", 1, "00000111"); -- id=1, prio=3 (invariato) + check_mem("7.0 dec4-count", 0, "00000001"); -- count invariato + + do_op("00", "000000", "00"); -- 5° decremento: ancora saturazione + check_mem("7.0 dec5-sat", 1, "00000111"); -- id=1, prio=3 (ancora invariato) + report "Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3"; + + -- 7.0b: Decremento ripetuto su lista con task a priorità miste + -- Verifica che ogni task segua la propria traiettoria di saturazione + -- indipendentemente dagli altri + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "000010", "01"); -- id=2, prio=1 + do_op("10", "000011", "10"); -- id=3, prio=2 + do_op("10", "000100", "11"); -- id=4, prio=3 + + do_op("00", "000000", "00"); -- 1° decremento + -- id=1: 0->1, id=2: 1->2, id=3: 2->3, id=4: 3->3 (sat) + -- ATTENZIONE: dopo il decremento l'ORDINE rimane invariato (no riordino) + -- quindi la struttura fisica della lista NON cambia posizione + check_mem("7.0b dec1-pos1", 1, "00000101"); -- id=1, prio=1 + check_mem("7.0b dec1-pos2", 2, "00001010"); -- id=2, prio=2 + check_mem("7.0b dec1-pos3", 3, "00001111"); -- id=3, prio=3 + check_mem("7.0b dec1-pos4", 4, "00010011"); -- id=4, prio=3 (saturato) + + do_op("00", "000000", "00"); -- 2° decremento + -- id=1: 1->2, id=2: 2->3, id=3: 3->3 (sat), id=4: 3->3 (sat) + check_mem("7.0b dec2-pos1", 1, "00000110"); -- id=1, prio=2 + check_mem("7.0b dec2-pos2", 2, "00001011"); -- id=2, prio=3 + check_mem("7.0b dec2-pos3", 3, "00001111"); -- id=3, prio=3 (saturato) + check_mem("7.0b dec2-pos4", 4, "00010011"); -- id=4, prio=3 (saturato) + + do_op("00", "000000", "00"); -- 3° decremento: tutti saturano a 3 + check_mem("7.0b dec3-pos1", 1, "00000111"); -- id=1, prio=3 + check_mem("7.0b dec3-pos2", 2, "00001011"); -- id=2, prio=3 + check_mem("7.0b dec3-pos3", 3, "00001111"); -- id=3, prio=3 + check_mem("7.0b dec3-pos4", 4, "00010011"); -- id=4, prio=3 + report "Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente"; + + -- 7.1: Decremento su lista con un solo task + clear_ram; + do_reset; + do_op("10", "001111", "01"); -- id=15, prio=1 + do_op("00", "000000", "00"); -- decremento + check_mem("7.1 count", 0, "00000001"); + check_mem("7.1 pos1", 1, "00111110"); -- id=15, prio=2 + do_op("00", "000000", "00"); -- secondo decremento + check_mem("7.1 pos1b", 1, "00111111"); -- id=15, prio=3 + do_op("00", "000000", "00"); -- terzo decremento: satura + check_mem("7.1 pos1c", 1, "00111111"); -- id=15, prio=3 (invariato) + report "Test 7.1 OK: decremento su lista con un solo task"; + + -- 7.2: Decrementa poi Svuota + -- (ordine inverso rispetto al test 4.3 che fa svuota->decrementa) + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "10"); + do_op("00", "000000", "00"); -- decremento: modifica i task + -- Ora svuotiamo: deve azzerare solo il count + do_op("11", "000000", "00"); + check_mem("7.2 count", 0, "00000000"); + -- Rimozione su lista appena svuotata deve restituire 0 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("7.2 remove-after-clear", captured_id, "000000"); + report "Test 7.2 OK: decrementa -> svuota -> rimozione su vuota"; + + + -- ============================================================ + -- GRUPPO 8: Insert dopo rimozione parziale e casi limite prio 0/3 + -- ============================================================ + report "=== GRUPPO 8: Insert dopo rimozione e casi limite ==="; + + -- 8.0: Insert -> Rimozione parziale -> Insert -> verifica ordinamento + -- + -- Fase 1: inseriamo id=1(p0), id=2(p1), id=3(p2) + -- Fase 2: rimuoviamo 2 volte -> restano: id=2(p1), id=3(p2) + -- Fase 3: inseriamo id=10(p0) e id=20(p2) + -- Risultato atteso: id=10(p0), id=2(p1), id=3(p2), id=20(p2) + -- id=20 va in coda agli elementi con prio=2 (dopo id=3) + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "000010", "01"); -- id=2, prio=1 + do_op("10", "000011", "10"); -- id=3, prio=2 + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.0 rem1", captured_id, "000001"); -- esce id=1 + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.0 rem2", captured_id, "000010"); -- esce id=2 + + -- Ora la lista contiene solo id=3(p2) + check_mem("8.0 mid-count", 0, "00000001"); + check_mem("8.0 mid-pos1", 1, "00001110"); -- id=3, prio=2 + + do_op("10", "001010", "00"); -- id=10, prio=0 -> va in testa + do_op("10", "010100", "10"); -- id=20, prio=2 -> va in coda agli p2 + + check_mem("8.0 final-count", 0, "00000011"); + check_mem("8.0 final-pos1", 1, "00101000"); -- id=10, prio=0 + check_mem("8.0 final-pos2", 2, "00001110"); -- id=3, prio=2 + check_mem("8.0 final-pos3", 3, "01010010"); -- id=20, prio=2 + report "Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto"; + + -- 8.1: Insert con priority=0 in lista dove tutti hanno prio=0 + -- Il nuovo task deve andare sempre IN FONDO (FIFO tra pari priorità) + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, prio=0 + do_op("10", "000010", "00"); -- id=2, prio=0 + do_op("10", "000011", "00"); -- id=3, prio=0 -> va in fondo agli p=0 + check_mem("8.1 count", 0, "00000011"); + check_mem("8.1 pos1", 1, "00000100"); -- id=1, prio=0 + check_mem("8.1 pos2", 2, "00001000"); -- id=2, prio=0 + check_mem("8.1 pos3", 3, "00001100"); -- id=3, prio=0 + -- Rimuoviamo per verificare l'ordine FIFO + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.1 rem1-fifo", captured_id, "000001"); -- esce il primo inserito + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.1 rem2-fifo", captured_id, "000010"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.1 rem3-fifo", captured_id, "000011"); + report "Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato"; + + -- 8.2: Insert con priority=3 in lista dove tutti hanno prio=3 + -- Simmetrico all'8.1: il nuovo va sempre in fondo + clear_ram; + do_reset; + do_op("10", "000001", "11"); -- id=1, prio=3 + do_op("10", "000010", "11"); -- id=2, prio=3 + do_op("10", "000011", "11"); -- id=3, prio=3 -> va in fondo agli p=3 + check_mem("8.2 count", 0, "00000011"); + check_mem("8.2 pos1", 1, "00000111"); -- id=1, prio=3 + check_mem("8.2 pos2", 2, "00001011"); -- id=2, prio=3 + check_mem("8.2 pos3", 3, "00001111"); -- id=3, prio=3 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.2 rem1-fifo", captured_id, "000001"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.2 rem2-fifo", captured_id, "000010"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("8.2 rem3-fifo", captured_id, "000011"); + report "Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato"; + + + -- ============================================================ + -- GRUPPO 9: Verifica o_task_id per OP != 01 + -- ============================================================ + -- La specifica richiede che o_task_id sia valido (= ID estratto) quando + -- DONE=1 per OP=01. Per le altre operazioni, il modulo non estrae nessun + -- task e quindi o_task_id deve valere 0x00 al momento di DONE=1. + -- Questi test verificano che non ci siano "fughe" di valori spuri. + report "=== GRUPPO 9: o_task_id per OP diverso da 01 ==="; + + -- 9.0: OP=10 (insert) -> o_task_id deve essere 000000 a DONE=1 + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= "001111"; -- id=15 + tb_task_priority <= "01"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("9.0 insert-task-id", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1"; + + -- 9.1: OP=00 (decremento) -> o_task_id deve essere 000000 a DONE=1 + clear_ram; + do_reset; + do_op("10", "001111", "01"); -- prima inseriamo qualcosa + wait until falling_edge(tb_clk); + tb_op <= "00"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("9.1 decrement-task-id", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1"; + + -- 9.2: OP=11 (svuota) -> o_task_id deve essere 000000 a DONE=1 + clear_ram; + do_reset; + do_op("10", "001111", "01"); + wait until falling_edge(tb_clk); + tb_op <= "11"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("9.2 clear-task-id", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1"; + + -- 9.3: OP=01 su lista vuota -> o_task_id deve essere 000000 a DONE=1 + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("9.3 remove-empty-task-id", "000000"); + tb_start <= '0'; + wait until falling_edge(tb_done); + report "Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1"; + + + -- ============================================================ + -- GRUPPO 10: Protocollo START-DONE, reset avanzato e stress test + -- ============================================================ + report "=== GRUPPO 10: Protocollo, reset avanzato, stress ==="; + + -- 10.0: Operazione immediata sul primo fronte disponibile dopo DONE->0 + -- Verifica che il modulo accetti START=1 senza cicli di margine + -- tra la fine del reset e l'inizio dell'operazione. + clear_ram; + tb_start <= '0'; + tb_rst <= '1'; + wait for 100 ns; + tb_rst <= '0'; + -- Aspettiamo DONE->0 e SUL FRONTE DI DISCESA STESSO alziamo START + wait until falling_edge(tb_done); + -- Non usiamo wait until falling_edge(tb_clk) extra: start immediato + tb_op <= "10"; + tb_i_task_id <= "000111"; -- id=7 + tb_task_priority <= "01"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("10.0 immediate-start-task-id", "000000"); -- non è OP=01 + tb_start <= '0'; + wait until falling_edge(tb_done); + check_mem("10.0 count", 0, "00000001"); + check_mem("10.0 pos1", 1, "00011101"); -- id=7, prio=1 + report "Test 10.0 OK: operazione immediata dopo DONE->0 post-reset"; + + -- 10.1: Sequenza lunga di stress + -- + -- Fase A: insert 8 task con priorità miste + -- id=1 p=0, id=2 p=2, id=3 p=1, id=4 p=3, + -- id=5 p=0, id=6 p=2, id=7 p=1, id=8 p=3 + -- Ordine atteso dopo tutti gli insert: + -- pos1: id=1 p=0 (00000100) + -- pos2: id=5 p=0 (00010100) + -- pos3: id=3 p=1 (00001101) + -- pos4: id=7 p=1 (00011101) + -- pos5: id=2 p=2 (00001010) + -- pos6: id=6 p=2 (00011010) + -- pos7: id=4 p=3 (00010011) + -- pos8: id=8 p=3 (00100011) + -- + -- Fase B: 3 decrementi + -- Dopo 1° dec: p=0->1, p=1->2, p=2->3, p=3->3(sat) + -- Dopo 2° dec: p=1->2, p=2->3, p=3->3(sat) + -- Dopo 3° dec: p=2->3, p=3->3(sat) -> tutti a prio=3, ordine fisico invariato + -- + -- Fase C: rimuovi 4 task -> escono i primi 4 nell'ordine fisico + -- esc1: id=1, esc2: id=5, esc3: id=3, esc4: id=7 + -- Rimangono: id=2(p3), id=6(p3), id=4(p3), id=8(p3) + -- + -- Fase D: re-insert 3 task: id=10 p=0, id=11 p=1, id=12 p=3 + -- Ordine atteso: id=10(p0), id=11(p1), id=2(p3), id=6(p3), + -- id=4(p3), id=8(p3), id=12(p3) + -- + -- Fase E: rimuovi fino a lista vuota, verifica count=0 + + clear_ram; + do_reset; + + -- Fase A: insert + do_op("10", "000001", "00"); -- id=1, p=0 + do_op("10", "000010", "10"); -- id=2, p=2 + do_op("10", "000011", "01"); -- id=3, p=1 + do_op("10", "000100", "11"); -- id=4, p=3 + do_op("10", "000101", "00"); -- id=5, p=0 + do_op("10", "000110", "10"); -- id=6, p=2 + do_op("10", "000111", "01"); -- id=7, p=1 + do_op("10", "001000", "11"); -- id=8, p=3 + + check_mem("10.1 phaseA count", 0, "00001000"); + check_mem("10.1 phaseA pos1", 1, "00000100"); -- id=1, p=0 + check_mem("10.1 phaseA pos2", 2, "00010100"); -- id=5, p=0 + check_mem("10.1 phaseA pos3", 3, "00001101"); -- id=3, p=1 + check_mem("10.1 phaseA pos4", 4, "00011101"); -- id=7, p=1 + check_mem("10.1 phaseA pos5", 5, "00001010"); -- id=2, p=2 + check_mem("10.1 phaseA pos6", 6, "00011010"); -- id=6, p=2 + check_mem("10.1 phaseA pos7", 7, "00010011"); -- id=4, p=3 + check_mem("10.1 phaseA pos8", 8, "00100011"); -- id=8, p=3 + + -- Fase B: 3 decrementi + do_op("00", "000000", "00"); -- 1° dec + do_op("00", "000000", "00"); -- 2° dec + do_op("00", "000000", "00"); -- 3° dec: tutti a p=3, ordine fisico invariato + + check_mem("10.1 phaseB count", 0, "00001000"); + check_mem("10.1 phaseB pos1", 1, "00000111"); -- id=1, p=3 + check_mem("10.1 phaseB pos2", 2, "00010111"); -- id=5, p=3 + check_mem("10.1 phaseB pos3", 3, "00001111"); -- id=3, p=3 + check_mem("10.1 phaseB pos4", 4, "00011111"); -- id=7, p=3 + check_mem("10.1 phaseB pos5", 5, "00001011"); -- id=2, p=3 + check_mem("10.1 phaseB pos6", 6, "00011011"); -- id=6, p=3 + check_mem("10.1 phaseB pos7", 7, "00010011"); -- id=4, p=3 + check_mem("10.1 phaseB pos8", 8, "00100011"); -- id=8, p=3 + + -- Fase C: rimuovi 4 task + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseC rem1", captured_id, "000001"); -- id=1 + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseC rem2", captured_id, "000101"); -- id=5 + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseC rem3", captured_id, "000011"); -- id=3 + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseC rem4", captured_id, "000111"); -- id=7 + + check_mem("10.1 phaseC count", 0, "00000100"); + check_mem("10.1 phaseC pos1", 1, "00001011"); -- id=2, p=3 + check_mem("10.1 phaseC pos2", 2, "00011011"); -- id=6, p=3 + check_mem("10.1 phaseC pos3", 3, "00010011"); -- id=4, p=3 + check_mem("10.1 phaseC pos4", 4, "00100011"); -- id=8, p=3 + + -- Fase D: re-insert 3 task + do_op("10", "001010", "00"); -- id=10, p=0 -> va in testa (p=0 < p=3) + do_op("10", "001011", "01"); -- id=11, p=1 -> va dopo id=10 (p=1 < p=3) + do_op("10", "001100", "11"); -- id=12, p=3 -> va in coda ai p=3 + + check_mem("10.1 phaseD count", 0, "00000111"); + check_mem("10.1 phaseD pos1", 1, "00101000"); -- id=10, p=0 + check_mem("10.1 phaseD pos2", 2, "00101101"); -- id=11, p=1 + check_mem("10.1 phaseD pos3", 3, "00001011"); -- id=2, p=3 + check_mem("10.1 phaseD pos4", 4, "00011011"); -- id=6, p=3 + check_mem("10.1 phaseD pos5", 5, "00010011"); -- id=4, p=3 + check_mem("10.1 phaseD pos6", 6, "00100011"); -- id=8, p=3 + check_mem("10.1 phaseD pos7", 7, "00110011"); -- id=12, p=3 + + -- Fase E: rimuovi tutti fino a lista vuota verificando count + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem1", captured_id, "001010"); -- id=10 + check_mem("10.1 phaseE cnt1", 0, "00000110"); + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem2", captured_id, "001011"); -- id=11 + check_mem("10.1 phaseE cnt2", 0, "00000101"); + + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem3", captured_id, "000010"); -- id=2 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem4", captured_id, "000110"); -- id=6 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem5", captured_id, "000100"); -- id=4 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem6", captured_id, "001000"); -- id=8 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE rem7", captured_id, "001100"); -- id=12 + + check_mem("10.1 phaseE final-count", 0, "00000000"); -- lista vuota + + -- Tentativo su lista vuota: deve restituire 0 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.1 phaseE empty-rem", captured_id, "000000"); + + report "Test 10.1 OK: stress test completo (insert/dec/remove/re-insert)"; + + -- 10.2: Reset dopo OP=11 (svuota poi reset) + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "10"); + do_op("11", "000000", "00"); -- svuota + check_mem("10.2 pre-reset count", 0, "00000000"); + -- Ora resettiamo + tb_start <= '0'; + tb_rst <= '1'; + wait for 100 ns; + assert tb_done = '1' + report "FAIL [10.2] DONE deve essere 1 durante reset post-svuota" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("10.2 post-reset count", 0, "00000000"); + -- Verifica che il modulo sia operativo: insert e rimozione corretti + do_op("10", "001111", "00"); -- id=15, p=0 + check_mem("10.2 post-reset-insert count", 0, "00000001"); + check_mem("10.2 post-reset-insert pos1", 1, "00111100"); -- id=15, p=0 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("10.2 post-reset-remove", captured_id, "001111"); -- id=15 + check_mem("10.2 post-reset-remove count", 0, "00000000"); + report "Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato"; + + + -- ============================================================ + -- GRUPPO 11: OP=10 con ID=0 (condizione di errore da specifica) + -- ============================================================ + -- La specifica definisce ID_TASK=0 come condizione di errore: + -- un inserimento con ID=0 deve essere ignorato, ma il protocollo + -- START-DONE deve comunque completarsi. + report "=== GRUPPO 11: Insert con ID=0 ==="; + + -- 11.0: Insert ID=0 in lista vuota -> ignorato, DONE arriva comunque + clear_ram; + do_reset; + do_op_capture("10", "000000", "01", captured_id); + check_captured_id("11.0 id0-task-id", captured_id, "000000"); + check_mem("11.0 count", 0, "00000000"); + check_mem("11.0 pos1", 1, "00000000"); + report "Test 11.0 OK: insert ID=0 su lista vuota ignorato"; + + -- 11.1: Insert ID=0 in lista popolata -> lista invariata + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, p=0 + do_op("10", "000010", "01"); -- id=2, p=1 + do_op("10", "000000", "00"); -- ID=0, prio massima: NON deve andare in testa + do_op("10", "000000", "11"); -- ID=0, prio minima: NON deve andare in coda + check_mem("11.1 count", 0, "00000010"); + check_mem("11.1 pos1", 1, "00000100"); -- id=1, p=0 + check_mem("11.1 pos2", 2, "00001001"); -- id=2, p=1 + check_mem("11.1 pos3", 3, "00000000"); -- nessun task aggiunto + report "Test 11.1 OK: insert ID=0 su lista popolata ignorato"; + + + -- ============================================================ + -- GRUPPO 12: Capacita' massima (63 task) + -- ============================================================ + -- L'errata del 24.02.2026 precisa che il limite e' 63 task (ID a + -- 6 bit, ID=0 escluso). Inseriamo TUTTI i 63 ID possibili con + -- prio = id mod 4, verifichiamo l'intera memoria, tentiamo + -- inserimenti oltre il limite (necessariamente duplicati) e + -- svuotiamo con 63 pop verificando l'ordine di estrazione. + report "=== GRUPPO 12: Capacita' massima 63 task ==="; + + -- Modello di riferimento: bucket per priorita' crescente, + -- FIFO (ordine di inserimento = id crescente) dentro ogni bucket + idx := 1; + for p in 0 to 3 loop + for id in 1 to 63 loop + if (id mod 4) = p then + exp_id(idx) := id; + exp_prio(idx) := p; + idx := idx + 1; + end if; + end loop; + end loop; + + clear_ram; + do_reset; + + -- 12.0: insert di tutti i 63 ID in ordine crescente, prio = id mod 4 + for id in 1 to 63 loop + do_op("10", + std_logic_vector(to_unsigned(id, 6)), + std_logic_vector(to_unsigned(id mod 4, 2))); + end loop; + check_mem("12.0 count", 0, std_logic_vector(to_unsigned(63, 8))); + for pos in 1 to 63 loop + exp_byte := std_logic_vector(to_unsigned(exp_id(pos) * 4 + exp_prio(pos), 8)); + check_mem("12.0 pos" & integer'image(pos), pos, exp_byte); + end loop; + report "Test 12.0 OK: 63 task inseriti, memoria completa verificata"; + + -- 12.1: inserimenti oltre il 63esimo: ogni ID possibile e' gia' + -- in lista -> tutti ignorati (dup in testa, in mezzo, in fondo) + do_op("10", "000001", "11"); -- dup ID=1 + do_op("10", "100000", "00"); -- dup ID=32 + do_op("10", "111111", "00"); -- dup ID=63 + do_op("10", "000000", "00"); -- ID=0 a lista piena + check_mem("12.1 count", 0, std_logic_vector(to_unsigned(63, 8))); + for pos in 1 to 63 loop + exp_byte := std_logic_vector(to_unsigned(exp_id(pos) * 4 + exp_prio(pos), 8)); + check_mem("12.1 pos" & integer'image(pos), pos, exp_byte); + end loop; + report "Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati"; + + -- 12.2: drain completo, 63 pop con verifica dell'ordine di estrazione + for pos in 1 to 63 loop + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("12.2 pop" & integer'image(pos), + captured_id, + std_logic_vector(to_unsigned(exp_id(pos), 6))); + end loop; + check_mem("12.2 count", 0, "00000000"); + -- pop numero 64 su lista appena svuotata -> 0 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("12.2 pop-empty", captured_id, "000000"); + report "Test 12.2 OK: drain di 63 task nell'ordine atteso"; + + + -- ============================================================ + -- GRUPPO 13: Memoria stale e duplicati ai bordi della lista + -- ============================================================ + report "=== GRUPPO 13: Stale memory e duplicati ai bordi ==="; + + -- 13.0: Re-insert di un ID appena rimosso + -- Dopo il pop lo shift lascia una copia stale dell'ultimo + -- task oltre il count: lo scan duplicati NON deve vederla + -- e il re-insert dell'ID estratto deve riuscire. + clear_ram; + do_reset; + do_op("10", "000101", "01"); -- id=5, p=1 + do_op("10", "000110", "10"); -- id=6, p=2 + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("13.0 pop", captured_id, "000101"); -- esce id=5 + -- mem: [1]=id6,p2 (count=1), [2] stale = id6,p2 + do_op("10", "000101", "11"); -- re-insert id=5 con prio diversa + check_mem("13.0 count", 0, "00000010"); + check_mem("13.0 pos1", 1, "00011010"); -- id=6, p=2 + check_mem("13.0 pos2", 2, "00010111"); -- id=5, p=3 (sovrascrive la stale) + report "Test 13.0 OK: re-insert di ID appena rimosso"; + + -- 13.1: Duplicato in PRIMA posizione (i gruppi 0-10 testano solo + -- il dup in posizione centrale) + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, p=0 + do_op("10", "000010", "01"); -- id=2, p=1 + do_op("10", "000011", "10"); -- id=3, p=2 + do_op("10", "000001", "11"); -- dup del task in pos 1 + check_mem("13.1 count", 0, "00000011"); + check_mem("13.1 pos1", 1, "00000100"); + check_mem("13.1 pos2", 2, "00001001"); + check_mem("13.1 pos3", 3, "00001110"); + check_mem("13.1 pos4", 4, "00000000"); + report "Test 13.1 OK: duplicato in prima posizione ignorato"; + + -- 13.2: Duplicato in ULTIMA posizione (stessa lista del 13.1) + do_op("10", "000011", "00"); -- dup del task in pos 3 (ultima) + check_mem("13.2 count", 0, "00000011"); + check_mem("13.2 pos1", 1, "00000100"); + check_mem("13.2 pos2", 2, "00001001"); + check_mem("13.2 pos3", 3, "00001110"); + check_mem("13.2 pos4", 4, "00000000"); + report "Test 13.2 OK: duplicato in ultima posizione ignorato"; + + -- 13.3: Clear poi re-insert dello STESSO ID + -- Il clear azzera solo il count: la cella task resta scritta + -- (stale). L'insert dello stesso ID non deve essere scambiato + -- per duplicato. + clear_ram; + do_reset; + do_op("10", "001001", "01"); -- id=9, p=1 + do_op("11", "000000", "00"); -- clear: mem[1] resta stale con id=9 + do_op("10", "001001", "10"); -- re-insert id=9, p=2: deve riuscire + check_mem("13.3 count", 0, "00000001"); + check_mem("13.3 pos1", 1, "00100110"); -- id=9, p=2 + report "Test 13.3 OK: re-insert stesso ID dopo clear"; + + + -- ============================================================ + -- GRUPPO 14: Reset asincrono avanzato + -- ============================================================ + -- La specifica consente RESET "in qualsiasi momento + -- dell'esecuzione": qui lo applichiamo nei punti piu' scomodi. + -- Dopo ogni reset si verifica che addr 0 = 0 e che il modulo + -- sia di nuovo pienamente operativo. + report "=== GRUPPO 14: Reset asincrono avanzato ==="; + + -- 14.0: Reset a meta' dello shift di OP=01 (fase COPY del 1° shift) + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + do_op("10", "000011", "10"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + for k in 1 to 6 loop + wait until rising_edge(tb_clk); + end loop; + wait until falling_edge(tb_clk); + tb_rst <= '1'; + tb_start <= '0'; + wait for 60 ns; + assert tb_done = '1' + report "FAIL [14.0] DONE deve essere 1 durante reset a meta' shift" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("14.0 count", 0, "00000000"); + do_op("10", "000111", "01"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("14.0 op-after-reset", captured_id, "000111"); + report "Test 14.0 OK: reset a meta' shift di OP=01"; + + -- 14.1: Reset nel ciclo della scrittura del count (fine OP=01) + -- Con 3 task i segnali di scrittura del count vengono + -- registrati al 12° fronte dopo il campionamento di START: + -- il reset arriva tra la registrazione e il commit in + -- memoria. S_RESET deve comunque lasciare addr 0 = 0. + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + do_op("10", "000011", "10"); + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + for k in 1 to 12 loop + wait until rising_edge(tb_clk); + end loop; + tb_rst <= '1'; + tb_start <= '0'; + wait for 60 ns; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("14.1 count", 0, "00000000"); + do_op("10", "001000", "10"); + check_mem("14.1 op-after-reset count", 0, "00000001"); + check_mem("14.1 op-after-reset pos1", 1, "00100010"); -- id=8, p=2 + report "Test 14.1 OK: reset durante la scrittura del count"; + + -- 14.2: Reset a meta' della scansione di OP=00 + -- (durante il ciclo di commit della scrittura del 1° task) + clear_ram; + do_reset; + do_op("10", "000001", "00"); + do_op("10", "000010", "01"); + wait until falling_edge(tb_clk); + tb_op <= "00"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + for k in 1 to 4 loop + wait until rising_edge(tb_clk); + end loop; + wait until falling_edge(tb_clk); + tb_rst <= '1'; + tb_start <= '0'; + wait for 60 ns; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("14.2 count", 0, "00000000"); + do_op("10", "000101", "00"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("14.2 op-after-reset", captured_id, "000101"); + report "Test 14.2 OK: reset durante OP=00"; + + -- 14.3: Reset mentre DONE=1 (tra il completamento dell'operazione + -- e l'abbassamento di START) + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= "000100"; -- id=4 + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + tb_rst <= '1'; -- reset proprio mentre DONE=1 + tb_start <= '0'; + wait for 60 ns; + assert tb_done = '1' + report "FAIL [14.3] DONE deve restare 1 durante reset" + severity failure; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("14.3 count", 0, "00000000"); -- lista di nuovo vuota + do_op("10", "000110", "11"); + check_mem("14.3 op-after-reset count", 0, "00000001"); + check_mem("14.3 op-after-reset pos1", 1, "00011011"); -- id=6, p=3 + report "Test 14.3 OK: reset mentre DONE=1"; + + -- 14.4: Reset corto (7 ns, non allineato al clock) + -- RESET e' asincrono: anche un impulso piu' corto del + -- periodo e fuori fase deve reinizializzare il modulo. + clear_ram; + do_reset; + do_op("10", "000001", "01"); + do_op("10", "000010", "10"); + wait until falling_edge(tb_clk); + wait for 3 ns; -- disallinea dal fronte + tb_rst <= '1'; + wait for 7 ns; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + check_mem("14.4 count", 0, "00000000"); + do_op("10", "001100", "01"); + do_op_capture("01", "000000", "00", captured_id); + check_captured_id("14.4 op-after-reset", captured_id, "001100"); + report "Test 14.4 OK: reset corto non allineato"; + + + -- ============================================================ + -- GRUPPO 15: Protocollo START-DONE con abbassamento lento di START + -- ============================================================ + -- La specifica NON garantisce che START scenda entro lo stesso + -- ciclo in cui DONE va a 1: dice solo che l'esterno lo riporta a 0 + -- quando DONE e' 1, e che il modulo puo' abbassare DONE quando + -- START torna a 0. Qui START resta alto per 1-2 cicli interi dopo + -- DONE=1: il modulo NON deve rieseguire l'operazione. + -- + -- NOTA: con l'RTL attuale (senza stato S_DONE che attende START=0) + -- questi test FALLISCONO: e' il comportamento da correggere. + report "=== GRUPPO 15: START lento dopo DONE=1 ==="; + + -- 15.0: Pop con START tenuto alto 1 ciclo extra -> NIENTE doppio pop + clear_ram; + do_reset; + do_op("10", "000001", "01"); -- id=1, p=1 + do_op("10", "000010", "10"); -- id=2, p=2 + wait until falling_edge(tb_clk); + tb_op <= "01"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + check_task_id("15.0 pop-id", "000001"); + wait until rising_edge(tb_clk); -- START resta alto un ciclo intero + wait until falling_edge(tb_clk); + tb_start <= '0'; + wait for 300 ns; -- tempo abbondante per un eventuale re-run + assert tb_done = '0' + report "FAIL [15.0] DONE non e' tornato a 0 dopo START=0" + severity failure; + check_mem("15.0 count", 0, "00000001"); -- UN solo pop: count=1 + check_mem("15.0 pos1", 1, "00001010"); -- id=2, p=2 ancora in lista + report "Test 15.0 OK: nessun doppio pop con START lento"; + + -- 15.1: Age con START tenuto alto 1 ciclo extra -> NIENTE doppio age + clear_ram; + do_reset; + do_op("10", "000001", "00"); -- id=1, p=0 + wait until falling_edge(tb_clk); + tb_op <= "00"; + tb_i_task_id <= "000000"; + tb_task_priority <= "00"; + tb_start <= '1'; + wait until rising_edge(tb_done); + wait until rising_edge(tb_clk); + wait until falling_edge(tb_clk); + tb_start <= '0'; + wait for 300 ns; + assert tb_done = '0' + report "FAIL [15.1] DONE non e' tornato a 0 dopo START=0" + severity failure; + check_mem("15.1 pos1", 1, "00000101"); -- prio 0->1, NON 0->2 + report "Test 15.1 OK: nessun doppio age con START lento"; + + -- 15.2: Insert con START tenuto alto 2 cicli extra + -- (un re-run qui sarebbe mascherato dal filtro duplicati: + -- il test verifica soprattutto la tenuta del protocollo DONE) + clear_ram; + do_reset; + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= "000111"; -- id=7 + tb_task_priority <= "01"; + tb_start <= '1'; + wait until rising_edge(tb_done); + wait until rising_edge(tb_clk); + wait until rising_edge(tb_clk); -- 2 cicli extra + wait until falling_edge(tb_clk); + tb_start <= '0'; + wait for 300 ns; + assert tb_done = '0' + report "FAIL [15.2] DONE non e' tornato a 0 dopo START=0" + severity failure; + check_mem("15.2 count", 0, "00000001"); + check_mem("15.2 pos1", 1, "00011101"); -- id=7, p=1 + report "Test 15.2 OK: insert con START tenuto 2 cicli extra"; + + + -- ============================================================ + -- Fine + -- ============================================================ + assert false + report "======================================" & LF + & " Tutti i test edge case sono PASSATI " & LF + & "======================================" + severity failure; + + end process; + +end architecture; \ No newline at end of file diff --git a/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd b/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd new file mode 100644 index 0000000..a914611 --- /dev/null +++ b/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd @@ -0,0 +1,351 @@ +-- ============================================================ +-- TESTBENCH TIMING - Progetto Reti Logiche 2025/2026 +-- ============================================================ +-- Verifica il numero di cicli di clock per ciascuna operazione. +-- +-- Formule attese (calibrate sull'FSM con stato S_DONE, che aggiunge +-- 1 ciclo a fine operazione per garantire DONE dopo il commit in memoria): +-- OP=10 inserimento: stati = 6 + 2*max(N,1) + 3k +-- (N = task gia' in lista, scanditi dal controllo +-- duplicati; k = task spostati per fare posto) +-- OP=01 rimozione: stati = 6 + 3k (k = task spostati, lista vuota = 2) +-- OP=00 decremento: stati = 4 + 3n (n = task in lista) +-- +-- Per ogni test viene stampato: +-- - il numero di cicli misurati +-- - il numero di cicli attesi +-- - PASS o FAIL +-- ============================================================ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity project_tb_timing is +end project_tb_timing; + +architecture timing_arch of project_tb_timing is + + constant CLOCK_PERIOD : time := 20 ns; + + signal tb_clk : std_logic := '0'; + signal tb_rst : std_logic := '0'; + signal tb_start : std_logic := '0'; + signal tb_done : std_logic; + signal tb_o_task_id : std_logic_vector(5 downto 0); + signal tb_task_priority : std_logic_vector(1 downto 0) := "00"; + signal tb_op : std_logic_vector(1 downto 0) := "00"; + signal tb_i_task_id : std_logic_vector(5 downto 0) := "000000"; + + signal exc_o_mem_addr : std_logic_vector(15 downto 0); + signal exc_o_mem_data : std_logic_vector(7 downto 0); + signal exc_o_mem_we : std_logic; + signal exc_o_mem_en : std_logic; + + signal init_o_mem_addr : std_logic_vector(15 downto 0) := (others => '0'); + signal init_o_mem_data : std_logic_vector(7 downto 0) := (others => '0'); + signal init_o_mem_we : std_logic := '0'; + signal init_o_mem_en : std_logic := '0'; + + signal tb_o_mem_addr : std_logic_vector(15 downto 0); + signal tb_o_mem_data : std_logic_vector(7 downto 0); + signal tb_o_mem_we : std_logic; + signal tb_o_mem_en : std_logic; + signal tb_i_mem_data : std_logic_vector(7 downto 0); + + signal memory_control : std_logic := '0'; + + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type := (others => "00000000"); + + component project_reti_logiche is + port ( + i_clk : in std_logic; + i_rst : in std_logic; + i_start : in std_logic; + i_task_id : in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op : in std_logic_vector(1 downto 0); + o_done : out std_logic; + o_task_id : out std_logic_vector(5 downto 0); + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we : out std_logic; + o_mem_en : out std_logic + ); + end component; + +begin + + UUT : project_reti_logiche + port map ( + i_clk => tb_clk, + i_rst => tb_rst, + i_start => tb_start, + i_task_id => tb_i_task_id, + i_task_priority => tb_task_priority, + i_op => tb_op, + o_done => tb_done, + o_task_id => tb_o_task_id, + o_mem_addr => exc_o_mem_addr, + i_mem_data => tb_i_mem_data, + o_mem_data => exc_o_mem_data, + o_mem_we => exc_o_mem_we, + o_mem_en => exc_o_mem_en + ); + + tb_clk <= not tb_clk after CLOCK_PERIOD / 2; + + MEM : process (tb_clk) + begin + if tb_clk'event and tb_clk = '1' then + if tb_o_mem_en = '1' then + if tb_o_mem_we = '1' then + RAM(to_integer(unsigned(tb_o_mem_addr))) <= tb_o_mem_data after 1 ns; + tb_i_mem_data <= tb_o_mem_data after 1 ns; + else + tb_i_mem_data <= RAM(to_integer(unsigned(tb_o_mem_addr))) after 1 ns; + end if; + end if; + end if; + end process; + + memory_signal_swapper : process (memory_control, + init_o_mem_addr, init_o_mem_data, init_o_mem_en, init_o_mem_we, + exc_o_mem_addr, exc_o_mem_data, exc_o_mem_en, exc_o_mem_we) + begin + tb_o_mem_addr <= init_o_mem_addr; + tb_o_mem_data <= init_o_mem_data; + tb_o_mem_en <= init_o_mem_en; + tb_o_mem_we <= init_o_mem_we; + if memory_control = '1' then + tb_o_mem_addr <= exc_o_mem_addr; + tb_o_mem_data <= exc_o_mem_data; + tb_o_mem_en <= exc_o_mem_en; + tb_o_mem_we <= exc_o_mem_we; + end if; + end process; + + -- ============================================================ + -- Processo principale + -- ============================================================ + main : process + + -- Cicli misurati e attesi + variable t_start : time; + variable cycles : integer; + variable expected : integer; + + -- -------------------------------------------------------- + -- Reset + -- -------------------------------------------------------- + procedure do_reset is + begin + tb_start <= '0'; + tb_rst <= '1'; + wait for 100 ns; + tb_rst <= '0'; + wait until tb_done = '0'; + wait until falling_edge(tb_clk); + end procedure; + + -- -------------------------------------------------------- + -- Esegue un'operazione e misura i cicli dal primo fronte + -- di clock dopo START=1 fino al fronte che porta DONE=1 + -- -------------------------------------------------------- + procedure run_and_measure ( + op : std_logic_vector(1 downto 0); + task_id : std_logic_vector(5 downto 0); + priority : std_logic_vector(1 downto 0); + exp : integer; + test_num : integer + ) is + begin + wait until falling_edge(tb_clk); + tb_op <= op; + tb_i_task_id <= task_id; + tb_task_priority <= priority; + tb_start <= '1'; + + -- Il primo fronte di clock dopo START campiona l'ingresso + -- ed entra nel primo stato dell'operazione: inizia il conteggio + wait until rising_edge(tb_clk); + t_start := now; + + wait until rising_edge(tb_done); + -- DONE viene registrato sul fronte: questo è l'ultimo stato + cycles := (now - t_start) / CLOCK_PERIOD; + expected := exp; + + if cycles = expected then + report "[PASS] test=" & integer'image(test_num) + & " | cicli misurati=" & integer'image(cycles) + & " attesi=" & integer'image(expected); + else + report "[FAIL] test=" & integer'image(test_num) + & " | cicli misurati=" & integer'image(cycles) + & " attesi=" & integer'image(expected) + severity failure; + end if; + + tb_start <= '0'; + wait until falling_edge(tb_done); + end procedure; + + -- -------------------------------------------------------- + -- Inserisce un task senza misurarlo (solo per preparare la lista) + -- -------------------------------------------------------- + procedure insert_silent ( + task_id : std_logic_vector(5 downto 0); + priority : std_logic_vector(1 downto 0) + ) is + begin + wait until falling_edge(tb_clk); + tb_op <= "10"; + tb_i_task_id <= task_id; + tb_task_priority <= priority; + tb_start <= '1'; + wait until rising_edge(tb_done); + tb_start <= '0'; + wait until falling_edge(tb_done); + end procedure; + + begin + memory_control <= '1'; + wait for 50 ns; + + -- ============================================================ + -- OP=10: Inserimento -> stati attesi = 6 + 4k + -- ============================================================ + report "=============================="; + report "OP=10 Inserimento: 6 + 2*max(N,1) + 3k stati"; + report "=============================="; + + -- N=0, k=0: lista vuota -> 6 + 2 + 0 = 8 stati + -- OP=10 N=0 k=0 (lista vuota) + do_reset; + run_and_measure("10", "000001", "01", 8, 1); + + -- N=1, k=1: 1 task con priorità minore -> spostato -> 6 + 2 + 3 = 11 + -- OP=10 N=1 k=1 (1 task spostato) + do_reset; + insert_silent("000001", "10"); + run_and_measure("10", "000010", "01", 11, 2); + + -- N=2, k=2: 2 task da spostare -> 6 + 4 + 6 = 16 + -- OP=10 N=2 k=2 (2 task spostati) + do_reset; + insert_silent("000001", "10"); + insert_silent("000010", "10"); + run_and_measure("10", "000011", "01", 16, 3); + + -- N=3, k=3: 3 task da spostare -> 6 + 6 + 9 = 21 + -- OP=10 N=3 k=3 (3 task spostati) + do_reset; + insert_silent("000001", "10"); + insert_silent("000010", "10"); + insert_silent("000011", "10"); + run_and_measure("10", "000100", "01", 21, 4); + + -- N=2, k=0: inserimento in fondo, lista non vuota -> 6 + 4 + 0 = 10 + -- OP=10 N=2 k=0 (inserimento in fondo) + do_reset; + insert_silent("000001", "00"); + insert_silent("000010", "01"); + run_and_measure("10", "000011", "11", 10, 5); + + -- ============================================================ + -- OP=01: Rimozione -> stati attesi = 5 + 3k (lista vuota = 1) + -- ============================================================ + report "=============================="; + report "OP=01 Rimozione: 6 + 3k stati (lista vuota = 2)"; + report "=============================="; + + -- Lista vuota -> 2 stati (CHECK_NUMBER + S_DONE) + -- OP=01 lista vuota + do_reset; + run_and_measure("01", "000000", "00", 2, 6); + + -- k=0: 1 solo task, nessuno spostamento -> 6 stati + -- OP=01 k=0 (1 task, nessuno spostamento) + do_reset; + insert_silent("000001", "01"); + run_and_measure("01", "000000", "00", 6, 7); + + -- k=1: 2 task, 1 da spostare -> 9 stati + -- OP=01 k=1 (1 task spostato) + do_reset; + insert_silent("000001", "01"); + insert_silent("000010", "01"); + run_and_measure("01", "000000", "00", 9, 8); + + -- k=2: 3 task, 2 da spostare -> 12 stati + -- OP=01 k=2 (2 task spostati) + do_reset; + insert_silent("000001", "01"); + insert_silent("000010", "01"); + insert_silent("000011", "01"); + run_and_measure("01", "000000", "00", 12, 9); + + -- k=3: 4 task, 3 da spostare -> 15 stati + -- OP=01 k=3 (3 task spostati) + do_reset; + insert_silent("000001", "01"); + insert_silent("000010", "01"); + insert_silent("000011", "01"); + insert_silent("000100", "01"); + run_and_measure("01", "000000", "00", 15, 10); + + -- ============================================================ + -- OP=00: Decremento -> stati attesi = 3 + 3n + -- ============================================================ + report "=============================="; + report "OP=00 Decremento: 4 + 3n stati"; + report "=============================="; + + -- n=0: lista vuota -> 4 stati + -- OP=00 n=0 (lista vuota) + do_reset; + run_and_measure("00", "000000", "00", 4, 11); + + -- n=1 -> 7 stati + -- OP=00 n=1 + do_reset; + insert_silent("000001", "01"); + run_and_measure("00", "000000", "00", 7, 12); + + -- n=2 -> 10 stati + -- OP=00 n=2 + do_reset; + insert_silent("000001", "01"); + insert_silent("000010", "10"); + run_and_measure("00", "000000", "00", 10, 13); + + -- n=3 -> 13 stati + -- OP=00 n=3 + do_reset; + insert_silent("000001", "01"); + insert_silent("000010", "10"); + insert_silent("000011", "11"); + run_and_measure("00", "000000", "00", 13, 14); + + -- n=4 con saturazione (tutti prio=3) -> 4 + 3*4 = 16 stati + -- OP=00 n=4 (tutti gia prio=3, saturazione) + do_reset; + insert_silent("000001", "11"); + insert_silent("000010", "11"); + insert_silent("000011", "11"); + insert_silent("000100", "11"); + run_and_measure("00", "000000", "00", 16, 15); + + -- ============================================================ + -- Fine + -- ============================================================ + assert false + report "Tutti i test di timing sono PASSATI" + severity failure; + + end process; + +end architecture; \ No newline at end of file diff --git a/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd b/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd new file mode 100644 index 0000000..2b3998e --- /dev/null +++ b/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd @@ -0,0 +1,207 @@ +-- TB EXAMPLE PFRL 2023-2024 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity project_tb is +end project_tb; + +architecture project_tb_arch of project_tb is + constant CLOCK_PERIOD : time := 20 ns; + signal tb_clk : std_logic := '0'; + signal tb_rst, tb_start, tb_done : std_logic; + signal tb_o_task_id : std_logic_vector(5 downto 0); + signal tb_task_priority, tb_op : std_logic_vector(1 downto 0); + signal tb_i_task_id : std_logic_vector(5 downto 0); + + signal tb_o_mem_addr, exc_o_mem_addr, init_o_mem_addr : std_logic_vector(15 downto 0); + signal tb_o_mem_data, exc_o_mem_data, init_o_mem_data : std_logic_vector(7 downto 0); + signal tb_i_mem_data : std_logic_vector(7 downto 0); + signal tb_o_mem_we, tb_o_mem_en, exc_o_mem_we, exc_o_mem_en, init_o_mem_we, init_o_mem_en : std_logic; + + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type := (OTHERS => "00000000"); + + type scenario_config_type_t is record + task_id : std_logic_vector(5 downto 0); + task_priority : std_logic_vector(1 downto 0); + op : std_logic_vector(1 downto 0); + end record scenario_config_type_t; + + constant SCENARIO_SIZE : integer := 9; + type scenario_config_type is array (0 to SCENARIO_SIZE-1) of scenario_config_type_t; + + signal scenario_config : scenario_config_type := ( + (task_id => "000001", task_priority => "01", op => "10"), -- Post memory: [00000001,00000101] + (task_id => "000000", task_priority => "00", op => "11"), -- Post memory: [00000000] + (task_id => "000001", task_priority => "01", op => "10"), -- Post memory: [00000001,00000101] + (task_id => "000010", task_priority => "01", op => "10"), -- Post memory: [00000010,00000101,00001001] + (task_id => "000011", task_priority => "10", op => "10"), -- Post memory: [00000011,00000101,00001001,00001110] + (task_id => "000100", task_priority => "00", op => "10"), -- Post memory: [00000100,00010000,00000101,00001001,00001110] + (task_id => "000000", task_priority => "00", op => "01"), -- Post memory: [00000011,00000101,00001001,00001110] + (task_id => "000000", task_priority => "00", op => "00"), -- Post memory: [00000011,00000110,00001010,00001111] + (task_id => "000000", task_priority => "00", op => "00") -- Post memory: [00000011,00000111,00001011,00001111] + ); + + type scenario_single_result_type is array (0 to 32) of std_logic_vector(7 downto 0); + type scenario_result_type is array (0 to 100) of scenario_single_result_type; + type int_array_t is array (0 to SCENARIO_SIZE - 1) of integer; + constant CHECK_SIZE_ARRAY : int_array_t := ( + 2,1,2,3,4,5,4,4,4 + ); + + signal scenario_result : scenario_result_type := ( + ( "00000001", "00000101", others => "00000000"), + ( "00000000", others => "00000000"), + ( "00000001", "00000101", others => "00000000"), + ( "00000010", "00000101", "00001001", others => "00000000"), + ( "00000011", "00000101", "00001001", "00001110", others => "00000000"), + ( "00000100", "00010000", "00000101", "00001001", "00001110", others => "00000000"), + ( "00000011", "00000101", "00001001", "00001110", others => "00000000"), + ( "00000011", "00000110", "00001010", "00001111", others => "00000000"), + ( "00000011", "00000111", "00001011", "00001111", others => "00000000"), + others => (others => "00000000") + ); + + + signal memory_control : std_logic := '0'; + signal first_task_queue : std_logic_vector(5 downto 0); + + component project_reti_logiche is + port ( + i_clk : in std_logic; + i_rst : in std_logic; + + i_start : in std_logic; + i_task_id : in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op : in std_logic_vector(1 downto 0); + + o_done : out std_logic; + o_task_id : out std_logic_vector(5 downto 0); + + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we : out std_logic; + o_mem_en : out std_logic + ); + end component project_reti_logiche; + + +begin + UUT : project_reti_logiche + port map( + i_clk => tb_clk, + i_rst => tb_rst, + i_start => tb_start, + i_task_id => tb_i_task_id, + i_task_priority => tb_task_priority, + i_op => tb_op, + + o_done => tb_done, + o_task_id => tb_o_task_id, + + o_mem_addr => exc_o_mem_addr, + i_mem_data => tb_i_mem_data, + o_mem_data => exc_o_mem_data, + o_mem_we => exc_o_mem_we, + o_mem_en => exc_o_mem_en + ); + + -- Clock generation + tb_clk <= not tb_clk after CLOCK_PERIOD/2; + + -- Process related to the memory + MEM : process (tb_clk) + begin + if tb_clk'event and tb_clk = '1' then + if tb_o_mem_en = '1' then + if tb_o_mem_we = '1' then + RAM(to_integer(unsigned(tb_o_mem_addr))) <= tb_o_mem_data after 1 ns; + tb_i_mem_data <= tb_o_mem_data after 1 ns; + else + tb_i_mem_data <= RAM(to_integer(unsigned(tb_o_mem_addr))) after 1 ns; + end if; + end if; + end if; + end process; + + memory_signal_swapper : process(memory_control, init_o_mem_addr, init_o_mem_data, + init_o_mem_en, init_o_mem_we, exc_o_mem_addr, + exc_o_mem_data, exc_o_mem_en, exc_o_mem_we) + begin + -- This is necessary for the testbench to work: we swap the memory + -- signals from the component to the testbench when needed. + + tb_o_mem_addr <= init_o_mem_addr; + tb_o_mem_data <= init_o_mem_data; + tb_o_mem_en <= init_o_mem_en; + tb_o_mem_we <= init_o_mem_we; + + if memory_control = '1' then + tb_o_mem_addr <= exc_o_mem_addr; + tb_o_mem_data <= exc_o_mem_data; + tb_o_mem_en <= exc_o_mem_en; + tb_o_mem_we <= exc_o_mem_we; + end if; + end process; + + -- This process provides the correct scenario on the signal controlled by the TB + create_scenario : process + begin + wait for 50 ns; + + -- Signal initialization and reset of the component + tb_start <= '0'; + tb_rst <= '1'; + + -- Wait some time for the component to reset... + wait for 100 ns; + + --assert tb_done = '1' report "TEST FALLITO o_done !=1 during reset" severity failure; + + tb_rst <= '0'; + memory_control <= '1'; -- Memory controlled by the component + + wait until tb_done = '0'; + + assert RAM(0) = "00000000" report "TEST FALLITO @ OFFSET=0 expected=0 actual=" & integer'image(to_integer(unsigned(RAM(0)))) severity failure; + + wait until falling_edge(tb_clk); + + for i in 0 to SCENARIO_SIZE - 1 loop + if i > 0 then + -- Save top of the queue for later use + first_task_queue <= scenario_result(i-1)(1)(7 downto 2); + end if; + tb_op <= scenario_config(i).op; + tb_i_task_id <= scenario_config(i).task_id; + tb_task_priority <= scenario_config(i).task_priority; + tb_start <= '1'; + + wait until rising_edge(tb_done); + + if scenario_config(i).op = "01" then + -- Check output task only if the operation was the task removal + assert first_task_queue = tb_o_task_id report "TEST FALLITO @ STEP=" & integer'image(i) & " expected task_id=" & integer'image(to_integer(unsigned(first_task_queue))) & " actual task_id=" & integer'image(to_integer(unsigned(tb_o_task_id))) ; + end if; + + -- Check memory contents + for j in 0 to CHECK_SIZE_ARRAY(i) - 1 loop + assert RAM(j) = scenario_result(i)(j) report "TEST FALLITO @ STEP=" & integer'image(i) & " OFFSET=" & integer'image(j) & " expected=" & integer'image(to_integer(unsigned(scenario_result(i)(j)))) & " actual=" & integer'image(to_integer(unsigned(RAM(j)))) ; + end loop; + + tb_start <= '0'; + wait until falling_edge(tb_done); + wait until falling_edge(tb_clk); + + report "Test step " & integer'image(i) & " OK."; + end loop; + + assert false report "Simulation Ended! TEST PASSATO (EXAMPLE)" severity failure; + end process; + +end architecture; diff --git a/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd b/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd new file mode 100644 index 0000000..3265420 --- /dev/null +++ b/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd @@ -0,0 +1,407 @@ +-- Progetto di reti logiche 2025/2026 - Aleandro Pagani + +-- Scheduler di task con priorità. Gestisce una lista ordinata in memoria +-- esterna (mem[0]=contatore, mem[1..N]=task come ID&PRIORITY a 8 bit). +-- OP 00=invecchiamento, 01=rimozione, 10=inserimento, 11=svuotamento. +-- FSM a due processi (combinatorio + sincrono), reset asincrono. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity project_reti_logiche is + port ( + i_clk : in std_logic; + i_rst : in std_logic; + + i_start : in std_logic; + i_task_id : in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op : in std_logic_vector(1 downto 0); + + o_done : out std_logic; + o_task_id : out std_logic_vector(5 downto 0); + + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we : out std_logic; + o_mem_en : out std_logic + ); +end project_reti_logiche; + + +architecture FSM of project_reti_logiche is + + ---------------------------------------------------------------- + -- Stati della FSM (prefisso S_xx_ = stati dell'operazione "xx") + ---------------------------------------------------------------- + type state_type is ( + -- Gestione del protocollo + S_IDLE, -- attesa di START, dispatch delle operazioni + S_RESET, -- reset: scrive 0 in mem[0] + S_DONE, -- DONE = 1 finché START non torna a 0 + + -- OP = "00": invecchiamento + S_00_READ, -- avvia la lettura del primo task (mem[1]) + S_00_WAIT, -- attesa latenza di lettura + S_00_CHECK, -- fine lista? altrimenti incrementa/satura + S_00_GO_NEXT, -- avvia la lettura del task successivo + + -- OP = "01": rimozione + S_01_CHECK_NUMBER, -- lista vuota? altrimenti avvia lettura di mem[1] + S_01_WAIT, -- attesa latenza di lettura + S_01_WRITE, -- salva l'ID estratto, avvia lettura di mem[2] + S_01_CHECK_END, -- fine lista? scrive il contatore decrementato + S_01_COPY, -- copia il task letto una posizione più su + S_01_GO_NEXT, -- avvia la lettura del task successivo + S_01_WAIT_FOR_COUNT, -- attesa della scrittura nel contatore + + -- OP = "10": inserimento + S_10_PLACE_AT_START, -- scarta ID = 0, avvia la scansione duplicati + S_10_WAIT_FOR_CHECK, -- attesa latenza di lettura (fase scansione) + S_10_CHECK_ID, -- duplicato? prosegue scansione o passa all'inserimento + S_10_WAIT, -- attesa latenza di lettura (fase inserimento) + S_10_COMPARE, -- inserisce qui oppure sposta il task in basso + S_10_GO_NEXT, -- avvia la lettura del task precedente + S_10_UPDATE_COUNT, -- scrive il contatore incrementato + S_10_WAIT_FOR_COUNT, -- attesa della scrittura nel contatore + + -- OP = "11": svuotamento + S_11_UPDATE_COUNT, -- scrive 0 in mem[0] + S_11_WAIT_FOR_COUNT -- attesa del commit della scrittura del contatore + ); + + ---------------------------------------------------------------- + -- Segnali interni (coppie current/next) + ---------------------------------------------------------------- + signal state : state_type; + signal next_state : state_type; + + -- Indirizzo di memoria su cui la FSM sta lavorando (0 = contatore) + signal current_mem_addr : std_logic_vector(15 downto 0); + signal next_mem_addr : std_logic_vector(15 downto 0); + + -- Copia locale del numero di task presenti in lista (mem[0]) + signal current_task_count : std_logic_vector(7 downto 0); + signal next_task_count : std_logic_vector(7 downto 0); + + -- ID estratto dall'ultima rimozione, presentato su o_task_id in S_DONE + signal current_popped_id : std_logic_vector(5 downto 0); + signal next_popped_id : std_logic_vector(5 downto 0); + + ---------------------------------------------------------------- + -- Segnali di controllo calcolati dal processo combinatorio, + -- registrati sulle uscite (o_done, o_task_id, interfaccia memoria) + ---------------------------------------------------------------- + signal ctrl_done : std_logic; + signal ctrl_mem_en : std_logic; + signal ctrl_mem_we : std_logic; + signal ctrl_mem_data : std_logic_vector(7 downto 0); + signal ctrl_task_id : std_logic_vector(5 downto 0); + +begin + + ---------------------------------------------------------------- + -- PROCESSO COMBINATORIO + -- Calcola stato prossimo e segnali di controllo. + -- Le assegnazioni di default in testa coprono ogni ramo: + -- nessun latch inferito. + ---------------------------------------------------------------- + process (state, i_start, i_op, i_mem_data, i_task_id, i_task_priority, + current_task_count, current_mem_addr, current_popped_id) + begin + next_state <= state; + next_task_count <= current_task_count; + next_mem_addr <= current_mem_addr; + next_popped_id <= current_popped_id; + ctrl_done <= '0'; + ctrl_mem_en <= '0'; + ctrl_mem_we <= '0'; + ctrl_mem_data <= (others => '0'); + ctrl_task_id <= (others => '0'); + + case state is + + ------------------------------------------------------------ + -- S_IDLE: attesa di START. Al dispatch azzera l'ID estratto, + -- così o_task_id varrà 0 in S_DONE per ogni operazione che + -- non sia una rimozione andata a buon fine. + ------------------------------------------------------------ + when S_IDLE => + if i_start = '1' then + next_popped_id <= (others => '0'); + case i_op is + when "00" => next_state <= S_00_READ; -- invecchiamento + when "01" => next_state <= S_01_CHECK_NUMBER; -- rimozione + when "10" => next_state <= S_10_PLACE_AT_START; -- inserimento + when "11" => next_state <= S_11_UPDATE_COUNT; -- svuotamento + when others => null; + end case; + end if; + + ------------------------------------------------------------ + -- S_RESET: dopo un reset la lista deve risultare vuota. + -- Scrive 0 in mem[0] tenendo DONE a 1. + ------------------------------------------------------------ + when S_RESET => + next_state <= S_DONE; + next_task_count <= (others => '0'); + next_mem_addr <= (others => '0'); + next_popped_id <= (others => '0'); + ctrl_done <= '1'; + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= (others => '0'); + + ------------------------------------------------------------ + -- S_DONE: alza DONE e lo tiene a 1 finché START non torna a 0, + -- come richiesto dal protocollo di hand-shake. + -- DONE viene asserito qui, un ciclo dopo lo stato terminale + -- dell'operazione: sale quindi sempre dopo il commit in + -- memoria dell'ultima scrittura, e chi campiona la memoria + -- sul fronte di DONE legge dati già aggiornati. + -- o_task_id è valido per tutta la finestra DONE = 1. + ------------------------------------------------------------ + when S_DONE => + if i_start = '1' then + ctrl_done <= '1'; + ctrl_task_id <= current_popped_id; + else + next_state <= S_IDLE; + end if; + + ------------------------------------------------------------ + -- OP = "00" (invecchiamento) + -- Scorre la lista da mem[1] a mem[N]. Per ogni task con + -- priorità < 3 riscrive l'intero byte incrementato di 1: + -- equivale a incrementare i soli 2 bit di priorità, perché + -- la scrittura avviene solo se la priorità non è "11" e il + -- riporto non può quindi mai propagarsi nei bit dell'ID. + -- I task già a priorità 3 non vengono riscritti (saturazione). + ------------------------------------------------------------ + when S_00_READ => + next_state <= S_00_WAIT; + next_mem_addr <= x"0001"; + ctrl_mem_en <= '1'; + + when S_00_WAIT => + next_state <= S_00_CHECK; + + when S_00_CHECK => + if unsigned(current_mem_addr) = resize(unsigned(current_task_count), 16) + 1 then + next_state <= S_DONE; + elsif i_mem_data(1 downto 0) /= "11" then + next_state <= S_00_GO_NEXT; + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= std_logic_vector(unsigned(i_mem_data) + 1); + else + next_state <= S_00_GO_NEXT; + end if; + + when S_00_GO_NEXT => + next_state <= S_00_WAIT; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) + 1); + ctrl_mem_en <= '1'; + + ------------------------------------------------------------ + -- OP = "01" (rimozione) + -- Se la lista è vuota termina subito (o_task_id resterà 0). + -- Altrimenti salva l'ID di mem[1], compatta la lista + -- copiando ogni task una posizione più in alto + -- (mem[j] -> mem[j-1] per j = 2...N) e infine scrive il + -- contatore decrementato in mem[0]. + ------------------------------------------------------------ + when S_01_CHECK_NUMBER => + if current_task_count = x"00" then + next_state <= S_DONE; + else + next_state <= S_01_WAIT; + next_mem_addr <= x"0001"; + ctrl_mem_en <= '1'; + end if; + + when S_01_WAIT => + next_state <= S_01_WRITE; + + -- Salva l'ID del task estratto e avvia la lettura di mem[2]. + when S_01_WRITE => + next_state <= S_01_CHECK_END; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) + 1); + ctrl_mem_en <= '1'; + next_popped_id <= i_mem_data(7 downto 2); + + -- Qui current_mem_addr vale j (lettura di mem[j] in corso). + -- Se j = N + 1 la compattazione è finita: scrive N - 1 in mem[0]. + when S_01_CHECK_END => + if unsigned(current_mem_addr) = resize(unsigned(current_task_count), 16) + 1 then + next_state <= S_01_WAIT_FOR_COUNT; + next_task_count <= std_logic_vector(unsigned(current_task_count) - 1); + next_mem_addr <= x"0000"; + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= std_logic_vector(unsigned(current_task_count) - 1); + else + next_state <= S_01_COPY; + end if; + + -- Scrive mem[j], appena letto, in mem[j-1]. + when S_01_COPY => + next_state <= S_01_GO_NEXT; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) - 1); + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= i_mem_data; + + -- In S_01_COPY l'indirizzo è sceso a j-1 per la scrittura: + -- il +2 riporta la lettura su j+1, il task successivo. + when S_01_GO_NEXT => + next_state <= S_01_CHECK_END; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) + 2); + ctrl_mem_en <= '1'; + + -- Un ciclo di attesa: al suo termine la scrittura del + -- contatore è stata campionata dalla memoria. + when S_01_WAIT_FOR_COUNT => + next_state <= S_DONE; + + ------------------------------------------------------------ + -- OP = "10" (inserimento) - due fasi: + -- 1) scansione duplicati: legge mem[N]...mem[1]; se trova un + -- task con lo stesso ID termina senza modifiche; + -- 2) inserimento dal fondo: confronta il nuovo task con + -- mem[j] per j = N...1; finché il nuovo task ha priorità + -- migliore (valore minore) sposta mem[j] in mem[j+1], + -- altrimenti scrive il nuovo task in mem[j+1]. + -- Il confronto ">=" colloca il nuovo task DOPO quelli di + -- pari priorità. + ------------------------------------------------------------ + -- Scarta ID = 0. + -- Con lista vuota (N = 0) la scansione legge mem[0], cioè il + -- contatore: il confronto in S_10_CHECK_ID non può dare un + -- falso duplicato, perché in quel caso il contatore vale 0 e + -- l'ID, già filtrato, non è mai 0. + when S_10_PLACE_AT_START => + if i_task_id = "000000" then + next_state <= S_DONE; + else + next_state <= S_10_WAIT_FOR_CHECK; + next_mem_addr <= x"00" & current_task_count; + ctrl_mem_en <= '1'; + end if; + + when S_10_WAIT_FOR_CHECK => + next_state <= S_10_CHECK_ID; + + when S_10_CHECK_ID => + if i_mem_data(7 downto 2) = i_task_id then + -- ID già presente: l'inserimento viene ignorato + next_state <= S_DONE; + elsif unsigned(current_mem_addr) <= 1 then + -- scansione completata: rilegge mem[N] e passa + -- alla fase di inserimento + next_state <= S_10_WAIT; + next_mem_addr <= x"00" & current_task_count; + ctrl_mem_en <= '1'; + else + -- prosegue la scansione verso l'inizio della lista + next_state <= S_10_WAIT_FOR_CHECK; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) - 1); + ctrl_mem_en <= '1'; + end if; + + when S_10_WAIT => + next_state <= S_10_COMPARE; + + -- Qui current_mem_addr vale j (mem[j] appena letto). + -- current_mem_addr = 0 significa che tutta la lista è stata spostata: + -- il nuovo task va in testa (mem[1]). + when S_10_COMPARE => + if (current_mem_addr = x"0000") or + (unsigned(i_task_priority) >= unsigned(i_mem_data(1 downto 0))) then + -- posizione trovata: scrive il nuovo task in mem[j+1] + next_state <= S_10_UPDATE_COUNT; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) + 1); + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= i_task_id & i_task_priority; + else + -- il nuovo task deve stare più in alto: sposta + -- mem[j] in mem[j+1] e prosegue verso l'alto + next_state <= S_10_GO_NEXT; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) + 1); + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= i_mem_data; + end if; + + -- In S_10_COMPARE l'indirizzo è salito a j+1 per la + -- scrittura: il -2 riporta la lettura su j-1, il task + -- precedente da confrontare. + when S_10_GO_NEXT => + next_state <= S_10_WAIT; + next_mem_addr <= std_logic_vector(unsigned(current_mem_addr) - 2); + ctrl_mem_en <= '1'; + + when S_10_UPDATE_COUNT => + next_state <= S_10_WAIT_FOR_COUNT; + next_task_count <= std_logic_vector(unsigned(current_task_count) + 1); + next_mem_addr <= x"0000"; + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= std_logic_vector(unsigned(current_task_count) + 1); + + when S_10_WAIT_FOR_COUNT => + next_state <= S_DONE; + + ------------------------------------------------------------ + -- OP = "11" (svuotamento) + -- Scrive 0 in mem[0]: la lista risulta vuota, il contenuto + -- delle celle task può essere ignorato. + ------------------------------------------------------------ + when S_11_UPDATE_COUNT => + next_state <= S_11_WAIT_FOR_COUNT; + next_task_count <= (others => '0'); + next_mem_addr <= (others => '0'); + ctrl_mem_en <= '1'; + ctrl_mem_we <= '1'; + ctrl_mem_data <= (others => '0'); + + when S_11_WAIT_FOR_COUNT => + next_state <= S_DONE; + + end case; + end process; + + + ---------------------------------------------------------------- + -- PROCESSO SINCRONO + -- Registra stato e uscite sul fronte di salita del clock. + -- Reset asincrono: porta la FSM in S_RESET con DONE = 1 e disabilita + -- temporaneamente la memoria. + ---------------------------------------------------------------- + process (i_clk, i_rst) + begin + if i_rst = '1' then + state <= S_RESET; + o_done <= '1'; + o_mem_en <= '0'; + o_mem_we <= '0'; + elsif rising_edge(i_clk) then + state <= next_state; + current_mem_addr <= next_mem_addr; + current_task_count <= next_task_count; + current_popped_id <= next_popped_id; + + o_done <= ctrl_done; + o_mem_en <= ctrl_mem_en; + o_mem_we <= ctrl_mem_we; + o_mem_addr <= next_mem_addr; + o_mem_data <= ctrl_mem_data; + o_task_id <= ctrl_task_id; + end if; + end process; + +end FSM; diff --git a/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp b/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp new file mode 100644 index 0000000..3126ddc Binary files /dev/null and b/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp differ diff --git a/progetto_reti_logiche.xpr b/progetto_reti_logiche.xpr new file mode 100644 index 0000000..66701f4 --- /dev/null +++ b/progetto_reti_logiche.xpr @@ -0,0 +1,265 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/project_tb_behav.wcfg b/project_tb_behav.wcfg new file mode 100644 index 0000000..e7a2286 --- /dev/null +++ b/project_tb_behav.wcfg @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + tb_clk + tb_clk + + + tb_rst + tb_rst + + + tb_start + tb_start + + + tb_done + tb_done + + + tb_o_task_id[5:0] + tb_o_task_id[5:0] + + + tb_task_priority[1:0] + tb_task_priority[1:0] + + + tb_op[1:0] + tb_op[1:0] + + + tb_i_task_id[5:0] + tb_i_task_id[5:0] + + + tb_o_mem_addr[15:0] + tb_o_mem_addr[15:0] + + + exc_o_mem_addr[15:0] + exc_o_mem_addr[15:0] + + + init_o_mem_addr[15:0] + init_o_mem_addr[15:0] + + + tb_o_mem_data[7:0] + tb_o_mem_data[7:0] + + + exc_o_mem_data[7:0] + exc_o_mem_data[7:0] + + + init_o_mem_data[7:0] + init_o_mem_data[7:0] + + + tb_i_mem_data[7:0] + tb_i_mem_data[7:0] + + + tb_o_mem_we + tb_o_mem_we + + + tb_o_mem_en + tb_o_mem_en + + + exc_o_mem_we + exc_o_mem_we + + + exc_o_mem_en + exc_o_mem_en + + + init_o_mem_we + init_o_mem_we + + + init_o_mem_en + init_o_mem_en + + + scenario_config[0:8] + scenario_config[0:8] + + + scenario_result[0:100][0:32][7:0] + scenario_result[0:100][0:32][7:0] + + + memory_control + memory_control + + + first_task_queue[5:0] + first_task_queue[5:0] + + + CLOCK_PERIOD + CLOCK_PERIOD + + + SCENARIO_SIZE + SCENARIO_SIZE + + + CHECK_SIZE_ARRAY[0:8] + CHECK_SIZE_ARRAY[0:8] + + + state + state + + + [0][7:0] + [0][7:0] + + + [1][7:0] + [1][7:0] + + + [2][7:0] + [2][7:0] + + + [3][7:0] + [3][7:0] + + + [4][7:0] + [4][7:0] + + diff --git a/project_tb_edge_behav.wcfg b/project_tb_edge_behav.wcfg new file mode 100644 index 0000000..4638332 --- /dev/null +++ b/project_tb_edge_behav.wcfg @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + tb_clk + tb_clk + + + tb_rst + tb_rst + + + tb_start + tb_start + + + tb_done + tb_done + + + tb_o_task_id[5:0] + tb_o_task_id[5:0] + + + tb_i_task_id[5:0] + tb_i_task_id[5:0] + + + tb_task_priority[1:0] + tb_task_priority[1:0] + + + tb_op[1:0] + tb_op[1:0] + + + tb_o_mem_addr[15:0] + tb_o_mem_addr[15:0] + + + tb_o_mem_data[7:0] + tb_o_mem_data[7:0] + + + tb_o_mem_we + tb_o_mem_we + + + tb_o_mem_en + tb_o_mem_en + + + tb_i_mem_data[7:0] + tb_i_mem_data[7:0] + + + state + state + + + [0][7:0] + [0][7:0] + + + [1][7:0] + [1][7:0] + + + [2][7:0] + [2][7:0] + + + [3][7:0] + [3][7:0] + + + [4][7:0] + [4][7:0] + + + number_of_task[7:0] + number_of_task[7:0] + + + current_task_addr[15:0] + current_task_addr[15:0] + + + ctrl_mem_data[7:0] + ctrl_mem_data[7:0] + + diff --git a/project_tb_edge_behav1.wcfg b/project_tb_edge_behav1.wcfg new file mode 100644 index 0000000..e73fcc4 --- /dev/null +++ b/project_tb_edge_behav1.wcfg @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + tb_clk + tb_clk + + + tb_rst + tb_rst + + + tb_start + tb_start + + + tb_done + tb_done + + + tb_op[1:0] + tb_op[1:0] + + + tb_i_task_id[5:0] + tb_i_task_id[5:0] + + + tb_task_priority[1:0] + tb_task_priority[1:0] + + + state + state + + + RAM + label + + + [0][7:0] + [0][7:0] + + + [1][7:0] + [1][7:0] + + + [2][7:0] + [2][7:0] + + + [3][7:0] + [3][7:0] + + + [4][7:0] + [4][7:0] + + + diff --git a/project_tb_edge_func_synth.wcfg b/project_tb_edge_func_synth.wcfg new file mode 100644 index 0000000..7e654c0 --- /dev/null +++ b/project_tb_edge_func_synth.wcfg @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + tb_clk + tb_clk + + + tb_rst + tb_rst + + + tb_start + tb_start + + + tb_done + tb_done + + + tb_o_task_id[5:0] + tb_o_task_id[5:0] + + + tb_task_priority[1:0] + tb_task_priority[1:0] + + + tb_op[1:0] + tb_op[1:0] + + + tb_i_task_id[5:0] + tb_i_task_id[5:0] + + + exc_o_mem_addr[15:0] + exc_o_mem_addr[15:0] + + + exc_o_mem_data[7:0] + exc_o_mem_data[7:0] + + + exc_o_mem_we + exc_o_mem_we + + + exc_o_mem_en + exc_o_mem_en + + + init_o_mem_addr[15:0] + init_o_mem_addr[15:0] + + + init_o_mem_data[7:0] + init_o_mem_data[7:0] + + + init_o_mem_we + init_o_mem_we + + + init_o_mem_en + init_o_mem_en + + + tb_o_mem_addr[15:0] + tb_o_mem_addr[15:0] + + + tb_o_mem_data[7:0] + tb_o_mem_data[7:0] + + + tb_o_mem_we + tb_o_mem_we + + + tb_o_mem_en + tb_o_mem_en + + + tb_i_mem_data[7:0] + tb_i_mem_data[7:0] + + + memory_control + memory_control + + + CLOCK_PERIOD + CLOCK_PERIOD + + + [0][7:0] + [0][7:0] + + + [1][7:0] + [1][7:0] + + + [2][7:0] + [2][7:0] + + + [3][7:0] + [3][7:0] + + + [4][7:0] + [4][7:0] + + + state[4:0] + state[4:0] + + + ctrl_done + ctrl_done + +