Aleandro/Progetto-reti-logiche
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Aleandro 259f6d5803 Initial commit
2026-06-12 20:37:03 +02:00
INFO
Initial commit
2026-06-12 20:37:03 +02:00
progetto_reti_logiche.cache
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2026-06-12 20:37:03 +02:00
progetto_reti_logiche.hw
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2026-06-12 20:37:03 +02:00
progetto_reti_logiche.ip_user_files
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2026-06-12 20:37:03 +02:00
progetto_reti_logiche.runs
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2026-06-12 20:37:03 +02:00
progetto_reti_logiche.sim/sim_1
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2026-06-12 20:37:03 +02:00
progetto_reti_logiche.srcs
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progetto_reti_logiche.xpr
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2026-06-12 20:37:03 +02:00
project_tb_behav.wcfg
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2026-06-12 20:37:03 +02:00
project_tb_edge_behav1.wcfg
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2026-06-12 20:37:03 +02:00
project_tb_edge_behav.wcfg
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2026-06-12 20:37:03 +02:00
project_tb_edge_func_synth.wcfg
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2026-06-12 20:37:03 +02:00
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99 MiB
Languages
Verilog 46.2%
C 35.7%
VHDL 9.6%
PureBasic 3%
TeX 2.8%
Other 2.6%