From 259f6d5803718e7a068c32b9d56d560df50ca398 Mon Sep 17 00:00:00 2001 From: aleandro Date: Fri, 12 Jun 2026 20:37:03 +0200 Subject: [PATCH] Initial commit --- INFO/PFRL_Regole_2526.md | 229 + INFO/PFRL_Specifiche_2526_V2.md | 660 ++ INFO/Relazione.tex | 793 +++ progetto_reti_logiche.cache/sim/ssm.db | 10 + progetto_reti_logiche.cache/wt/project.wpc | 4 + progetto_reti_logiche.cache/wt/synthesis.wdf | 52 + .../wt/synthesis_details.wdf | 3 + progetto_reti_logiche.cache/wt/webtalk_pa.xml | 21 + progetto_reti_logiche.cache/wt/xsim.wdf | 4 + .../progetto_reti_logiche.lpr | 7 + .../README.txt | 1 + .../.jobs/vrs_config_1.xml | 13 + .../.jobs/vrs_config_10.xml | 13 + .../.jobs/vrs_config_11.xml | 13 + .../.jobs/vrs_config_12.xml | 13 + .../.jobs/vrs_config_13.xml | 13 + .../.jobs/vrs_config_14.xml | 13 + .../.jobs/vrs_config_15.xml | 13 + .../.jobs/vrs_config_16.xml | 13 + .../.jobs/vrs_config_17.xml | 13 + .../.jobs/vrs_config_18.xml | 13 + .../.jobs/vrs_config_19.xml | 13 + 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5 + .../sim_1/synth/timing/xsim/compile.sh | 32 + .../sim_1/synth/timing/xsim/elaborate.log | 38 + .../sim_1/synth/timing/xsim/elaborate.sh | 26 + .../synth/timing/xsim/project_tb_edge.tcl | 11 + .../xsim/project_tb_edge_time_synth.sdf | 6313 +++++++++++++++++ .../timing/xsim/project_tb_edge_time_synth.v | 2905 ++++++++ .../xsim/project_tb_edge_time_synth.wdb | Bin 0 -> 185525 bytes .../timing/xsim/project_tb_edge_vhdl.prj | 6 + .../timing/xsim/project_tb_edge_vlog.prj | 6 + .../sim_1/synth/timing/xsim/simulate.log | 18 + .../sim_1/synth/timing/xsim/simulate.sh | 26 + .../sim_1/synth/timing/xsim/xelab.pb | Bin 0 -> 3730 bytes .../Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../obj/xsim_0.lnx64.o | Bin 0 -> 834560 bytes .../obj/xsim_1.lnx64.o | Bin 0 -> 563480 bytes .../obj/xsim_2.lnx64.o | Bin 0 -> 480 bytes .../project_tb_edge_time_synth/obj/xsim_3.c | 3006 ++++++++ .../obj/xsim_3.lnx64.o | Bin 0 -> 212352 bytes .../project_tb_edge_time_synth/xsim.dbg | Bin 0 -> 153496 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progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd create mode 100644 progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp create mode 100644 progetto_reti_logiche.xpr create mode 100644 project_tb_behav.wcfg create mode 100644 project_tb_edge_behav.wcfg create mode 100644 project_tb_edge_behav1.wcfg create mode 100644 project_tb_edge_func_synth.wcfg diff --git a/INFO/PFRL_Regole_2526.md b/INFO/PFRL_Regole_2526.md new file mode 100644 index 0000000..03ba76d --- /dev/null +++ b/INFO/PFRL_Regole_2526.md @@ -0,0 +1,229 @@ +Progetto di Reti Logiche + +Prof. Fornaciari, Prof. Palermo e Prof. Salice +Anno Accademico 2025 - 2026 + +REGOLE per lo svolgimento del progetto +(Aggiornamento del 27 Novembre 2025) + +Compito dello studente è quello di descrivere in VHDL e sintetizzare il componente HW che +implementa la specifica richiesta, interfacciandosi con una memoria dove sono memorizzati i +dati e dove andrà scritto il risultato finale. Allo studente verrà fornito un Test Bench di +esempio (che include la memoria) per validare il corretto funzionamento del modulo +implementato. + +● + +● + +Il progetto può essere svolto in gruppi composti da un massimo di 2 studenti che +debbono avere il medesimo docente di riferimento. +Il progetto è una attività autonoma che non coinvolge in nessun modo il corpo +docente a meno di chiarimenti sulla specifica di progetto. + +● Nel caso il testo di specifica risulti incompleto, è compito del gruppo di lavoro + +contattare i docenti motivando accuratamente la ragione della incompletezza. + +● Strumento di sintesi da usare è XILINX VIVADO WEBPACK e la FPGA target può +essere qualunque perchè il progetto è talmente piccolo che non ha problemi. +(Esempio: Artix-7 FPGA xc7a200tfbg484-1) + +Il progetto deve funzionare con un periodo di clock di almeno 20 ns; + +Criteri di valutazione + +● Un componente descritto e simulabile correttamente in pre-sintesi viene valutato fino + +ad un massimo di 24. + +● Un componente sintetizzabile e correttamente simulabile in post-sintesi può ottenere +una valutazione superiore a 24: fino a 30 per un progetto fatto in coppia, fino a 30L +per un progetto svolto da un singolo studente. + +● Lo studente deve allegare al progetto come documentazione una relazione. +Quest’ultima deve includere: 1) specifiche di progetto 2) scelte progettuali 3) risultati +dei test fatti e le ragioni di tali test (motivare le scelte) 4) risultati della sintesi. Nel +caso di un componente descritto e simulabile correttamente in pre-sintesi questo +deve essere chiaramente segnalato anche nella relazione. La qualità della relazione +concorre alla definizione del voto complessivo. +Il voto finale, in entrambi i casi, terrà conto dei test superati dal componente, dalla +qualità del codice VHDL e della relazione presentata (incluse le scelte progettuali). +Un progetto fatto in coppia può comunque raggiungere la lode grazie alla valutazione +complessiva dell’implementazione e della relazione. + +● + +● ATTENZIONE: non è possibile rifiutare il voto finale. Questo è dovuto alla +tipologia del progetto che è considerato, da regolamento didattico, una “PROVA +FINALE”. + +● E’ facoltà dei docenti richiedere un'integrazione mediante una discussione orale o +una prova pratica relativamente allo sviluppo del progetto nell'ambiente suggerito, in +aggiunta alla valutazione basata sulla prova di funzionamento del codice e della +relazione. + + Criteri di Consegna + +● La specifica del progetto resta invariata per tutto l’anno accademico. La consegna +del progetto può essere fatta solo una volta nell’arco dell’anno accademico con la +possibilità di una ed unica risottomissione in caso di insufficienza (si legga la nota +successiva). + +● + +● NOTA: nel caso che la prima consegna risulti insufficiente (9 0), esso +deve comportarsi come segue: + +● Dopo un reset, la lista deve essere considerata vuota. Il modulo deve quindi scrivere + +il valore zero all’indirizzo 0 della memoria. + +● Durante questa fase di inizializzazione, il segnale DONE deve essere mantenuto a 1, +indicando che il modulo non è ancora pronto a ricevere operazioni, e solo dopo che +l’azzeramento è stato effettuato, il modulo può riportare DONE a 0 e rendersi +disponibile a nuove operazioni. + +Il modulo deve garantire: + +Il corretto aggiornamento della memoria in seguito a ogni operazione. +Il mantenimento dell’ordine dei task nella lista. + +● +● +● La gestione appropriata dei casi limite, ad esempio lista vuota. +● + +Il rispetto del protocollo START-DONE come descritto. + +Si precisa che +la presente specifica descrive un comportamento completamente +deterministico: a parità di sequenze di ingresso, le uscite generate e il contenuto della +memoria nella parte valida (lista dei task) risultano invariati. Qualsiasi eventuale scenario +che presenti ambiguità o comportamenti non univocamente determinati dovrà essere +identificato e prontamente segnalato. + + Interfaccia del Componente +Il modulo da implementare ha 4 ingressi primari, uno ad 1 bit (i_start), uno a 6 bit (i_task_id), +uno a 2 bit (i_task_priority) e uno da 2 bit (i_op), e due uscite primarie, una da 1 bit (o_done) +e una da 6 bit (o_task_id). Inoltre, il modulo ha un segnale di clock CLK, unico per tutto il +sistema e un segnale di reset RESET anch’esso unico per tutto il sistema. Tutti i segnali +sono sincroni e devono essere interpretati sul fronte di salita del clock. L’unica eccezione è +RESET che, invece, è asincrono. RESET può essere generato in qualsiasi momento +dell’esecuzione. + +Il componente da descrivere deve avere la seguente interfaccia. + +entity project_reti_logiche is + +port ( + +i_clk : in std_logic; + +i_rst : in std_logic; + +i_start + +: in std_logic; + +i_task_id + +: in std_logic_vector(5 downto 0); + +i_task_priority : in std_logic_vector(1 downto 0); + +i_op : in std_logic_vector(1 downto 0); + +o_done : out std_logic; + +o_task_id : out std_logic_vector(5 downto 0); + +o_mem_addr : out std_logic_vector(15 downto 0); + +i_mem_data : in std_logic_vector(7 downto 0); + +o_mem_data : out std_logic_vector(7 downto 0); + +o_mem_we : out std_logic; + +o_mem_en : out std_logic + +); + +end project_reti_logiche; + +In particolare: + +● + +● +● + +● +● + +il nome del modulo deve essere project_reti_logiche e deve essere +presente una sola architettura per ogni entità; la violazione di queste +indicazioni comporta +il Test Bench e una +l’impossibilità di eseguire +conseguente valutazione di zero; +i_clk è il segnale di CLOCK in ingresso generato dal Test Bench; +i_rst è il segnale di RESET che inizializza la macchina pronta per ricevere il +primo segnale di START; +i_start è il segnale di START generato dal Test Bench; +i_task_id è il vettore di bit rappresentante il ID_TASK generato dal Test +Bench; + + ● + +● + +i_task_priority è il vettore di bit rappresentante il PRIORITY generato dal Test +Bench; +i_op è il vettore di 2 bit rappresentante l’operazione da dover effettuare sulla +lista di task; + +● o_done è il segnale DONE di uscita che comunica la fine dell’elaborazione; +● o_task_id è il vettore di bit rappresentante il ID_TASK del task a priorità più + +alta estratto dalla memoria; + +● o_mem_addr è il segnale (vettore) di uscita che manda l’indirizzo alla + +● + +memoria; +i_mem_data è il segnale (vettore) che arriva dalla memoria e contiene il dato +in seguito ad una richiesta di lettura; + +● o_mem_data è il segnale (vettore) che va verso la memoria e contiene il dato + +che verrà successivamente scritto; + +● o_mem_en è il segnale di ENABLE da dover mandare alla memoria per poter + +comunicare (sia in lettura che in scrittura); + +● o_mem_we è il segnale di WRITE ENABLE da dover mandare alla memoria + +(=1) per poter scriverci. Per leggere da memoria, esso deve essere 0. + + APPENDICE: Descrizione Memoria +NOTA: La memoria è già istanziata all’interno del Test Bench e non va sintetizzata + +La memoria e il suo protocollo può essere estratto dalla seguente descrizione VHDL che fa +parte del test bench e che è derivata dalla User guide di VIVADO disponibile al seguente +link: +https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug901-vivado-synth +esis.pdf + +-- Single-Port Block RAM Write-First Mode (recommended template) +-- +-- File: rams_02.vhd +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +entity rams_sp_wf is +port( + clk : in std_logic; + we : in std_logic; + en : in std_logic; + addr : in std_logic_vector(15 downto 0); + di : in std_logic_vector(7 downto 0); + do : out std_logic_vector(7 downto 0) +); +end rams_sp_wf; + +architecture syn of rams_sp_wf is +type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); +signal RAM : ram_type; +begin + process(clk) + +begin +if clk'event and clk = '1' then +if en = '1' then + if we = '1' then + +RAM(conv_integer(addr)) <= di; +do + +<= di after 2 ns; + + else + +do <= RAM(conv_integer(addr)) after 2 ns; + + end if; +end if; +end if; + end process; +end syn; + + ESEMPIO +L’esempio qui di seguito mostra il comportamento a seguito dei segnali di ingresso. Qui di +seguito è presente la situazione della memoria a seguito dell’inserimento di diversi task (fase +non mostrata nell’esempio). I valori non espliciti sono valori di memoria che non vengono +considerati per il normale funzionamento. + +SITUAZIONE INIZIALE (6 task già in tabella) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01000000 + +0x01011000 + +0x01011100 + +0x01010101 + +0x01110010 + +0x00010011 + +16 + +22 + +23 + +21 + +28 + +4 + +0 + +0 + +0 + +1 + +2 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +OPERAZIONE: 00 (incremento valore di priorità) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01000001 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01110011 + +0x00010011 + +16 + +22 + +23 + +21 + +28 + +4 + +1 + +1 + +1 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + + OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 19 - PRIORITY: 2 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000111 + +0x01000001 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01001110 + +0x01110011 + +0x00010011 + +16 + +22 + +23 + +21 + +19 + +28 + +4 + +1 + +1 + +1 + +2 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +8 + +OPERAZIONE: 01 (rimuove il primo task) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000110 + +0x01011001 + +0x01011101 + +0x01010110 + +0x01001110 + +0x01110011 + +0x00010011 + +22 + +23 + +21 + +19 + +28 + +4 + +1 + +1 + +2 + +2 + +3 + +3 + +0 + +1 + +2 + +3 + +4 + +5 + +6 + +7 + + OPERAZIONE: 11 (svuota la lista) + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000000 + +0 + +1 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 31 - PRIORITY: 3 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000001 + +0x01111111 + +0 + +1 + +2 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 15 - PRIORITY: 0 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0x00000010 + +0x00111100 + +0x01111111 + +15 + +31 + +0 + +3 + +0 + +1 + +2 + +3 + +OPERAZIONE: 10 (aggiunge un task) - ID_TASK: 20 - PRIORITY: 0 + +MEMORIA + +INDIRIZZO + +VALORE + +ID_TASK PRIORITY + +0 + +1 + +2 + +3 + +0x000000011 + +0x00111100 + +0x01010000 + +0x01111111 + +15 + +20 + +31 + +0 + +0 + +3 + + Progetto di Reti Logiche + +Prof. Fornaciari, Prof. Palermo e Prof. Salice +Anno Accademico 2025 - 2026 + +NOTE DI AGGIORNAMENTO DELLA SPECIFICA + +In questa pagina potete trovare le modifiche fatte alla specifica del progetto dal suo primo rilascio. +Tutti i cambiamenti con data annessa saranno riportati qui sotto e sono mantenuti in rosso nel testo. + +Errata Corrige: + +- Aggiornamento 24.02.2026: + +- + +Il numero massimo di task nella lista non è 31 come nella versione originale ma 63. +Questo è derivato dal fatto che il numero di bit per il task_id è 6. + diff --git a/INFO/Relazione.tex b/INFO/Relazione.tex new file mode 100644 index 0000000..84ea047 --- /dev/null +++ b/INFO/Relazione.tex @@ -0,0 +1,793 @@ +\documentclass[12pt,a4paper]{article} + +% --- Preambolo --- +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} +\usepackage[italian]{babel} +\usepackage{amsmath, amsfonts, amssymb} +\usepackage{geometry} +\usepackage{graphicx} +\usepackage{listings} +\usepackage{xcolor} +\usepackage{lstautogobble} + +\usepackage{booktabs} +\usepackage{xcolor} +\usepackage{colortbl} +\usepackage{float} + +\usepackage{caption} + +\usepackage{hyperref} +\hypersetup{ + colorlinks=false, + pdfborder={0 0 0} +} + + +\geometry{a4paper, margin=3cm} + +% Configurazione professionale per il codice VHDL +\lstset{ + language=VHDL, + basicstyle=\ttfamily\small, % Font monospaziato piccolo + keywordstyle=\color{blue}, % Parole chiave in blu + commentstyle=\color{gray}, % Commenti in grigio + breaklines=true, % VA A CAPO AUTOMATICAMENTE + frame=single, % Bordo attorno al codice + numbers=left, % Numeri di riga a sinistra + numberstyle=\tiny\color{gray}, + xleftmargin=10pt, % Margine per far rientrare i numeri di riga + showstringspaces=false, + autogobble=true, + tabsize=2, +} + +\begin{document} + + \begin{titlepage} + \centering + {\large \textbf{POLITECNICO DI MILANO 1863}} \\ + \vspace{1cm} + \includegraphics[width=0.4\textwidth]{logo_polimi.jpg} \\ + \vspace{2cm} + + {\Large \textbf{Relazione Progetto Reti Logiche}} \\ + \vspace{1cm} + + {\large Aleandro Pagani} \\ + \vspace{0.5cm} + {\large Giugno 2026} \\ + + \vfill + + {\large Matricola: 236992} \\ + {\large Codice persona: 10893566} \\ + \vspace{1cm} + {\large Professore: Fabio Salice} + \end{titlepage} + + \newpage + + \pagenumbering{roman} + \tableofcontents + \newpage + + + + \pagenumbering{arabic} + \section{Introduzione} + \subsection{Specifiche generali} + \subsubsection{Descrizione} + + Il progetto consiste nel descrivere un modulo hardware che si interfaccia con una memoria in cui la prima cella contiene il contatore dei task e le celle successive la lista ordinata. Il modulo deve supportare quattro tipi di operazioni il cui codice identificativo è fornito in ingresso: + \begin{itemize} + \item \textbf{00}: Decrementa la priorità di tutti i task + \item \textbf{01}: Rimuove il primo task della lista + \item \textbf{10}: Aggiunge un nuovo task in lista + \item \textbf{11}: Svuota completamente la lista + \end{itemize} + +\begin{figure}[H] + \centering + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_00.png} + \caption*{OP 00.} + \label{fig:00} + \end{minipage} + \hfill + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_01.png} + \caption*{OP 01.} + \label{fig:01} + \end{minipage} +\end{figure} + +\begin{figure}[H] + \centering + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_10.png} + \caption*{OP 10 (inserisco task 000000 01).} + \label{fig:10} + \end{minipage} + \hfill + \begin{minipage}{0.45\textwidth} + \centering + \includegraphics[width=\textwidth]{INTRODUZIONE/OP_11.png} + \caption*{OP 11.} + \label{fig:11} + \end{minipage} + \end{figure} + + \newpage + + + + + + + + \subsubsection{Funzionamento} + La sincronizzazione tra la logica esterna e il modulo hardware avviene tramite un protocollo di handshake \textbf{START-DONE}. + Il funzionamento del modulo è scandito attraverso 5 fasi: + \begin{itemize} + \item \textbf{Inizializzazione:} Vengono forniti i dati e posto il segnale \textbf{START} a 1. + \item \textbf{Elaborazione:} Il modulo avvia le operazioni e interagisce con la memoria. + \item \textbf{Completamento:} Terminate le operazioni, il modulo imposta il segnale \textbf{DONE} a 1. + \item \textbf{Riconoscimento:} La logica esterna pone il segnale \textbf{START} a 0. + \item \textbf{Ripristino:} Il modulo riporta il segnale \textbf{DONE} a 0 e torna in attesa di nuove direttive. + \end{itemize} + + \vspace{0.5cm} + \centerline{\includegraphics[width=0.6\textwidth]{START-DONE handshake.png}} + \newpage + + + + + + + + + + + + + + \subsection{Descrizione modulo} + + \begin{lstlisting} + entity project_reti_logiche is + port ( + i_clk: in std_logic; + i_rst: in std_logic; + + i_start: in std_logic; + i_task_id: in std_logic_vector(5 downto 0); + i_task_priority : in std_logic_vector(1 downto 0); + i_op: in std_logic_vector(1 downto 0); + + o_done: out std_logic; + o_task_id: out std_logic_vector(5 downto 0); + + o_mem_addr : out std_logic_vector(15 downto 0); + i_mem_data : in std_logic_vector(7 downto 0); + o_mem_data : out std_logic_vector(7 downto 0); + o_mem_we: out std_logic; + o_mem_en: out std_logic + ); + end project_reti_logiche; + \end{lstlisting} + + \begin{itemize} + \item \textbf{i\_clk:} Segnale di clock + \item \textbf{i\_rst:} Segnale di reset + \vspace{0.5cm} + \item \textbf{i\_start:} Segnale \textbf{START} di handshake + \item \textbf{i\_task\_id:} Codice del task da inserire + \item \textbf{i\_task\_priority:} Priorità del task da inserire + \item \textbf{i\_op:} ID dell'operazione da eseguire + \vspace{0.5cm} + \item \textbf{o\_done:} Segnale \textbf{DONE} di handshake + \item \textbf{o\_task\_id:} Codice del task restituito dall'eliminazione + \vspace{0.5cm} + \item \textbf{o\_mem\_addr:} Indirizzo di memoria con cui interagire + \item \textbf{i\_mem\_data:} Informazioni lette dalla memoria + \item \textbf{o\_mem\_data:} Informazioni da scrivere in memoria + \item \textbf{o\_mem\_we:} Flag per abilitare la scrittura in memoria + \item \textbf{o\_mem\_en:} Flag per abilitare la lettura in memoria + \end{itemize} + \newpage + + + + + + \subsection{Descrizione memoria} + \subsubsection{Implementazione fornita} + \begin{lstlisting} + library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + + entity rams_sp_wf is + port( + clk : in std_logic; + we : in std_logic; + en : in std_logic; + addr : in std_logic_vector(15 downto 0); + di : in std_logic_vector(7 downto 0); + do : out std_logic_vector(7 downto 0) + ); + end rams_sp_wf; + + architecture syn of rams_sp_wf is + type ram_type is array (65535 downto 0) of std_logic_vector(7 downto 0); + signal RAM : ram_type; + begin + process(clk) + begin + if clk'event and clk = '1' then + if en = '1' then + if we = '1' then + RAM(conv_integer(addr)) <= di; + do <= di; -- Write-First + else + do <= RAM(conv_integer(addr)); + end if; + end if; + end if; + end process; + end syn; + \end{lstlisting} + + \begin{itemize} + \item \textbf{clk:} Segnale di clock + \item \textbf{we:} Flag di scrittura + \item \textbf{en:} Flag di lettura + \item \textbf{addr:} Indirizzo con cui interagire + \item \textbf{di:} Dati in ingresso + \item \textbf{do:} Dati in uscita + \end{itemize} + \newpage + + \subsubsection{Layout di memoria} + La RAM indirizza 65536 celle da un byte (indirizzi a 16 bit); la lista ne utilizza al più 64: la prima (\textbf{0}) rappresenta il numero di task presenti, le successive contengono i task (al massimo 63, dato che gli ID sono a 6 bit e l'ID 0 è riservato).\\ + Per ogni task, i primi 6 bit ne identificano il codice, mentre gli ultimi 2 la priorità. + \vspace{0.7cm} + + + \begin{minipage}[c]{0.30\textwidth} + \centering + \includegraphics[width=\textwidth]{MemoryDiagram.png} + \end{minipage} + \hfill + \begin{minipage}[c]{0.60\textwidth} + + In questo esempio abbiamo 3 task: + \begin{itemize} + \item \textbf{001111 00:} Task con codice 15 e priorità 0 + \item \textbf{010100 00:} Task con codice 20 e priorità 0 + \item \textbf{011011 11:} Task con codice 27 e priorità 3 + \end{itemize} + Tutti gli altri elementi in memoria non vengono considerati validi. + \end{minipage} + \newpage + + + + + + + + + + + + + + + + + \section{Architettura} + Data la dimensione ridotta del progetto, il componente è composto da un unico modulo con due processi: uno sincrono e uno combinatorio. + + Nell'implementazione presentata è stata privilegiata la leggibilità rispetto all'efficienza e alla minimizzazione del numero di segnali. + + \subsection{Segnali interni} + \begin{lstlisting} + signal state : state_type; + signal next_state : state_type; + + signal current_mem_addr : std_logic_vector(15 downto 0); + signal next_mem_addr : std_logic_vector(15 downto 0); + + signal current_task_count : std_logic_vector(7 downto 0); + signal next_task_count : std_logic_vector(7 downto 0); + + signal current_popped_id : std_logic_vector(5 downto 0); + signal next_popped_id : std_logic_vector(5 downto 0); + + signal ctrl_done : std_logic; + signal ctrl_mem_en : std_logic; + signal ctrl_mem_we : std_logic; + signal ctrl_mem_data : std_logic_vector(7 downto 0); + signal ctrl_task_id : std_logic_vector(5 downto 0); + \end{lstlisting} + + I registri interni sono organizzati in coppie \textbf{current\_*}/\textbf{next\_*}: il processo combinatorio calcola il valore \textbf{next\_*}, il processo sincrono lo registra in \textbf{current\_*} sul fronte di clock. + + \begin{itemize} + \item \textbf{state:} Stato attuale dell'FSM + \item \textbf{next\_state:} Prossimo stato dell'FSM + \vspace{0.5cm} + \item \textbf{current\_mem\_addr / next\_mem\_addr:} Indirizzo di memoria su cui la FSM sta lavorando (0 = contatore, 1..N = task) + \item \textbf{current\_task\_count / next\_task\_count:} Copia locale del numero di task presenti in lista (cella 0 della memoria) + \item \textbf{current\_popped\_id / next\_popped\_id:} ID estratto dall'ultima rimozione, presentato su \textbf{o\_task\_id} quando \textbf{DONE} viene alzato + \vspace{0.5cm} + \item \textbf{ctrl\_done:} Segnale di controllo di \textbf{DONE} + \item \textbf{ctrl\_mem\_en:} Segnale per abilitare la lettura in memoria + \item \textbf{ctrl\_mem\_we:} Segnale per abilitare la scrittura in memoria + \item \textbf{ctrl\_mem\_data:} Dati da scrivere in memoria + \item \textbf{ctrl\_task\_id:} Valore da presentare sull'uscita \textbf{o\_task\_id} + \end{itemize} + + \subsection{Processo sincrono} + Questo processo registra sul fronte di salita del clock lo stato, i registri e tutte le uscite del modulo. + \begin{lstlisting} + process(i_clk, i_rst) + begin + if i_rst = '1' then + state <= S_RESET; + o_done <= '1'; + o_mem_en <= '0'; + o_mem_we <= '0'; + elsif rising_edge(i_clk) then + state <= next_state; + current_mem_addr <= next_mem_addr; + current_task_count <= next_task_count; + current_popped_id <= next_popped_id; + + o_done <= ctrl_done; + o_mem_en <= ctrl_mem_en; + o_mem_we <= ctrl_mem_we; + o_mem_addr <= next_mem_addr; + o_mem_data <= ctrl_mem_data; + o_task_id <= ctrl_task_id; + end if; + end process; + \end{lstlisting} + Sul fronte di salita del clock i registri \textbf{current\_*} vengono aggiornati con i corrispettivi valori \textbf{next\_*} e, contemporaneamente, vengono scritti sui bus di uscita \textbf{o\_*} i valori calcolati dal processo combinatorio. + + Il reset, asincrono, porta la FSM in \textbf{S\_RESET} con \textbf{DONE} a 1 (come richiesto dalla specifica) e disabilita l'interfaccia verso la memoria: in questo modo il modulo non può produrre scritture involontarie mentre il reset è attivo, indipendentemente dall'istante in cui arriva. + + \vspace{0.5cm} + Due scelte progettuali meritano attenzione: + \begin{itemize} + \item \textbf{Uscite registrate:} I segnali interni \textbf{ctrl\_*} vengono assegnati alle uscite \textbf{o\_*} solo nel processo sincrono: oltre a separare la logica di controllo dall'aggiornamento delle uscite, questo garantisce che i segnali verso la memoria siano privi di glitch. + \item \textbf{Indirizzo anticipato:} \textbf{o\_mem\_addr} viene registrato da \textbf{next\_mem\_addr} (e non da \textbf{current\_mem\_addr}): l'indirizzo arriva così alla memoria con un ciclo di anticipo rispetto allo stato che ne consumerà il dato. Poiché la memoria ha lettura sincrona con latenza di un ciclo, questa convenzione permette a ogni stato di richiedere una lettura e allo stato successivo (dopo un solo ciclo "cuscinetto") di usarne il risultato. + \end{itemize} + \newpage + + \subsection{Processo combinatorio} + Questo è il processo principale del modulo hardware: esso è responsabile della logica interna e della gestione degli stati FSM.\\ + Vengono di seguito analizzati tutti gli stati presenti. + + + \begin{lstlisting} + type state_type is ( + S_IDLE, S_RESET, S_DONE, + + S_00_READ, S_00_WAIT, S_00_CHECK, S_00_GO_NEXT, + + S_01_CHECK_NUMBER, S_01_WAIT, S_01_WRITE, S_01_CHECK_END, S_01_COPY, S_01_GO_NEXT, S_01_WAIT_FOR_COUNT, + + S_10_PLACE_AT_START, S_10_WAIT_FOR_CHECK, S_10_CHECK_ID, S_10_WAIT, S_10_COMPARE, S_10_GO_NEXT, S_10_UPDATE_COUNT, S_10_WAIT_FOR_COUNT, + + S_11_UPDATE_COUNT, S_11_WAIT_FOR_COUNT + ); + \end{lstlisting} + + \subsubsection{Stati di gestione del protocollo} + \begin{itemize} + \item \textbf{S\_IDLE:} Stato di attesa. Quando viene rilevato il segnale \textbf{START=1}, viene avviata l'operazione indicata dal codice \textbf{i\_op}. Al dispatch viene anche azzerato il registro \textbf{popped\_id}, così \textbf{o\_task\_id} varrà 0 per ogni operazione diversa da una rimozione andata a buon fine. + \item \textbf{S\_RESET:} Stato di reset. Imposta il contatore nella prima cella di memoria a 0, invalidando tutte le altre, mentre \textbf{DONE} rimane a 1 come richiesto dalla specifica. + \item \textbf{S\_DONE:} Alza \textbf{DONE} e lo tiene a 1 finché \textbf{START} non torna a 0, come richiesto dal protocollo di handshake. Tutte le operazioni raggiungono questo stato un ciclo dopo il proprio stato terminale: \textbf{DONE} sale quindi sempre \emph{dopo} il commit in memoria dell'ultima scrittura, e la logica esterna che campiona la memoria sul fronte di \textbf{DONE} legge dati già aggiornati. + \end{itemize} + \newpage + + \subsubsection{Operazione 00} + Questa operazione decrementa la priorità di tutti i task presenti in lista. + Se un task ha già la priorità minima \textbf{11}, questa non viene modificata. + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.4\textwidth]{DIAGRAMS/S_00_DIAGRAM.png}} + + \vspace{0.5cm} + Gli stati presenti sono 4: + \begin{itemize} + \item \textbf{S\_00\_READ:} Seleziona il primo elemento in lista + \item \textbf{S\_00\_WAIT:} Stato cuscinetto. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato + \item \textbf{S\_00\_CHECK:} Controlla se l'indirizzo selezionato è un task valido. In tal caso, se possibile, ne incrementa la priorità numerica di 1. + \item \textbf{S\_00\_GO\_NEXT:} Seleziona la cella di memoria successiva + \end{itemize} + \newpage + + \subsubsection{Operazione 01} + Questa operazione rimuove il primo task della lista e sposta in alto tutti i task sottostanti. + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_01_DIAGRAM.png}} + + \vspace{0.5cm} + Gli stati presenti sono 7: + \begin{itemize} + \item \textbf{S\_01\_CHECK\_NUMBER:} Se non ci sono task termina subito (\textbf{o\_task\_id} resterà \textbf{000000}). Altrimenti avvia la lettura del primo task. + \item \textbf{S\_01\_WAIT:} Stato cuscinetto. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato + \item \textbf{S\_01\_WRITE:} Salva l'ID del primo task nel registro \textbf{popped\_id} (verrà presentato su \textbf{o\_task\_id} in \textbf{S\_DONE}) e avvia la lettura del task successivo. + \item \textbf{S\_01\_CHECK\_END:} Controlla se ha raggiunto la fine della lista. In tal caso scrive nella prima cella il valore del contatore decrementato di uno. + \item \textbf{S\_01\_COPY:} Copia il contenuto della cella \textbf{n+1} dentro alla cella \textbf{n}. + \item \textbf{S\_01\_GO\_NEXT:} Passa al task successivo. + \item \textbf{S\_01\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + \end{itemize} + \newpage + + \subsubsection{Operazione 10} + Questa operazione inserisce un nuovo task nella posizione corretta secondo la sua priorità, in coda ai task di pari priorità. L'operazione è divisa in due fasi: + \begin{enumerate} + \item \textbf{Scansione duplicati:} la lista viene percorsa dall'ultimo task verso il primo; se viene trovato un task con lo stesso ID, l'inserimento viene ignorato (la specifica vieta la presenza di due task con lo stesso ID). Vengono inoltre scartate immediatamente le richieste con ID = 0, valore riservato dalla specifica come condizione di errore. + \item \textbf{Inserimento dal fondo:} partendo dall'ultimo task e salendo, viene controllata la priorità del task corrente. Se questa risulta numericamente maggiore (gerarchicamente inferiore) rispetto a quella del task da inserire, la cella viene copiata in quella sottostante e il confronto prosegue verso l'alto. Contrariamente, se la priorità dovesse risultare minore o uguale, il nuovo task viene inserito nella cella sottostante: il confronto "minore o uguale" è ciò che colloca il nuovo task \emph{dopo} quelli di pari priorità, garantendo l'ordine FIFO richiesto. + \end{enumerate} + + Si fa notare come il caso limite di lista piena non può verificarsi: con ID a 6 bit e ID = 0 escluso esistono al più 63 task distinti, e un 64-esimo inserimento sarebbe necessariamente un duplicato, quindi ignorato dalla fase di scansione. + + \vspace{0.5cm} + Di seguito viene illustrato un esempio di inserimento del task \textbf{011110 01}. + + Nota: la scansione iniziale per identificare i duplicati viene ignorata nell'esempio. + + \begin{itemize} + + \item L’ultimo task presenta una priorità gerarchicamente minore, di conseguenza viene copiato nella cella sottostante. + + \includegraphics[width=0.7\textwidth]{S_10_EXAMPLE/S_10_ITERATION1.png} + + \item Si passa quindi al task soprastante. Anche questo presenta una priorità inferiore e viene pertanto copiato nella cella sottostante. + + \includegraphics[width=0.7\textwidth]{S_10_EXAMPLE/S_10_ITERATION2.png} + + \item Il task nella cella 1 presenta invece una priorità maggiore o uguale: il nuovo task viene quindi inserito nella cella sottostante. + + \includegraphics[width=0.87\textwidth]{S_10_EXAMPLE/S_10_ITERATION3.png} + + \item Infine, viene aggiornato il contatore. + + \end{itemize} + \newpage + + + + + \vspace{0.5cm} + + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_10_DIAGRAM.png}} + \vspace{0.5cm} + Gli stati presenti sono 8: + \begin{itemize} + \item \textbf{S\_10\_PLACE\_AT\_START:} Scarta le richieste con ID = 0 e avvia la scansione duplicati dall'ultimo task della lista. + + \item \textbf{S\_10\_WAIT\_FOR\_CHECK:} Stato cuscinetto della fase di scansione. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato. + + \item \textbf{S\_10\_CHECK\_ID:} Confronta l'ID del task letto con quello da inserire. Se coincidono, l'operazione termina senza modifiche; se la scansione ha raggiunto la cima della lista, rilegge l'ultimo task e passa alla fase di inserimento; altrimenti prosegue la scansione verso l'alto. + + \item \textbf{S\_10\_WAIT:} Stato cuscinetto della fase di inserimento. Serve per dare tempo alla RAM di leggere il contenuto del task selezionato. + + \item \textbf{S\_10\_COMPARE:} Verifica la condizione di inserimento del nuovo task. + Se tutta la lista è stata scorsa (o era vuota), il nuovo task viene scritto in testa. + In caso contrario, se il task da inserire presenta una priorità numericamente maggiore o uguale rispetto al task corrente, viene scritto nella cella sottostante; + se invece presenta una priorità numericamente minore, è il task corrente a venire copiato nella cella sottostante. + + \item \textbf{S\_10\_GO\_NEXT:} Seleziona il task precedente nella lista, da confrontare al giro successivo. + + \item \textbf{S\_10\_UPDATE\_COUNT:} Aggiorna il contatore con il numero totale di task presenti nella lista. + + \item \textbf{S\_10\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + + \end{itemize} + \newpage + + + \subsubsection{Operazione 11} + Questa operazione svuota completamente la lista impostando il contatore dei task a 0 (non è necessario resettare tutti i valori nella memoria). + + \vspace{0.5cm} + \centerline{\includegraphics[width=0.7\textwidth]{DIAGRAMS/S_11_DIAGRAM.png}} + \vspace{0.5cm} + Gli stati presenti sono 2: + \begin{itemize} + \item \textbf{S\_11\_UPDATE\_COUNT:} Imposta il contatore a 0. + + \item \textbf{S\_11\_WAIT\_FOR\_COUNT:} Attende il commit della scrittura del contatore, poi transita in \textbf{S\_DONE}. + + \end{itemize} + + + + + + + + + \newpage + \section{Risultati sperimentali} + \subsection{Report di sintesi} + \subsubsection{Risorse utilizzate} + La seguente tabella mostra le risorse hardware occupate dal design sul dispositivo target Artix-7 FPGA xc7a200tfbg484-1. L'utilizzo è estremamente contenuto: le Slice LUT occupano solo lo 0.13\% delle risorse disponibili e i registri lo 0.03\%, confermando che il modulo è decisamente leggero. Inoltre, non è stato inferito alcun latch: tutti gli elementi di memoria sono flip-flop, a conferma che il processo combinatorio assegna un valore di default a ogni segnale in ogni ramo. + + \begin{table}[H] + \centering + \caption{Risorse utilizzate -- Slice Logic} + \label{tab:utilization} + \begin{tabular}{lrrrrr} + \toprule + \textbf{Site Type} & \textbf{Used} & \textbf{Fixed} & \textbf{Prohibited} & \textbf{Available} & \textbf{Util\%} \\ + \midrule + Slice LUTs* & 181 & 0 & 0 & 134600 & 0.13 \\ + \quad LUT as Logic & 181 & 0 & 0 & 134600 & 0.13 \\ + \quad LUT as Memory & 0 & 0 & 0 & 46200 & 0.00 \\ + Slice Registers & 71 & 0 & 0 & 269200 & 0.03 \\ + \quad Register as Flip Flop & 71 & 0 & 0 & 269200 & 0.03 \\ + \quad Register as Latch & 0 & 0 & 0 & 269200 & 0.00 \\ + F7 Muxes & 0 & 0 & 0 & 67300 & 0.00 \\ + F8 Muxes & 0 & 0 & 0 & 33650 & 0.00 \\ + Unique Control Sets & 6 & -- & 0 & 33650 & 0.02 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + \subsubsection{FSM codificata} + La tabella riporta la codifica degli stati FSM generata automaticamente dal tool di sintesi. Sono presenti in totale 24 stati. Vivado ha scelto una codifica \textbf{one-hot} (un flip-flop per stato, 24 bit complessivi), tipica sulle FPGA: aumenta il numero di registri, risorsa abbondante, ma minimizza la logica di decodifica dello stato e ne accorcia i percorsi combinatori. Per compattezza la tabella riporta, per ogni stato, l'indice del bit attivo della codifica one-hot e la codifica sequenziale a 5 bit di partenza. + \begin{table}[H] + \caption{FSM -- Codifica degli stati} + \label{tab:fsm-encoding} + \centering + \begin{tabular}{lcc} + \toprule + \textbf{Stato} & \textbf{One-hot (bit attivo)} & \textbf{Previous Encoding} \\ + \midrule + \texttt{s\_reset} & 0 & 00001 \\ + \texttt{s\_done} & 1 & 00010 \\ + \texttt{s\_idle} & 2 & 00000 \\ + \texttt{s\_00\_read} & 3 & 00011 \\ + \texttt{s\_00\_wait} & 4 & 00100 \\ + \texttt{s\_00\_check} & 5 & 00101 \\ + \texttt{s\_00\_go\_next} & 6 & 00110 \\ + \texttt{s\_01\_check\_number} & 7 & 00111 \\ + \texttt{s\_01\_wait} & 8 & 01000 \\ + \texttt{s\_01\_write} & 9 & 01001 \\ + \texttt{s\_01\_check\_end} & 10 & 01010 \\ + \texttt{s\_01\_wait\_for\_count}& 11 & 01101 \\ + \texttt{s\_01\_copy} & 12 & 01011 \\ + \texttt{s\_01\_go\_next} & 13 & 01100 \\ + \texttt{s\_10\_place\_at\_start}& 14 & 01110 \\ + \texttt{s\_10\_wait\_for\_check}& 15 & 01111 \\ + \texttt{s\_10\_check\_id} & 16 & 10000 \\ + \texttt{s\_10\_wait} & 17 & 10001 \\ + \texttt{s\_10\_compare} & 18 & 10010 \\ + \texttt{s\_10\_update\_count} & 19 & 10100 \\ + \texttt{s\_10\_wait\_for\_count}& 20 & 10101 \\ + \texttt{s\_10\_go\_next} & 21 & 10011 \\ + \texttt{s\_11\_update\_count} & 22 & 10110 \\ + \texttt{s\_11\_wait\_for\_count}& 23 & 10111 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + + \subsubsection{Statistiche RTL} + La tabella dettaglia i componenti RTL inferiti dal tool di sintesi a partire dal codice VHDL. Sono presenti sommatori a 16, 9 e 8 bit per l'aritmetica su indirizzi, priorità e contatore. I registri a 16, 8, 6 e 1 bit corrispondono ai segnali interni e alle uscite registrate del design. I multiplexer a 24 ingressi riflettono la selezione tra i 24 stati della FSM (quelli a 24 bit operano sulla codifica one-hot dello stato). + \begin{table}[H] + \caption{Statistiche RTL -- Componenti} + \label{tab:rtl-stats} + \centering + \small + \begin{tabular}{rlrl} + \toprule + \textbf{Ingressi} & \textbf{Bit} & \textbf{Tipo} & \textbf{Quantità} \\ + \midrule + \multicolumn{4}{l}{\textit{Adders}} \\ + 2 & 16 bit & Adder & 4 \\ + 2 & 9 bit & Adder & 1 \\ + 2 & 8 bit & Adder & 3 \\ + \midrule + \multicolumn{4}{l}{\textit{Registers}} \\ + -- & 16 bit & Register & 1 \\ + -- & 8 bit & Register & 2 \\ + -- & 6 bit & Register & 2 \\ + -- & 1 bit & Register & 3 \\ + \midrule + \multicolumn{4}{l}{\textit{Muxes}} \\ + 24 & 24 bit & Mux & 1 \\ + 4 & 24 bit & Mux & 1 \\ + 2 & 24 bit & Mux & 7 \\ + 2 & 16 bit & Mux & 3 \\ + 24 & 16 bit & Mux & 1 \\ + 2 & 8 bit & Mux & 4 \\ + 24 & 8 bit & Mux & 2 \\ + 2 & 6 bit & Mux & 1 \\ + 24 & 6 bit & Mux & 2 \\ + 2 & 1 bit & Mux & 1 \\ + 24 & 1 bit & Mux & 6 \\ + \bottomrule + \end{tabular} + \end{table} + \newpage + + + + \subsubsection{Timing} + La specifica richiede che il progetto funzioni con un periodo di clock di almeno 20 ns. Il requisito è stato verificato in sintesi applicando il vincolo \texttt{create\_clock -period 20.000} sul segnale \texttt{i\_clk}: + + \begin{table}[H] + \centering + \caption{Design Timing Summary (periodo di clock 20 ns)} + \label{tab:timing} + \begin{tabular}{lrr} + \toprule + \textbf{Metrica} & \textbf{Slack (ns)} & \textbf{Endpoint in violazione} \\ + \midrule + Worst Negative Slack (setup, WNS) & $+14.786$ & 0 / 114 \\ + Worst Hold Slack (WHS) & $+0.149$ & 0 / 114 \\ + Worst Pulse Width Slack (WPWS) & $+9.500$ & 0 / 72 \\ + \bottomrule + \end{tabular} + \end{table} + + Lo slack di setup ampiamente positivo indica che il percorso critico è di circa 5.2 ns: il modulo rispetta il vincolo dei 20 ns con un margine di quasi 4 volte. La correttezza funzionale del circuito sintetizzato è inoltre confermata dalla simulazione post-sintesi (functional) di tutti i test bench descritti nella sezione successiva. + \newpage + + \subsection{Report di simulazioni} + \subsubsection{Test bench 1} + Il test bench di esempio fornito dal docente copre le operazioni base quali reset, inserimento in lista, rimozione dalla lista, decremento di priorità e svuotamento della lista. + + Seppur non vengano coperti molti casi limite, questo test bench ci offre la possibilità di analizzare facilmente i tempi di esecuzione delle singole operazioni. + Le 10 operazioni, infatti, vengono eseguite correttamente in 2540 ns.\\ + In particolar modo, le latenze in cicli di clock (periodo 20 ns), con \textbf{N} task presenti in lista e \textbf{k} task spostati, sono le seguenti: + \begin{itemize} + \item \textbf{OP 00}: $(4 + 3N) \cdot 20\,$ns + \item \textbf{OP 01}: $(6 + 3k) \cdot 20\,$ns, con $k = N - 1$; lista vuota: $2 \cdot 20\,$ns + \item \textbf{OP 10}: $(6 + 2\max(N,1) + 3k) \cdot 20\,$ns + \item \textbf{OP 11}: $3 \cdot 20\,$ns + \end{itemize} + + Nota: nell'operazione \textbf{10} il termine $2\max(N,1)$ è il costo della scansione duplicati, che percorre sempre l'intera lista, mentre $3k$ è il costo degli spostamenti, con $k$ compreso tra 0 (inserimento in fondo) e $N$ (inserimento in testa). + Per caratterizzare il comportamento medio, si considera una distribuzione delle priorità equiprobabile: $E[T] = \left(6 + \frac{25}{8}N\right) \cdot 20\,$ns. + + Tutte le formule sono state verificate al ciclo esatto da un test bench dedicato (par. 3.2.3). + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/RESET.png} + \caption{Operazione di reset.} + \label{fig:reset} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/INSERIMENTO_VUOTA.png} + \caption{Operazione di inserimento in lista vuota.} + \label{fig:insert_empty} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/SVUOTA.png} + \caption{Operazione di svuotamento della lista.} + \label{fig:empty} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/INSERIMENTO_PIENA.png} + \caption{Operazione di inserimento in lista popolata.} + \label{fig:insert_full} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/RIMOZIONE.png} + \caption{Operazione di rimozione di un task.} + \label{fig:remove} + \end{figure} + + \begin{figure}[H] + \centering + \includegraphics[width=1\textwidth]{WAVEFORM/DECREMENTA.png} + \caption{Operazione di decremento della priorità.} + \label{fig:decrease} + \end{figure} + + + + + + + + + + + + + + + + + + + + + + \newpage + + \subsubsection{Test bench 2 (casi limite)} + Il secondo test bench è stato pensato per coprire i possibili casi limite che potrebbero presentarsi: + + \begin{table}[H] + \centering + \renewcommand{\arraystretch}{1.6} + \begin{tabular}{|m{6cm}|m{8cm}|} + \hline + \textbf{Caso testato} & \textbf{Descrizione} \\ + \hline + DONE durante il reset & DONE rimane a 1 durante reset e inizializzazione. \\ + \hline + Reset asincrono & Reset durante operazioni in corso: il modulo torna allo stato iniziale senza corrompere la memoria. \\ + \hline + Operazioni su lista vuota & Rimozione, decremento e svuotamento su lista vuota non producono scritture. La rimozione restituisce ID = 000000. \\ + \hline + Saturazione della priorità & Task già a priorità 11 non vengono modificati da ulteriori decrementi. \\ + \hline + Ordinamento e FIFO & Inserimenti con priorità diverse e tra task di pari priorità; l'ordine di estrazione è verificato con rimozioni successive. \\ + \hline + ID duplicati e ID = 0 & L'inserimento viene ignorato se l'ID è già presente o vale 0; DONE viene emesso comunque. \\ + \hline + Sequenza di stress & Inserimenti, invecchiamenti, rimozioni e svuotamento in sequenza mista. \\ + \hline + \end{tabular} + \caption*{Casi limite testati nel test bench 2} + \label{tab:testbench2} + \end{table} + + \subsubsection{Test bench 3 (latenze)} + Un terzo test bench misura, per ciascuna operazione, il numero esatto di cicli di clock che intercorrono tra il campionamento di START e l'assertion di DONE, confrontandolo con le formule di latenza riportate nel paragrafo 3.2.1. Le 15 misure (inserimenti con 0--3 spostamenti e inserimento in fondo, rimozioni con lista vuota e con 1--4 task, invecchiamenti con 0--4 task incluso il caso di saturazione completa) coincidono tutte al ciclo esatto con il valore atteso: la FSM non contiene quindi stati morti né attese superflue. + + Tutti e tre i test bench passano sia in simulazione comportamentale sia in simulazione post-sintesi functional. + + + + + + + + + + \newpage + \section{Conclusioni} + I test comportamentali e post-sintesi mostrano che il modulo funziona correttamente, rispettando la specifica. + Il componente completa l'elaborazione del test bench di esempio in 2540 ns, con un utilizzo delle risorse hardware + estremamente contenuto: le Slice LUT occupano lo 0.13\% delle risorse disponibili sul + dispositivo target Artix-7 FPGA xc7a200tfbg484-1, senza alcun latch inferito, confermando la leggerezza e la pulizia del design. Il vincolo di clock di 20 ns è rispettato con ampio margine (WNS $+14.786$ ns, percorso critico $\approx 5.2$ ns). + + In fase di progettazione ho scelto deliberatamente di adottare un numero di stati superiore allo stretto necessario, privilegiando la leggibilità rispetto all'efficienza. Questa scelta, pur garantendo la correttezza del comportamento, introduce una leggera inefficienza temporale: + accorpando o eliminando alcuni stati intermedi sarebbe possibile ridurre la latenza complessiva di qualche punto percentuale. + Ad esempio, gli stati iniziali di alcune operazioni possono essere accorpati nello stato \textbf{S\_IDLE}, all'interno del ramo di decodifica dell'operazione corrispondente. + + +\end{document} \ No newline at end of file diff --git a/progetto_reti_logiche.cache/sim/ssm.db b/progetto_reti_logiche.cache/sim/ssm.db new file mode 100644 index 0000000..f0dde68 --- /dev/null +++ b/progetto_reti_logiche.cache/sim/ssm.db @@ -0,0 +1,10 @@ +################################################################################ +# DONOT REMOVE THIS FILE +# Unified simulation database file for selected simulation model for IP +# +# File: ssm.db (Tue Mar 3 17:54:07 2026) +# +# This file is generated by the unified simulation automation and contains the +# selected simulation model information for the IP/BD instances. +# DONOT REMOVE THIS FILE +################################################################################ diff --git a/progetto_reti_logiche.cache/wt/project.wpc b/progetto_reti_logiche.cache/wt/project.wpc new file mode 100644 index 0000000..3e85024 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +6d6f64655f636f756e7465727c42617463684d6f6465:1 +6d6f64655f636f756e7465727c4755494d6f6465:39 +eof: diff --git a/progetto_reti_logiche.cache/wt/synthesis.wdf b/progetto_reti_logiche.cache/wt/synthesis.wdf new file mode 100644 index 0000000..18883a1 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/synthesis.wdf @@ -0,0 +1,52 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030746662673438342d31:00:00 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b/progetto_reti_logiche.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/progetto_reti_logiche.cache/wt/webtalk_pa.xml b/progetto_reti_logiche.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..2fb1012 --- /dev/null +++ b/progetto_reti_logiche.cache/wt/webtalk_pa.xml @@ -0,0 +1,21 @@ + + + + +
+ + +
+
+ + + + + + + +
+ + diff --git a/progetto_reti_logiche.cache/wt/xsim.wdf b/progetto_reti_logiche.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/progetto_reti_logiche.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/progetto_reti_logiche.hw/progetto_reti_logiche.lpr b/progetto_reti_logiche.hw/progetto_reti_logiche.lpr new file mode 100644 index 0000000..04ef66e --- /dev/null +++ b/progetto_reti_logiche.hw/progetto_reti_logiche.lpr @@ -0,0 +1,7 @@ + + + + + + + diff --git a/progetto_reti_logiche.ip_user_files/README.txt b/progetto_reti_logiche.ip_user_files/README.txt new file mode 100644 index 0000000..023052c --- /dev/null +++ b/progetto_reti_logiche.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_25.xml @@ -0,0 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index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..d1e22cb --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..e9426aa --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml b/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..b87bc75 --- /dev/null +++ b/progetto_reti_logiche.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/.Vivado_Synthesis.queue.rst b/progetto_reti_logiche.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst b/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..4960303 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/.vivado.end.rst b/progetto_reti_logiche.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/ISEWrap.js b/progetto_reti_logiche.runs/synth_1/ISEWrap.js new file mode 100755 index 0000000..61806d0 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/progetto_reti_logiche.runs/synth_1/ISEWrap.sh b/progetto_reti_logiche.runs/synth_1/ISEWrap.sh new file mode 100755 index 0000000..e085d18 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/bash + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/progetto_reti_logiche.runs/synth_1/__synthesis_is_complete__ b/progetto_reti_logiche.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/progetto_reti_logiche.runs/synth_1/gen_run.xml b/progetto_reti_logiche.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..d43dd4b --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/gen_run.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/progetto_reti_logiche.runs/synth_1/htr.txt b/progetto_reti_logiche.runs/synth_1/htr.txt new file mode 100644 index 0000000..f0971b4 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/htr.txt @@ -0,0 +1,10 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# + +vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl diff --git a/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb b/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb new file mode 100644 index 0000000..4cb4ed4 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/incr_synth_reason.pb @@ -0,0 +1 @@ + 6No compile time benefit to using incremental synthesis \ No newline at end of file diff --git a/progetto_reti_logiche.runs/synth_1/project.wdf b/progetto_reti_logiche.runs/synth_1/project.wdf new file mode 100644 index 0000000..1d56225 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 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threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param general.usePosixSpawnForFork 1 +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7a200tfbg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/wt [current_project] +set_property parent.project_path /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_vhdl -library xil_defaultlib /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef project_reti_logiche.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +generate_parallel_reports -reports { "report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb" } +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds new file mode 100644 index 0000000..b83d504 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds @@ -0,0 +1,257 @@ +#----------------------------------------------------------- +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Fri Jun 12 14:52:36 2026 +# Process ID : 33507 +# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1 +# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl +# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds +# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou +# Running On : cachyos-x8664 +# Platform : cachyos +# Operating System : CachyOS +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F +# CPU Frequency : 4313.234 MHz +# CPU Physical cores : 12 +# CPU Logical cores : 20 +# Host memory : 16502 MB +# Swap memory : 16501 MB +# Total Virtual : 33003 MB +# Available Virtual : 19387 MB +#----------------------------------------------------------- +source project_reti_logiche.tcl -notrace +Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 33546 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151] +INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a200tfbg484-1 +INFO: [Device 21-403] Loading part xc7a200tfbg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + s_reset | 000000000000000000000001 | 00001 + s_done | 000000000000000000000010 | 00010 + s_idle | 000000000000000000000100 | 00000 + s_00_read | 000000000000000000001000 | 00011 + s_00_wait | 000000000000000000010000 | 00100 + s_00_check | 000000000000000000100000 | 00101 + s_00_go_next | 000000000000000001000000 | 00110 + s_01_check_number | 000000000000000010000000 | 00111 + s_01_wait | 000000000000000100000000 | 01000 + s_01_write | 000000000000001000000000 | 01001 + s_01_check_end | 000000000000010000000000 | 01010 + s_01_wait_for_count | 000000000000100000000000 | 01101 + s_01_copy | 000000000001000000000000 | 01011 + s_01_go_next | 000000000010000000000000 | 01100 + s_10_place_at_start | 000000000100000000000000 | 01110 + s_10_wait_for_check | 000000001000000000000000 | 01111 + s_10_check_id | 000000010000000000000000 | 10000 + s_10_wait | 000000100000000000000000 | 10001 + s_10_compare | 000001000000000000000000 | 10010 + s_10_update_count | 000010000000000000000000 | 10100 + s_10_wait_for_count | 000100000000000000000000 | 10101 + s_10_go_next | 001000000000000000000000 | 10011 + s_11_update_count | 010000000000000000000000 | 10110 + s_11_wait_for_count | 100000000000000000000000 | 10111 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 4 + 2 Input 9 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 2 + 6 Bit Registers := 2 + 1 Bit Registers := 3 ++---Muxes : + 24 Input 24 Bit Muxes := 1 + 4 Input 24 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 7 + 2 Input 16 Bit Muxes := 3 + 24 Input 16 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 4 + 24 Input 8 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 + 24 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 740 (col length:100) +BRAMs: 730 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 18| +|3 |LUT1 | 34| +|4 |LUT2 | 16| +|5 |LUT3 | 25| +|6 |LUT4 | 44| +|7 |LUT5 | 22| +|8 |LUT6 | 78| +|9 |FDCE | 25| +|10 |FDPE | 2| +|11 |FDRE | 44| +|12 |IBUF | 21| +|13 |OBUF | 33| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 363| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463 +INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 3d7ece1d +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026... diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.pb b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..0ffdde379965b8962e2fdf6b14780cc2887b9ab0 GIT binary patch literal 276 zcmd;LGcqtT)iavJtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- zGTAMlTdL4OdG}b4ZZSSv!!Dx%LbU3XV^KBm=`+7ZADE6(rK?24eSmgUGu; ovcX}g4~YHAhu1wMz||<;*~8J#&(&vbAV~BtkZiC&8U$hk03iNIPyhe` literal 0 HcmV?d00001 diff --git a/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt new file mode 100644 index 0000000..18b9943 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/project_reti_logiche_utilization_synth.rpt @@ -0,0 +1,188 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +| Date : Fri Jun 12 14:52:50 2026 +| Host : cachyos-x8664 running 64-bit CachyOS +| Command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +| Design : project_reti_logiche +| Device : xc7a200tfbg484-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 181 | 0 | 0 | 134600 | 0.13 | +| LUT as Logic | 181 | 0 | 0 | 134600 | 0.13 | +| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 | +| Slice Registers | 71 | 0 | 0 | 269200 | 0.03 | +| Register as Flip Flop | 71 | 0 | 0 | 269200 | 0.03 | +| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 | +| Unique Control Sets | 6 | | 0 | 33650 | 0.02 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances +** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 2 | Yes | - | Set | +| 25 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 44 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 730 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 740 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 54 | 0 | 0 | 285 | 18.95 | +| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 0 | 40 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| LUT6 | 78 | LUT | +| LUT4 | 44 | LUT | +| FDRE | 44 | Flop & Latch | +| LUT1 | 34 | LUT | +| OBUF | 33 | IO | +| LUT3 | 25 | LUT | +| FDCE | 25 | Flop & Latch | +| LUT5 | 22 | LUT | +| IBUF | 21 | IO | +| CARRY4 | 18 | CarryLogic | +| LUT2 | 16 | LUT | +| FDPE | 2 | Flop & Latch | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/progetto_reti_logiche.runs/synth_1/rundef.js b/progetto_reti_logiche.runs/synth_1/rundef.js new file mode 100644 index 0000000..d5d6754 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;"; +} else { + PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/progetto_reti_logiche.runs/synth_1/runme.bat b/progetto_reti_logiche.runs/synth_1/runme.bat new file mode 100644 index 0000000..60fbf14 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.bat @@ -0,0 +1,12 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/progetto_reti_logiche.runs/synth_1/runme.log b/progetto_reti_logiche.runs/synth_1/runme.log new file mode 100644 index 0000000..f2d80ce --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.log @@ -0,0 +1,247 @@ + +*** Running vivado + with args -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl + + +****** Vivado v2025.2 (64-bit) + **** SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 + **** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 + **** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 + **** Start of session at: Fri Jun 12 14:52:36 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. + +source project_reti_logiche.tcl -notrace +Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t' +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 33546 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151] +INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a200tfbg484-1 +INFO: [Device 21-403] Loading part xc7a200tfbg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + s_reset | 000000000000000000000001 | 00001 + s_done | 000000000000000000000010 | 00010 + s_idle | 000000000000000000000100 | 00000 + s_00_read | 000000000000000000001000 | 00011 + s_00_wait | 000000000000000000010000 | 00100 + s_00_check | 000000000000000000100000 | 00101 + s_00_go_next | 000000000000000001000000 | 00110 + s_01_check_number | 000000000000000010000000 | 00111 + s_01_wait | 000000000000000100000000 | 01000 + s_01_write | 000000000000001000000000 | 01001 + s_01_check_end | 000000000000010000000000 | 01010 + s_01_wait_for_count | 000000000000100000000000 | 01101 + s_01_copy | 000000000001000000000000 | 01011 + s_01_go_next | 000000000010000000000000 | 01100 + s_10_place_at_start | 000000000100000000000000 | 01110 + s_10_wait_for_check | 000000001000000000000000 | 01111 + s_10_check_id | 000000010000000000000000 | 10000 + s_10_wait | 000000100000000000000000 | 10001 + s_10_compare | 000001000000000000000000 | 10010 + s_10_update_count | 000010000000000000000000 | 10100 + s_10_wait_for_count | 000100000000000000000000 | 10101 + s_10_go_next | 001000000000000000000000 | 10011 + s_11_update_count | 010000000000000000000000 | 10110 + s_11_wait_for_count | 100000000000000000000000 | 10111 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 16 Bit Adders := 4 + 2 Input 9 Bit Adders := 1 + 2 Input 8 Bit Adders := 3 ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 2 + 6 Bit Registers := 2 + 1 Bit Registers := 3 ++---Muxes : + 24 Input 24 Bit Muxes := 1 + 4 Input 24 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 7 + 2 Input 16 Bit Muxes := 3 + 24 Input 16 Bit Muxes := 1 + 2 Input 8 Bit Muxes := 4 + 24 Input 8 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 + 24 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 740 (col length:100) +BRAMs: 730 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108 +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |BUFG | 1| +|2 |CARRY4 | 18| +|3 |LUT1 | 34| +|4 |LUT2 | 16| +|5 |LUT3 | 25| +|6 |LUT4 | 44| +|7 |LUT5 | 22| +|8 |LUT6 | 78| +|9 |FDCE | 25| +|10 |FDPE | 2| +|11 |FDRE | 44| +|12 |IBUF | 21| +|13 |OBUF | 33| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 363| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463 +INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 3d7ece1d +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374 +INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026... diff --git a/progetto_reti_logiche.runs/synth_1/runme.sh b/progetto_reti_logiche.runs/synth_1/runme.sh new file mode 100755 index 0000000..646b7fc --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/runme.sh @@ -0,0 +1,40 @@ +#!/bin/bash + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin +else + PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl diff --git a/progetto_reti_logiche.runs/synth_1/vivado.jou b/progetto_reti_logiche.runs/synth_1/vivado.jou new file mode 100644 index 0000000..bbc0a51 --- /dev/null +++ b/progetto_reti_logiche.runs/synth_1/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2025.2 (64-bit) +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025 +# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025 +# Start of session at: Fri Jun 12 14:52:36 2026 +# Process ID : 33507 +# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1 +# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl +# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds +# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou +# Running On : cachyos-x8664 +# Platform : cachyos +# Operating System : CachyOS +# Processor Detail : 12th Gen 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diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log new file mode 100644 index 0000000..2f60c4a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log @@ -0,0 +1,17 @@ +Vivado Simulator v2025.2 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling architecture fsm of entity xil_defaultlib.project_reti_logiche [project_reti_logiche_default] +Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge +Built simulation snapshot project_tb_edge_behav diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh new file mode 100755 index 0000000..63b062f --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Fri Jun 12 15:55:44 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log + diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log new file mode 100644 index 0000000..cff1490 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log @@ -0,0 +1,24 @@ +# +# An unexpected error has occurred (11) Segmentation fault +# +Stack: +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7fd51747195c] +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7fd51747242e] +/usr/lib/libc.so.6(+0x3e2d0) [0x7fd556e4d2d0] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7fd52434ebcb] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7fd52434f1e1] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector >&) const+0x6f) [0x7fd52436a6ff] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0xb7) [0x7fd5243c2cd7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0x128) [0x7fd5243c60c8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7fd5243a9596] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7fd5243a3f64] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7fd5243f1b2f] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7fd5243f1ca4] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7fd5242391a7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7fd52423922c] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7fd52423a8e8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7fd5243f137e] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7fd5244037da] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7fd524403c62] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7fd5242050dc] +[0x7fd506f7a1ea] diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..ecb626c4ab827a746adffcf4fe874036ab413661 GIT binary patch literal 13294 zcmeHMdvH|M8NUG{fr2Cfl(nL17$>2S>;vQ>LbD_bMDkdZ4Ot%cvScr0VUtaFZy-!z z5<84g2AmXTY_K4a0*S~=h15dP=+A-E(j5ZrnbU$*gnOPlx26>$J+}XNfxW%R>uo{WtD!990&@m zWiY$Ce}hkSO?7JH&KT7@&{ehTOxnzUW-X9uxLE|YoN$z_xAHNSojXXiy;D_tbm+~Z z2*UB!28D150prM1J_I3Yl&U+d8vT=PS6FFfLs-WPw>WEjx?{dnF6&Iy(fD!9nZ)K< zowHHsB$U&UG$A_&7XVjan`sql91GsSE`sn3EK;j4bY+P-`4h7<1q>>n3iJR{ic*9W zH(&v*z%-y3$N?q+X(<9NJ{iy=72R2=B!ohO^?7zzQGq>2Ne4qhYinyYEoBGd`J}}u zj!aj6fkKQC>Xm$mNP8ixwHt`A4rs*yW0+q0RMImwYZSsk31FXlPi%D7cj#>Kp%-0_YAnzll2&r&^2t+5<=Y$7w?IaQ^! z#j;uyrI=$cq|oRxIlRpLT&KN&a#K2r7+yPZc3z>QfGLZdxC0%K73H~ zfPuJhjKWw2&Rtz^6=z^m9~6Y0&=I;pLij!d&OunCduJ5ZNF^c~9b@V(>xG z4hTCH>KsP3J~61#xzL(+i%?%XGZc!R5lTp!K%*Gch(k9T*%TlW=M3iPwo_HDt$pD~ zYLw3-0PTxvL5<=+%q-1oaZp0NX}M?vkvL~G0%u9v9WdsP%cG9{u*pQ1l^SvB@ut2M%d8F7b7)`=luyeQLy^ ze0VPTIyd-x(=ha@(KyvqTbstHj>M%oVOW#tDY9r<3_f4VMdu>lEQP6Zam4A_rsqpX zSmz>#e2z;zsO@&W!JLEc=Ov^ZK8hpMEbVg}!N?g?8mmD`8K3`wb>0H$JHI8eB z&&Q=Rs&f%{FUK8j;L;h@xj1LXIPR11`5fqs>f9Gkm`-!t5%BpO=#1*zXHJ@0IPTN% zJGvH19X{P^`j+F4y&3njt){Ll5S`y~H{czNZv^caT-)NlnO6QGl zG*0`v-SN8>|90ctEpI7rLg1$h|Coe=Fs{}-Epj?8{SOKw2Dib|k zZx94>y&ltwa?{DuY41ajQ!xk=uO%DZ2LgrAQGFT#oM60=6S`dLaztk(30~NA)zHh$A8!+1}wkOkV<|%5A zc4P*{Z$?0KNcM_0i*+;{WaJ5Y(`ibe$aC@GE0bnb`uyIIc{EzOMRXQq=Q>2I)nXHE zR@-Q^uN*?ZKVO}B zyYRo8D8IyQXN!AL3i?WLN8hE>*H+H((07s@zsozkK{`y4i%)-#_@+H~8{m`zWAKOY z2JD|;Yk_L~aU2djffviOu!mu50E$6c&64lo`r7!dY#ucEfD?EYC;$op7f=LD0g8dC zzzpCyKm=&55fa=x=(7WOm;B{atunpJ_>;QHGZvbxsZvnf2-N0{wJpjEs zz5~1qGz0Ge?*j*bgTNu+1KNQ#i9mdi>DWAv;oZWJQ~N*(;Kfl z&iEfk(BY`+jn~!oREO)BHLj<9*B}@jZK6zbyFLh!7vqs$m5p>Fz zOU%XfRtZKOyFAJyzupzbS6+-UYt*sJ6Q=v}L3N!g%o=s9%wf95KB|s>m!W3Vu`(-j ze4cgj%8*dctWn3x9Hv{Apz3OwHR@QI!*o@Ns;-7vqfRRuvG_bo`>MJMW{o;lE``MF z-2GJDOlFNbR<1Bz)kCUo8M8(mD_5AV-lXapnKkNIxx#eK?1!Vn%o=s9Tw%JMkE-i6 zGi%hba)s#{2dcWA%o=s9Tw%Jp$5dTCvqoKibvjJ9>~VFXmRX~Yl{rjTm89xwm^JDi zR;QIu{<@d`K%J;!)~Fj0K{qp5ohW72sAHEkY(3{7Rp(~bsCy*BdhB;v{6xzU;A;A7 z>;c-y7Z&sDtnK;HUbF(y3ba+Au+5En_dx};=b4tumFV+JD@D{sD-c$J6=5UMfqPj2 zRno!-g?JLpeS6eZnUbF&+3UIfIVJ6zW7ZotR ze+7o!i!7pRMl0~YQGw|5>;Ae<#`iDn{{dAoEyrI?5G=jAWNg?o_uKXLFXhEwO&#@@ zlBup8WK*O=YIRDbo46 z#N>Z&958aH-hQ$0?5eBV&X=x9Kk(9}=fv+WTppVo7=7f|fluF>-hao5 zErb3%<)LfmUU~P};x!A`9lU<#wdI}2Le2EM_02ux*|7rUvbT2)<#IJ)gZJqPGncGr zj$1K#dB40R`@3BH;Bx;aIpMm0@VLtL1uyR1ygl`*bH)+p+Ijn53GCYU$BBm~?nv&` z-j!8v#Qu0&OV_UInoBaU=Hrj9uYGgy^R>0LiK)F4KTj(iGjpxG>GQdpe*X3;_lmDl zHmtoW@49yV#>zUI>(cb%>fd~maH_cV<)w#``{vHJeLelWJ*Csj2jWM?tV)b^)AH~2 zsLANnt+_F2T-wpZMbm!v#ZQxlG(2(m{OZZ?x0Gx-y<0x_$?43Ir%r6%EiO9!FZV~? w&;KsBDD*-@$~%kq4Eg$8Lok2Qho7X}I6dd}zMZ@FHNx|)J!cHa?E1#P0b?vs$^ZZW literal 0 HcmV?d00001 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..4f79ae6ce79b3b911150866aa8dd9ea69343618e GIT binary patch literal 396500 zcmeEP2|QKL7q=Cn@+%dUtzK!fw5q63L<>dxhLBV!vK2~^U%RbUN~N^#dm^p0YhQ#) zyU0@Z{Lj2M^jyF9`?u)l;=GSB_ueyS=FIoZd}q1y7-v7r-qAyOtlk&{iy9#Z=i*pB*Nq#NX1hum8 zZ#jrkAxD>Ykv6DeY8w;YJ;$8N$MWLHNxay`ipr-^`3x#|qVl;^?n&j|RKAGH1E_oj zl?PJ!8Yv`C}?iqVgA1 z{)WmwQh6qo=TdnAm4Bmh5n=8{q&P3Ok>qxjB`Oqw>jAZbjwOsC*`s&!+OZRPIUTK2*M#$^)o;1(gR;`C2O9 zNab6oJd(KSJdvsXUs>&r|tjD!)eMx2gOdl|QEP=T!cZ%HL4=M=JkJhSBmd&XHqEKL6_qPdIfu$SQn@;nccXGGD%YWMJt{Y#@*z}i zO68-dd>oZert+y&Zb#)aseCq-yHfc)D)*uC#Z>+`m9M1oASz!=^%ZnaaOVc_EdTQn@IPu_7gS zu}wo>%xS`l)0$IxD=Jr}@^)0-k;>JnygQZmrg9xB*Q0VnDj!Parc^$P%Ewdr6e^!e z<#tp)i^}Ivxhs{=qw)n*?nmW+Q~63N52o^UR31j<5mdf|%J)$D0V+RA<)^6p9F@mW z`4uX^PUUx~{63XGq4H!Ze?{eQsXU#^v#9(ll^0TZDV2+f@%on}FHUR7izA!xVw)CJ z-kQplsk|MPccO9)D(_C^y{Wt(mFrWvA(aoM@)1-%n##vh`4lR*rt;}jK8wodP`MkG z&!_SQRPIOROR0Pnl?PM#Ix62p7d{5qB2q4Eb* z{*=m-sr(g{zoYU`RGvlUU#Yx^%7yB2{gfugiz6j@u}vdh%oY9zzaowQgF>(fL;w*$ z1P}p401>Fs27OF@_BuW!T0sP&PCk1{*)H^OLA=alg}yhLElY z6fp#1FfGD-)F6vtrh|WCZLcEiJM5~ zrKRwT8<&=f^Dc>%+(P`|9=sCaVr}ba4ab>eX-`ReyXL*XUT9Fh^v;Xlisi-|G_cScWnn%_&x}6%o{m}t>9__$ zop@T*2=d%?_y|2SVg}rNFAZ)+kAQ7$1OBqU=UY~O*Gj2)738y$;NJlP`IK#jpX1#M zJ*TlEby9yC(=A6KapDp9&@C^aczQ2S8xP$w5xPY0DL0#q8dY&INwXEor(C{?(f~h~ z57HkDEZ$3qaCk1XkyE5#DDPA&At58kUk=)KAT&5;kb^wWHx&{Z0j-9F2ne4c>;gR! z2-B0$hlX|#Ge7?DU>lURnvw+RJtQ2U35or}@QZ}977ZqHDUvILr)Bpf1^Lh_mS0oo zxZG6M7nDKD%@SfFCmf+buPtcY58|>kaLFx)ltt2$&P|{n3_(yDH;|EPkx@)g8b6Q` zd#(N{!_;e1vhlu+jwvZ3Ocp(H*hxri7>I;|UHj^}D+nUs$e0Z9rrQkk+ zA7U4{o$Et_4f&9~rD#m@;y@t&CHc36KtANUJB^86Sy^O$Q1&Uqu$> zT{>T%$jRsbrd>H-pT0i(|7nBf>nriH<)$UGNYbuIJ1(=O+}O>69-f9FTj4)@T1{-bF} zdgy=n(X^vI^z(l-?RXFU`n2Mt{mFCnB)EN%+!GEf#{n>Fz?YVAS|9}CThhizzb;SP z{;EEGjmh;J;ph(2d7MYu1ZmIZX+4wmJMraf05XBT@bb{_!U%rmJ`48H_u@;d403^KLp}5t@uh9^Z)w+f=r7|-+ZNLDV@BFO!Hk^P(^uSF9IPQNKW1buQl2m1(3lG}ukYG0(kk+&1$-6w(%ONHA2ZVS z%k#}l)Ys%oJDrhMnLjP$tIL;mCdl~Pg9?Az#fkc6d}(Jf(zfAG3;9~{r6p?*3L#uE z@V)AxPhYQdF?0F1wAVfK-TCq*`$huuz3rh-U&nLvb%nJ2n329(j@hPX`t%h&H!Yd- z@#8@HYI$0y+h%G5i4H;#qXD8yd=|l%HtzqVCHiHYNv_F~k_U@qb7@1mCK9UbYEURtCwR)K*abW$B0wFRY z_6vIcv-w!eg&oJ)&Q3FItzlwRx%L*bob2qar`rk{nhzI( zQ0R$5?e>UOhE9xc#!br z2O_>ZkeTTX7b-)FZZUtq=k1o3!3-PFbDf=L2~D#HzQJJ>A;~DBMi)p zO=0V8pn-`VTv?bKPcRVT?Z}Z!3q3P4z41c!T+r>gnA=mxzhg+R%J-}73Cd0uT!(!3 z20yM`h`A{7p7LEnU3t%-n%qrLAxB$}xundwwnEmf&d%^Y!#@wmh zdUorj?l#>H4)#-f{M*FJCo zc33&v5baq)q`VpM%ih6us;m7h8yAf}@KJ{?TQk@phmNY*&7xb^ZhbWD9YJx{ESDe5 z_Ghh{3!b%is$!ceWcq^^+1uLMmH}nMqb@+9SC6VO?f>Ndn>MOVb+YmNvxf2)@zd5i zx;of8+gn2quAVsa00?f2&W;Og>Vi+9E1xHEPZi27_LYa-b;F{RE2LiEmAB0m7 zh)ri8L_;9uUxRQR!Yv4i5bi>_2jM=12M``Ycm&}I1hT)E3?T)=2M8Y_e1ebxArnFl zggglO5DFj^Lf|?Sd{5rxkgp7gLJ)&c4+8n>0QuTLLkNu^G=?ApfqZqKIfNDvT0_u) zpb3F|MW8!`9uRs%AYT#a2Z6jt(}SQ7VITxU2!kOQK^O+X48mv#V<3=yG4fS`@es&Y z1*Sl-fM5y13c_><_7G-3aDdt{ed8g=t zES|W;{JP8Z-5%dn)NEH|ObfpfOXAx~Gz! zObc2bjhTAXJ(cvhCoABogd9(wsYl&YNsqiwC!c%)delAKH2nTcmFGSZdPiesdDK0X z^degF^mfshsYl&YNzbwsPtURyuLU#psCz2uO>fOhpHE|^9(7M8y+aB-y~qClTpo2# zCB48Uy!7j7%q)+>TuE`92SD1Q=Wl9k9>oLa_rk;`jJtprm^^^tZF~$WYa>99IsP&A+6vHPj({>0`!DpvUAv zrd|gDdQ2W<>U9*L_xInt{ufANrd}rjdLB!8dJAdH)axujZ~8Kxo(GMYdR+wQSuW@4 z&89I^PfdW{xD`A-OByrv)CK4nt>o#ApfOWVLx5iIRXjai8Z-4Y1?Y8H&C}DQF;lOr z06n=to}My|nR?v>=t%_e^kitv)ax!lFQ29t3g+oE^?C@lM7NFNtfZpQ}UOA~W zW|r4WfSzU<@lrYeJeB03#iz%AIq3iB_2y5^cTLX=!cjrKhj3Xoo?W5?u4adda+|U< z=M^909U_1T00JAB9Uf7sRs_oUtjvg#X8bz`Wlu3i1P}p&fH||nAS~620Mi{2Qv5T+ zYBdcDM+8`h0C|6eANC+X+_8PZcY8*(!1>pAH1G-$sEELcinn-I%?L1ullpSVU)Agq zES|*(JY}(MbXH@)x^2gx0VL0o?y$lQ+J9pS#Q|8)f9LGAuAg1ege9F(2T4wIaZre~nf_ z{;F1oVBxGrpoG=d)ji{w{AJb#`K#`=0<7_mB0&DOFn-vB0F%FlwnhG8k9W`#wjq$j zHiPQ8Jxu;m*{Kdk8T3E2{&}zkUx<)UM44Ab+vTyG;K2+!6VUT^>Sf*n~h4n~XtQ%Ksl^ z85AEoA%B%&fiWV$L?E5{0Pm|60p|ScQD@|@YIO(}&Ta&l9fsZ3)_Uuh?s(J%`K#7D z9V__D2;lc0e;K+zqR8a0`)bHve*|dEv{oRHUn^=+dn&=?uN&&fU$w`(Sd*$o;B8fB zi23~%0!;oos)79VTY#c+twsRPPq53qO#V8eiTuSb51}<|LZFyU#-J^g&QBcZiu{Gm z0uc~|0G|I6giQ53XU@NNcSHWF9#3GYH35ONnqXudvXRMOE4w3q)gkv|ReurzVP=Q< zNqtOSwFofXv8o61SJfhnxz#2FaQ(*ennMK?sO27c7Dj;`9Fm0j4|V^+x{sPk_flY9s>q z{YQ4Wjmcl`eUQJ{I?2G)xE)StKY(n5An~XtQD(!y_*GB%r zW`PI@LIC%_1R+yB&zb8-Qyt{5>hT1YS`!fXP!o)-LpCz`t4}}VuR7#@tm;o9@bxFt zWAZ$Y0g$5-gs@2-IVC7#7=F z7ffTiqp2?PS6%Qs*74U6$ow@m)cQjRF!@VF5Bcj4L5xC<(k$zQR9kiP_Bh0hUzbcBFa2r&6;uL1HGs~m*JunK`3R#}6_F!^h%YJq%cz+MWYkQvYpvBx{#s##{8ek6jTQTC1fKnN z4wykzBEaM?J7eUps>B!bs$B?V*RJZ+_}Vb}Yy1%8uNv=EtiT^b0RR5iAA|OnGG_AE z#G%MvzXT*I)d>Xf{|~Xt%}o9>8;1PFE)StKY(n4(n~XtQD*gTF&cl(vuvs7if)K#{ zFG0vu&vWMdOTh&Bt9m?vrPc%l3TuLqb;w30f3+}0{;EUn$EyA$0{K6g9+UrB1epBQ zcm(p-pG6#VugM7D`7d^PkI7#jkiXdFAhd>62;lw~tK3m(|2}CX&cE2@A+&}~2$ZnN z7__Ale?2in{=#N~2na$TSC9aoR|^8n_2W%*A)&fPa6LP2Q-? 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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run all diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..83efe5284d52f51c3a2afb1fb4b89318ab903e68 GIT binary patch literal 19872 zcmeI(cYGAp+Q9KeQ9x19YoQZ*U_+XKAP9sIAW{-TLa{9&S;=COT{jyDUc92xRHTSk z0Yzg0v7o4c2tfhqHf;Bzh=N!EQKN#QBD}w6=FH|W$t3d1{V(V9`R0baQ|Q5%tbsp|;s+@A37Gg{@}O`8Cqz%4X~EzI~#T#(DEY zw#XW)-CI3h8KBzg`AjkoXd==_rY1%7OCH378=l-WiQ3DvnL5N3Gp4JksfvfD_w@`) z>7ShFl0gc2aw1XfGTOP?jX*5oa1DlI5C))QJC}@NpqXRzl=1hvilD2r7}Su2^o+EG zLB?=ca*nER!M~)`WC^;sh^7ed0tdb5TZVyosOod32JVJUGd9 z4h=cZ9$S8aYrk|&DJ*dH?o-cL%p-RDg6^_h;LT!0i$2`Xa-J{Ws3qqM8Z`r72l6mpC9PaiF=_KgBa7X@s#p&Rp*qk}gkt~#`cUM@&<9Sp434JiAkP>bkETAgfz9TEKZGzIAeh9lbNLk zA?s5HrzWJyFldy$8;y)q9%3fx?^V{X_5N|?qRbuCMk%L2Pslmq%MW=ngTc%RT`u#4 z!Y7KHAl8W@wdkd4IRm+@jbc4GU8~x=RozSyC_Pnur>cKa^=NgvsOvl}Jw4e>P_HV? zwMyL=tkX-sFZAuxpF2Vqm)s8yGp1GKMsU6qx952+{ZBvNd~PexZgr6tx?IaHa=8XH zG|i*lkJ;o2IoCyRC4$;s7O>(D-fNyr6vfIpsP;?7UxOE6&Yp4k8<(50jkR*2$yTe# zX>OIXS&&m-iqvx7l)MhArZU#cH7S>d#4J~Je`@1xsinyKNRgP$kRe_Trv`H*^h}8#Kg1C*gpm#H=e0hn_7xF;u9z8upEHw=WG}`)Kc`A+v!JQ zt#$t}A}W57am!~y-5GJK;I!?Pj$4OPw;U@e5-ZoIV{CM( zd%6TtBvzL7@ydRN$G~{!(Uu~ycR?SooGam2#=C^J6p6hXj$>F_;$A6%6p6hDj;!ImYQ)tbC5hTv@TQui;pZ#Yiny?pLbGQrYz;`L07H z?onE-d@kwZm3fhVjabGoR*RL-C;j}DuT0@s#!#rmHfEcC?#LX5$4kGHwAd!LSeZk; z-+Q#!rfgG9mTdd>bBX(YEw))@v4>0C3$@r36>EKloOF-+y~O>57MogG?4Kp>=e5|O z#OiY<$6WT!IDeUk*R|MmTdW-Oa4hrtwiY{_ZTkFPqQ`a`8?{G^9bt==^F!~qRExcq zZTk5j=SMiU<_%G27$=7L9pyS(EMINQVj1rRTI^`HskdRN?6?{8&|s~*u@;+ES!|QF z?si&ic4e^7GPT&Lwpclz!?E-`R*RiRtbASzDRTaXV`=AW zvD1mw=Rv-+gku@QcrEsKI<)tz-+w1)v45OGY;7i|vVJFO{hogcv5ik5wq+Hule971 zb_%hNokHxIDq`7uQjy~-=bD^5dXe=qT&ML;{m60Gi}WM+E9*XJZIktK&it?Ao!u78X#E63~VH*~OzALn^J zp15vZU4xSbyYjqw{@?^pfp1KHX0E4Td}biv4N7vzpXJZ>9LMOkchy2dLD>9Ve!)qXLgtlXPiR6*jXc&r#S7P9^MURmMygfa_m^7yi)VJrrMK7Y^`nqX`V z$g3|L<1NY}g8_Onv$KP)vSxN>C{t^W_i7DqzRSmu^+c_0WNK|vwHCR?Aj5ANZW(#u z7FpqCGskBP(}+?Nn&rZG{BzTW>zSeYYyF5lD-*9c$wjamyJ;yE$a-)$_#`G zgJ!?pqJVTSmCTIGmtABuMo(Zz0yJF#e}VB_Oism^9DklSCNtNYnV%i>$E2E9OhF7M z^%!p`8M8#{P3xZh%F$KOnPh3pCcf17YS6%eDoNQN&KM;yBpN+=E$HsS#j*l7U z8<&~wkCB~;AtX13Zej{T*`D~=xNa;kpv+*lWaqk!K6&xwc}Exea2HelAXrG ze@|RoY`iBvF1}lgFQ3HR+=9Q@?Wv9`#3|wPpXM>0)ahRwkag|<`?F9gT5>-{nK>zl}%^)uK&*H^u3ge?r&Tm6%JAF z|FqpE{Dr|RZ$a6uqWoP(PL1$0XZijpMSX0#7PBx0^6cbK>W`>r;a_}-m4CCf=0V3^ z>Mhi_p&kEN5LO>nE&bidcB}nYYsr~R?qwn}C0@ZQyo%LWgA%OAMr^`nY{6D+!&{K&4DaAw?7(|?A0OaD$g$dq zkMRk1;Zy9!XZRd@uoqwAD}0S_upb9-5Z~euzJol2_!07VyPt6wNAL@N#Zml*-|+{I z;{@bERSn2wE$ z0#9NQ7UL-_!BQ;4i+BkyV>wn}C0@ZQyo%LWgA%O8Yj_>&upS%m1~y_7wqhH$<4wGU zxA6|%#SXlO_wfNf#7EeLefSbz;cI+@{WyR__zvIW2bAJR9L5p+f?shIf8ZGY#BtQ% zo^}S##M!8Y+BgRd&=8H#7){X}5om#yXa%|Nwt*Wlh(#RY(FvW=1zph%-O&R*(F?uN z2Z`v5WL$-T7=*zXf>fj<1H&*JBXKRR!}YiUqmYTw$U-)}$bk=IaT9WphkW=Ez|9C^ z9LA#v6L1SA;#SCK%Ou>6X_$>UxDRu2KOVq?n2!Zmh(}P2$M6K6#3C%lQ+O87VJV)+ z3s{C1@e*Ff3arE{ScO-y8f)-6)?qz1;08#4db_-S`Zj zV-NP?3+%&}_zGV`etUHg-{KIy!}s_BrT7s);b$Di5gf&D_#J=X82-d@oPa#!tAR6c zCTgMo&j6EgvkD?gzjQnvtiA7k9r?3Q1 z;~6}Q=dcvd<0ZU|Y+X^z=ik+F2cpQ1ec-#8ln*zqZyhb0xi%It~0 z8oY+}*nl^%5u30XTd)oKzZpNFy$kxk8TZlt2K#XU2k`?+@gwa2e*Ben^7ldcH}P>8 z|6u0dIcMQ))Iwb}M+91;6sVkjKLU!6r|#6 zjDY;U;2K^u!mr#1E z+McHlj~S%BMm91Vv8uM`sl%gXn2QY>n{|Y$?Ro0(l*@~3Vy=o+wLMQAo^p8&nwqN` zG&RqBd!9NxhS4o|r}`~A~?|5AsiT%P^@Y0p!Kr(B->{%Oxsho@Yg z{r+OlQ-`Nqp8Y;(&r^q|T%P?tXwOrJsa&4@K5x&H-|kdY?Du(lUh|5QSZBX~+VdhD z^6cleJ+FmBp8dXS&ui(BXTR^-^IAFN+3&mdyw(nR5zWl&AyU=$yfzMb^_!b{4ODH< zYwM8biZJu)tJnA_@fSa?H%&=v^3vmzpCx;*TErgM=LXL zr>gCFZil>et)$ zn-pp0O;@!&FV-P1(B8}|QnfuV&LMBB?LM!6uaZ9E9rE^6k$0Ix-l5LsIIYe0_v>VB zu+>MqRG!z_7H>6=Rgu@l3bfT1U0(V7U2coFnvqrHb+rO*b&o3Yy4m8bW@;6AS6G3z zI=hOz?zVWVSyV+{4=d1C&!{5rN?W|uEUqH2rxj?cmsgS3%NB1n)&I}qzvfwM%-Z_? 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Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb b/progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb new file mode 100644 index 0000000000000000000000000000000000000000..fc4bb917c9f7997b3dfbdc3b7d7a750c337af038 GIT binary patch literal 15322 zcmeHNZE##w8NMxFg_cicTcD-emL_Rwv%BfXv;s~y$+ij27s;j#IC#6+UAnhycGula zKU6S^V1&^rqd+O35eKcvXn#4#$cQuk02~=W1aw5Z#UI7bAgGlYiO+M-xpz-aa#Cu` zzkO$(ea|`fdCq-y2qP@=<8qOxl`JyFl zll14zTD8lL-`L}|@3>f$nl2Uo@oT&*|DO*-=3%BD&Y0<9?OH7ZwG7lUP|H9q1GNm) zGEmDvEd#X-)G|=ZKrI8c4Ae3(Lk4=fpK`Chg#(83W}`SqkRNWl$Spi8s^-rI%Sz$u z_SWXc*zR<$tTAWF`T}`w(kAQj+@&1{FF_oy#DbgKJ8&R_6PXqB&&HVx!x%(N*Tch& z^~GE5j_xh(Ef#|$cp`ExP~Tr~)eit+AOhS3YzI1kHehwV#VEE4joVZIsdW`ZS7#xp zu4uf!H`?KbgC=WYV&ZeWRTMz_szKY^VlDCRUY9t_8gt_zk5g>>L-k`lJ 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/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo +Time: 12950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.5 OK: insert con ID duplicato ignorato +Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 2: Rimozione === +Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0 +Time: 16990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto +Time: 18930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato +Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 3: Decremento priorità === +Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.0 OK: decremento su lista vuota +Time: 23130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.1 OK: saturazione a priorità 3 +Time: 25350 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica +Time: 27870 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino) +Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 4: Svuota lista === +Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.0 OK: svuota lista popolata +Time: 33050 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.1 OK: svuota lista già vuota +Time: 34730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0 +Time: 36690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto +Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 5: Sequenze composite === +Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto +Time: 41490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.1 OK: ordinamento completo con priorità miste +Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 6: Rimozione multipla e ordinamento === +Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota +Time: 48310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1 +Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 7: Decremento ripetuto === +Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3 +Time: 53430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente +Time: 57010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.1 OK: decremento su lista con un solo task +Time: 59330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota +Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 8: Insert dopo rimozione e casi limite === +Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto +Time: 64950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato +Time: 67830 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato +Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 9: o_task_id per OP diverso da 01 === +Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1 +Time: 72490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1 +Time: 74450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1 +Time: 76330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1 +Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 10: Protocollo, reset avanzato, stress === +Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset +Time: 79750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert) +Time: 92030 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato +Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 11: Insert con ID=0 === +Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato +Time: 96290 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato +Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 12: Capacita' massima 63 task === +Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata +Time: 231450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati +Time: 235970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.2 OK: drain di 63 task nell'ordine atteso +Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 13: Stale memory e duplicati ai bordi === +Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.0 OK: re-insert di ID appena rimosso +Time: 365710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.1 OK: duplicato in prima posizione ignorato +Time: 368130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.2 OK: duplicato in ultima posizione ignorato +Time: 368250 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.3 OK: re-insert stesso ID dopo clear +Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 14: Reset asincrono avanzato === +Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.0 OK: reset a meta' shift di OP=01 +Time: 373150 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.1 OK: reset durante la scrittura del count +Time: 375930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.2 OK: reset durante OP=00 +Time: 378470 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.3 OK: reset mentre DONE=1 +Time: 380550 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.4 OK: reset corto non allineato +Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 15: START lento dopo DONE=1 === +Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.0 OK: nessun doppio pop con START lento +Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.1 OK: nessun doppio age con START lento +Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.2 OK: insert con START tenuto 2 cicli extra +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: ====================================== + Tutti i test edge case sono PASSATI +====================================== +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616 +INFO: xsimkernel Simulation Memory Usage: 291592 KB (Peak: 337672 KB), Simulation CPU Usage: 710 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh new file mode 100755 index 0000000..113c34b --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Fri Jun 12 15:55:46 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log" +xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log + diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb b/progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..98e6892a92db9e35314c12a9cead968ca30bfb90 GIT binary patch literal 1688 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0000000..98f96bd --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_26(char*, char *); +IKI_DLLESPEC extern void execute_27(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[4] = {(funcp)execute_26, (funcp)execute_27, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 4; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc", (void **)funcTab, 4); + iki_vhdl_file_variable_register(dp + 9192); + iki_vhdl_file_variable_register(dp + 9248); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_reti_logiche_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..86cadfd7417d099334d8d3e08e32926c9d306cc6 GIT binary patch literal 4224 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0 HcmV?d00001 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log new file mode 100644 index 0000000..ebacc77 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_reti_logiche_behav/xsimk -simmode gui -wdb project_reti_logiche_behav.wdb -simrunnum 0 -socket 60931 +Design successfully loaded +Design Loading Memory Usage: 196484 KB (Peak: 196604 KB) +Design Loading CPU Usage: 750 ms +Simulation completed +Simulation Memory Usage: 278220 KB (Peak: 335752 KB) +Simulation CPU Usage: 770 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..f100233 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_behav" "xil_defaultlib.project_tb" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..82742bd7c6cf92a1f2762db199788ce4320f7777 GIT binary patch literal 35624 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defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 9; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_behav/xsim.reloc", (void **)funcTab, 9); + iki_vhdl_file_variable_register(dp + 562288); + iki_vhdl_file_variable_register(dp + 562344); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..5b60d60e4f1f81d7ce4ed53082accd1f102ccf6c GIT binary patch literal 4520 zcmb`KU2GIp6vywDuZp;~_=V!fqG+noVYh`^jgs90WyJ;vZG#cbI6HgW9oX4jXJ%_5 zF<@$pm5>lLA<+l*L1SWKcm#RS1Y-2b_+m)ZnD`_X zch5QZbMKiwyls4}CzBB@8L?S(YD|R~xUHiXm0A?5MZcIRFI+iu3xV>{yMW8bHler} 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b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/Compile_Options.txt new file mode 100644 index 0000000..e7c995c --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_edge_behav" "xil_defaultlib.project_tb_edge" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o 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+/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_40(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[10] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 10; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc", (void **)funcTab, 10); + iki_vhdl_file_variable_register(dp + 535048); + iki_vhdl_file_variable_register(dp + 535104); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_edge_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git 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slxFc`<$rAB*}SWs>i@<}h4rz7__63(u)Cz_f5BkYzjH!|gv-GH0jh|bdjJ3c literal 0 HcmV?d00001 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log new file mode 100644 index 0000000..c19589a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_edge_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_edge_behav/xsimk -simmode gui -wdb project_tb_edge_behav.wdb -simrunnum 0 -socket 59621 +Design successfully loaded +Design Loading Memory Usage: 198404 KB (Peak: 198404 KB) +Design Loading CPU Usage: 680 ms +Simulation completed +Simulation Memory Usage: 291592 KB (Peak: 337672 KB) +Simulation CPU Usage: 710 ms diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt new file mode 100644 index 0000000..43596fa --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_timing_behav" "xil_defaultlib.project_tb_timing" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o new file mode 100644 index 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0000000..a95fd1a --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_36(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void execute_34(char*, char *); +IKI_DLLESPEC extern void execute_35(char*, char *); +IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback}; +const int NumRelocateId= 9; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc", (void **)funcTab, 9); + iki_vhdl_file_variable_register(dp + 534752); + iki_vhdl_file_variable_register(dp + 534808); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_timing_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_timing_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_timing_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return 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z#T%6bj(wr*)lyl`y=01iJPC;Y4wpAK2y=L`l9?hd^|kdqoU2{s@WrnZN)L zPhUPrX!|R%csmqx#`c$VCWIWtTtUQ{EqKlll9ZbM-YaVSQOFs9cARMwF0ptE7jq6b z;tYfw#auzenJswE5Q+l;HU22%3_!bEf$wkHE=%|wRLuQ!(vbd!kfWL_h`6%_&mDr? zHdKtD#vdW~EO=@AEaA6TFtIa2Vi0mXas?4Fw&00DkOx;q3^o2JCPv$73IDiWI_gZ) z$tJHXm%e&WuE#e)6K|dp%{LvP=GoB1i%YmO&L%A}0U_7+TtU>Lp2qbzbKi?F9)6?#SG*>0|k9f(H55;rPNW6W68+i_?NFyQS+LSAZ z8p#%XBOw%zIBNV+*hm1fMmoti5|VEu@?9Ib0gY5Iec3>2SLybSeA;@B5BZ%RRRU8`| zLt+qeJaPpQF}C1|K`4$5)cB*A*d`F;w~y5bh-+dK>13mr<>J|Zwq_IeW;Cyf?b!^U ziz>w%@Hm_(qa?p1LHyJj`a(>(kER zdJBXVs+?FW8oLG|HAqvE6)$90pu7_;*&4jJ1%byx+Zt5^e_wAMDJPuWkOEg^!od4K zkK3lq6E^Hn7bR43qkRA_kF&{5pf!Uw?&8mAkQ}fDJD0y&1 | tee compile.log + +# compile VHDL design sources +echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj" +xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log + +echo "Waiting for jobs to finish..." +echo "No pending jobs, compilation finished." diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log new file mode 100644 index 0000000..81bee70 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log @@ -0,0 +1,36 @@ +Vivado Simulator v2025.2 +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log +Using 8 slave threads. +Starting static elaboration +Pass Through NonSizing Optimizer +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling package std.standard +Compiling package std.textio +Compiling package ieee.std_logic_1164 +Compiling package ieee.numeric_std +Compiling package vl.vl_types +Compiling module xil_defaultlib.glbl +Compiling module unisims_ver.x_lut2_mux4 +Compiling module unisims_ver.LUT2 +Compiling module unisims_ver.LUT4 +Compiling module unisims_ver.LUT5 +Compiling module unisims_ver.x_lut1_mux2 +Compiling module unisims_ver.LUT1 +Compiling module unisims_ver.x_lut3_mux8 +Compiling module unisims_ver.LUT3 +Compiling module unisims_ver.LUT6 +Compiling module unisims_ver.FDPE_default +Compiling module unisims_ver.FDCE_default +Compiling module unisims_ver.CARRY4 +Compiling module unisims_ver.FDRE_default +Compiling module unisims_ver.BUFG +Compiling module unisims_ver.IBUF +Compiling module unisims_ver.OBUF +Compiling module xil_defaultlib.project_reti_logiche +Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge +Built simulation snapshot project_tb_edge_func_synth diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh new file mode 100755 index 0000000..8c6335f --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Fri Jun 12 15:48:17 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log new file mode 100644 index 0000000..b83a9b4 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/hs_err_pid131429.log @@ -0,0 +1,24 @@ +# +# An unexpected error has occurred (11) Segmentation fault +# +Stack: +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7ff9b8e7195c] +/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7ff9b8e7242e] +/usr/lib/libc.so.6(+0x3e2d0) [0x7ff9f884d2d0] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7ff9c5d4ebcb] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7ff9c5d4f1e1] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector >&) const+0x6f) [0x7ff9c5d6a6ff] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0xb7) [0x7ff9c5dc2cd7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector >&) const+0x128) [0x7ff9c5dc60c8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7ff9c5da9596] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7ff9c5da3f64] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7ff9c5df1b2f] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7ff9c5df1ca4] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7ff9c5c391a7] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7ff9c5c3922c] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7ff9c5c3a8e8] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7ff9c5df137e] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7ff9c5e037da] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7ff9c5e03c62] +/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7ff9c5c050dc] +[0x7ff9a937ac6a] diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl new file mode 100644 index 0000000..fe47dd3 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run all diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v new file mode 100644 index 0000000..0af6440 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v @@ -0,0 +1,3225 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Fri Jun 12 15:48:15 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode funcsim -nolib -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_4_n_0 ; + wire \FSM_onehot_state[17]_i_5_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[21]_i_7_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire \current_mem_addr[0]_i_10_n_0 ; + wire \current_mem_addr[0]_i_11_n_0 ; + wire \current_mem_addr[0]_i_1_n_0 ; + wire \current_mem_addr[0]_i_2_n_0 ; + wire \current_mem_addr[0]_i_3_n_0 ; + wire \current_mem_addr[0]_i_4_n_0 ; + wire \current_mem_addr[0]_i_5_n_0 ; + wire \current_mem_addr[0]_i_6_n_0 ; + wire \current_mem_addr[0]_i_7_n_0 ; + wire \current_mem_addr[0]_i_8_n_0 ; + wire \current_mem_addr[0]_i_9_n_0 ; + wire \current_mem_addr[10]_i_1_n_0 ; + wire \current_mem_addr[10]_i_2_n_0 ; + wire \current_mem_addr[10]_i_3_n_0 ; + wire \current_mem_addr[10]_i_4_n_0 ; + wire \current_mem_addr[11]_i_10_n_0 ; + wire \current_mem_addr[11]_i_1_n_0 ; + wire \current_mem_addr[11]_i_2_n_0 ; + wire \current_mem_addr[11]_i_3_n_0 ; + wire \current_mem_addr[11]_i_4_n_0 ; + wire \current_mem_addr[11]_i_7_n_0 ; + wire \current_mem_addr[11]_i_8_n_0 ; + wire \current_mem_addr[11]_i_9_n_0 ; + wire \current_mem_addr[12]_i_1_n_0 ; + wire \current_mem_addr[12]_i_2_n_0 ; + wire \current_mem_addr[12]_i_3_n_0 ; + wire \current_mem_addr[12]_i_4_n_0 ; + wire \current_mem_addr[13]_i_1_n_0 ; + wire \current_mem_addr[13]_i_2_n_0 ; + wire \current_mem_addr[13]_i_3_n_0 ; + wire \current_mem_addr[13]_i_4_n_0 ; + wire \current_mem_addr[14]_i_1_n_0 ; + wire \current_mem_addr[14]_i_2_n_0 ; + wire \current_mem_addr[14]_i_3_n_0 ; + wire \current_mem_addr[14]_i_4_n_0 ; + wire \current_mem_addr[14]_i_5_n_0 ; + wire \current_mem_addr[14]_i_6_n_0 ; + wire \current_mem_addr[14]_i_7_n_0 ; + wire \current_mem_addr[14]_i_8_n_0 ; + wire \current_mem_addr[15]_i_13_n_0 ; + wire \current_mem_addr[15]_i_14_n_0 ; + wire \current_mem_addr[15]_i_15_n_0 ; + wire \current_mem_addr[15]_i_16_n_0 ; + wire \current_mem_addr[15]_i_17_n_0 ; + wire \current_mem_addr[15]_i_18_n_0 ; + wire \current_mem_addr[15]_i_19_n_0 ; + wire \current_mem_addr[15]_i_1_n_0 ; + wire \current_mem_addr[15]_i_20_n_0 ; + wire \current_mem_addr[15]_i_21_n_0 ; + wire \current_mem_addr[15]_i_22_n_0 ; + wire \current_mem_addr[15]_i_23_n_0 ; + wire \current_mem_addr[15]_i_24_n_0 ; + wire \current_mem_addr[15]_i_2_n_0 ; + wire \current_mem_addr[15]_i_3_n_0 ; + wire \current_mem_addr[15]_i_4_n_0 ; + wire \current_mem_addr[15]_i_5_n_0 ; + wire \current_mem_addr[15]_i_7_n_0 ; + wire \current_mem_addr[15]_i_8_n_0 ; + wire \current_mem_addr[1]_i_1_n_0 ; + wire \current_mem_addr[1]_i_2_n_0 ; + wire \current_mem_addr[1]_i_3_n_0 ; + wire \current_mem_addr[1]_i_4_n_0 ; + wire \current_mem_addr[1]_i_5_n_0 ; + wire \current_mem_addr[1]_i_6_n_0 ; + wire \current_mem_addr[1]_i_7_n_0 ; + wire \current_mem_addr[2]_i_1_n_0 ; + wire \current_mem_addr[2]_i_2_n_0 ; + wire \current_mem_addr[2]_i_3_n_0 ; + wire \current_mem_addr[2]_i_4_n_0 ; + wire \current_mem_addr[3]_i_10_n_0 ; + wire \current_mem_addr[3]_i_11_n_0 ; + wire \current_mem_addr[3]_i_12_n_0 ; + wire \current_mem_addr[3]_i_1_n_0 ; + wire \current_mem_addr[3]_i_2_n_0 ; + wire \current_mem_addr[3]_i_3_n_0 ; + wire \current_mem_addr[3]_i_4_n_0 ; + wire \current_mem_addr[3]_i_5_n_0 ; + wire \current_mem_addr[3]_i_6_n_0 ; + wire \current_mem_addr[3]_i_9_n_0 ; + wire \current_mem_addr[4]_i_10_n_0 ; + wire \current_mem_addr[4]_i_11_n_0 ; + wire \current_mem_addr[4]_i_12_n_0 ; + wire \current_mem_addr[4]_i_13_n_0 ; + wire \current_mem_addr[4]_i_1_n_0 ; + wire \current_mem_addr[4]_i_2_n_0 ; + wire \current_mem_addr[4]_i_3_n_0 ; + wire \current_mem_addr[4]_i_4_n_0 ; + wire \current_mem_addr[4]_i_5_n_0 ; + wire \current_mem_addr[4]_i_6_n_0 ; + wire \current_mem_addr[4]_i_7_n_0 ; + wire \current_mem_addr[5]_i_1_n_0 ; + wire \current_mem_addr[5]_i_2_n_0 ; + wire \current_mem_addr[5]_i_3_n_0 ; + wire \current_mem_addr[5]_i_4_n_0 ; + wire \current_mem_addr[5]_i_5_n_0 ; + wire \current_mem_addr[6]_i_1_n_0 ; + wire \current_mem_addr[6]_i_2_n_0 ; + wire \current_mem_addr[6]_i_3_n_0 ; + wire \current_mem_addr[6]_i_4_n_0 ; + wire \current_mem_addr[6]_i_5_n_0 ; + wire \current_mem_addr[7]_i_10_n_0 ; + wire \current_mem_addr[7]_i_11_n_0 ; + wire \current_mem_addr[7]_i_1_n_0 ; + wire \current_mem_addr[7]_i_2_n_0 ; + wire \current_mem_addr[7]_i_3_n_0 ; + wire \current_mem_addr[7]_i_4_n_0 ; + wire \current_mem_addr[7]_i_5_n_0 ; + wire \current_mem_addr[7]_i_8_n_0 ; + wire \current_mem_addr[7]_i_9_n_0 ; + wire \current_mem_addr[8]_i_10_n_0 ; + wire \current_mem_addr[8]_i_1_n_0 ; + wire \current_mem_addr[8]_i_2_n_0 ; + wire \current_mem_addr[8]_i_3_n_0 ; + wire \current_mem_addr[8]_i_4_n_0 ; + wire \current_mem_addr[8]_i_7_n_0 ; + wire \current_mem_addr[8]_i_8_n_0 ; + wire \current_mem_addr[8]_i_9_n_0 ; + wire \current_mem_addr[9]_i_1_n_0 ; + wire \current_mem_addr[9]_i_2_n_0 ; + wire \current_mem_addr[9]_i_3_n_0 ; + wire \current_mem_addr[9]_i_4_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_1 ; + wire \current_mem_addr_reg[11]_i_5_n_2 ; + wire \current_mem_addr_reg[11]_i_5_n_3 ; + wire \current_mem_addr_reg[11]_i_6_n_0 ; + wire \current_mem_addr_reg[11]_i_6_n_1 ; + wire \current_mem_addr_reg[11]_i_6_n_2 ; + wire \current_mem_addr_reg[11]_i_6_n_3 ; + wire \current_mem_addr_reg[12]_i_5_n_0 ; + wire \current_mem_addr_reg[12]_i_5_n_1 ; + wire \current_mem_addr_reg[12]_i_5_n_2 ; + wire \current_mem_addr_reg[12]_i_5_n_3 ; + wire \current_mem_addr_reg[15]_i_10_n_1 ; + wire \current_mem_addr_reg[15]_i_10_n_2 ; + wire \current_mem_addr_reg[15]_i_10_n_3 ; + wire \current_mem_addr_reg[15]_i_11_n_1 ; + wire \current_mem_addr_reg[15]_i_11_n_2 ; + wire \current_mem_addr_reg[15]_i_11_n_3 ; + wire \current_mem_addr_reg[15]_i_12_n_0 ; + wire \current_mem_addr_reg[15]_i_12_n_1 ; + wire \current_mem_addr_reg[15]_i_12_n_2 ; + wire \current_mem_addr_reg[15]_i_12_n_3 ; + wire \current_mem_addr_reg[15]_i_6_n_2 ; + wire \current_mem_addr_reg[15]_i_6_n_3 ; + wire \current_mem_addr_reg[15]_i_9_n_2 ; + wire \current_mem_addr_reg[15]_i_9_n_3 ; + wire \current_mem_addr_reg[3]_i_7_n_0 ; + wire \current_mem_addr_reg[3]_i_7_n_1 ; + wire \current_mem_addr_reg[3]_i_7_n_2 ; + wire \current_mem_addr_reg[3]_i_7_n_3 ; + wire \current_mem_addr_reg[3]_i_8_n_0 ; + wire \current_mem_addr_reg[3]_i_8_n_1 ; + wire \current_mem_addr_reg[3]_i_8_n_2 ; + wire \current_mem_addr_reg[3]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_8_n_0 ; + wire \current_mem_addr_reg[4]_i_8_n_1 ; + wire \current_mem_addr_reg[4]_i_8_n_2 ; + wire \current_mem_addr_reg[4]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_9_n_0 ; + wire \current_mem_addr_reg[4]_i_9_n_1 ; + wire \current_mem_addr_reg[4]_i_9_n_2 ; + wire \current_mem_addr_reg[4]_i_9_n_3 ; + wire \current_mem_addr_reg[7]_i_6_n_0 ; + wire \current_mem_addr_reg[7]_i_6_n_1 ; + wire \current_mem_addr_reg[7]_i_6_n_2 ; + wire \current_mem_addr_reg[7]_i_6_n_3 ; + wire \current_mem_addr_reg[7]_i_7_n_0 ; + wire \current_mem_addr_reg[7]_i_7_n_1 ; + wire \current_mem_addr_reg[7]_i_7_n_2 ; + wire \current_mem_addr_reg[7]_i_7_n_3 ; + wire \current_mem_addr_reg[8]_i_5_n_0 ; + wire \current_mem_addr_reg[8]_i_5_n_1 ; + wire \current_mem_addr_reg[8]_i_5_n_2 ; + wire \current_mem_addr_reg[8]_i_5_n_3 ; + wire \current_mem_addr_reg[8]_i_6_n_0 ; + wire \current_mem_addr_reg[8]_i_6_n_1 ; + wire \current_mem_addr_reg[8]_i_6_n_2 ; + wire \current_mem_addr_reg[8]_i_6_n_3 ; + wire [5:0]current_popped_id; + wire \current_popped_id[5]_i_1_n_0 ; + wire \current_popped_id[5]_i_2_n_0 ; + wire [7:0]current_task_count; + wire \current_task_count[0]_i_1_n_0 ; + wire \current_task_count[1]_i_1_n_0 ; + wire \current_task_count[2]_i_1_n_0 ; + wire \current_task_count[3]_i_1_n_0 ; + wire \current_task_count[4]_i_1_n_0 ; + wire \current_task_count[4]_i_2_n_0 ; + wire \current_task_count[5]_i_1_n_0 ; + wire \current_task_count[5]_i_2_n_0 ; + wire \current_task_count[5]_i_3_n_0 ; + wire \current_task_count[6]_i_1_n_0 ; + wire \current_task_count[7]_i_1_n_0 ; + wire \current_task_count[7]_i_2_n_0 ; + wire \current_task_count[7]_i_3_n_0 ; + wire \current_task_count[7]_i_4_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in23; + wire [15:1]in26; + wire [15:1]in27; + wire [15:0]in30; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[3]_i_3_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_en_i_4_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire o_mem_we_i_3_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED ; + wire [0:0]\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_task_count[3]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_task_count[4]), + .I1(current_task_count[3]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(current_task_count[2]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[13]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h2100002100214200)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_3_n_0 ), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\FSM_onehot_state[12]_i_10_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[5]), + .I3(\current_task_count[5]_i_2_n_0 ), + .I4(o_mem_addr_OBUF[4]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_task_count[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF2)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[15]_i_3 + (.I0(i_task_id_IBUF[5]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[3]), + .I3(i_task_id_IBUF[4]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF1)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_4_n_0 ), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state[17]_i_4_n_0 ), + .I1(\FSM_onehot_state[17]_i_5_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[17]_i_4 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[17]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[17]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h20)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[17]_i_4_n_0 ), + .I2(\FSM_onehot_state[17]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000002)) + \FSM_onehot_state[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFFFEFF)) + \FSM_onehot_state[21]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(\FSM_onehot_state[21]_i_4_n_0 ), + .I2(\FSM_onehot_state[21]_i_5_n_0 ), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_7_n_0 ), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[15]), + .I3(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[10]), + .I1(o_mem_addr_OBUF[11]), + .I2(o_mem_addr_OBUF[9]), + .I3(o_mem_addr_OBUF[8]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'hBF0B)) + \FSM_onehot_state[21]_i_7 + (.I0(i_task_priority_IBUF[0]), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(i_task_priority_IBUF[1]), + .O(\FSM_onehot_state[21]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state[23]_i_4_n_0 ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[2] ), + .I5(\FSM_onehot_state[23]_i_5_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_2 + (.I0(o_mem_en_i_2_n_0), + .I1(\FSM_onehot_state[23]_i_6_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .I3(\FSM_onehot_state_reg_n_0_[7] ), + .I4(\FSM_onehot_state_reg_n_0_[14] ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[15] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[22] ), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[4] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA8)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[8]_i_2 + (.I0(current_task_count[7]), + .I1(current_task_count[6]), + .I2(current_task_count[3]), + .I3(current_task_count[4]), + .I4(current_task_count[5]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT6 #( + .INIT(64'hFF54FF54FFFFFF54)) + \current_mem_addr[0]_i_1 + (.I0(\current_mem_addr[0]_i_2_n_0 ), + .I1(\current_mem_addr[0]_i_3_n_0 ), + .I2(\current_mem_addr[0]_i_4_n_0 ), + .I3(\current_mem_addr[0]_i_5_n_0 ), + .I4(current_task_count[0]), + .I5(\current_mem_addr[0]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'hE)) + \current_mem_addr[0]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .O(\current_mem_addr[0]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'hFEEE)) + \current_mem_addr[0]_i_11 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000000000000777)) + \current_mem_addr[0]_i_2 + (.I0(in30[0]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .I4(\current_mem_addr[0]_i_7_n_0 ), + .I5(\current_mem_addr[3]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[0]_i_3 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + \current_mem_addr[0]_i_4 + (.I0(\current_mem_addr[0]_i_8_n_0 ), + .I1(\current_mem_addr[0]_i_9_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in30[0]), + .I4(\current_mem_addr[0]_i_10_n_0 ), + .I5(\current_mem_addr[0]_i_11_n_0 ), + .O(\current_mem_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAEFF00AEAE)) + \current_mem_addr[0]_i_5 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\current_mem_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \current_mem_addr[0]_i_6 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\current_mem_addr[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[0]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(o_mem_addr_OBUF[0]), + .O(\current_mem_addr[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h55555554)) + \current_mem_addr[0]_i_8 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[9] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[0]_i_9 + (.I0(\FSM_onehot_state[23]_i_4_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[8] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state_reg_n_0_[4] ), + .O(\current_mem_addr[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[10]_i_1 + (.I0(\current_mem_addr[10]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[10]), + .I3(\current_mem_addr[10]_i_3_n_0 ), + .I4(\current_mem_addr[10]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[10]_i_2 + (.I0(in26[10]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[10]_i_3 + (.I0(in30[10]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[10]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[10]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[10]), + .O(\current_mem_addr[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[11]_i_1 + (.I0(\current_mem_addr[11]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[11]), + .I3(\current_mem_addr[11]_i_3_n_0 ), + .I4(\current_mem_addr[11]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[11]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[11]_i_2 + (.I0(in26[11]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[11]_i_3 + (.I0(in27[11]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[11]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[11]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[11]), + .O(\current_mem_addr[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[11]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[12]_i_1 + (.I0(\current_mem_addr[12]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[12]), + .I3(\current_mem_addr[12]_i_3_n_0 ), + .I4(\current_mem_addr[12]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[12]_i_2 + (.I0(in26[12]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[12]_i_3 + (.I0(in30[12]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[12]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[12]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[12]), + .O(\current_mem_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[13]_i_1 + (.I0(\current_mem_addr[13]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[13]), + .I3(\current_mem_addr[13]_i_3_n_0 ), + .I4(\current_mem_addr[13]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[13]_i_2 + (.I0(in26[13]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[13]_i_3 + (.I0(in30[13]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[13]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[13]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[13]), + .O(\current_mem_addr[13]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[14]_i_1 + (.I0(\current_mem_addr[14]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[14]), + .I3(\current_mem_addr[14]_i_4_n_0 ), + .I4(\current_mem_addr[14]_i_5_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[14]_i_2 + (.I0(in26[14]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_mem_addr[14]_i_3 + (.I0(\current_mem_addr[14]_i_7_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\current_mem_addr[14]_i_8_n_0 ), + .O(\current_mem_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[14]_i_4 + (.I0(in30[14]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[14]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[14]_i_5 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[14]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[14]), + .O(\current_mem_addr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'h00000045)) + \current_mem_addr[14]_i_6 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[14]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[8] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\current_mem_addr[14]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .O(\current_mem_addr[14]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_mem_addr[15]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_16 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\current_mem_addr[15]_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_17 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_18 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_19 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \current_mem_addr[15]_i_2 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\current_mem_addr[15]_i_4_n_0 ), + .I3(\current_mem_addr[15]_i_5_n_0 ), + .I4(in26[15]), + .I5(\current_mem_addr[15]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_20 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_20_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_21 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_21_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_22 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[15]_i_22_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_23 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[15]_i_23_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_24 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[15]_i_24_n_0 )); + LUT6 #( + .INIT(64'h0000000011010000)) + \current_mem_addr[15]_i_3 + (.I0(\FSM_onehot_state[1]_i_3_n_0 ), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\current_mem_addr[14]_i_3_n_0 ), + .I5(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[15]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[15]), + .O(\current_mem_addr[15]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[15]_i_5 + (.I0(in27[15]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[15]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[15]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h45)) + \current_mem_addr[15]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_8 + (.I0(\current_mem_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\current_mem_addr[14]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[1]_i_1 + (.I0(\current_mem_addr[1]_i_2_n_0 ), + .I1(\current_mem_addr[1]_i_3_n_0 ), + .I2(\current_mem_addr[1]_i_4_n_0 ), + .I3(\current_mem_addr[1]_i_5_n_0 ), + .I4(\current_mem_addr[1]_i_6_n_0 ), + .I5(\current_mem_addr[1]_i_7_n_0 ), + .O(\current_mem_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[1]_i_2 + (.I0(current_task_count[1]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA8A8AAA8AAAAAAAA)) + \current_mem_addr[1]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\current_mem_addr[14]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[1]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[1]), + .O(\current_mem_addr[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[1]_i_5 + (.I0(in30[1]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[1]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[1]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[1]_i_7 + (.I0(in26[1]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[1]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFEEFE)) + \current_mem_addr[2]_i_1 + (.I0(\current_mem_addr[2]_i_2_n_0 ), + .I1(\current_mem_addr[2]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[2]), + .I3(\current_mem_addr[15]_i_3_n_0 ), + .I4(\current_mem_addr[2]_i_4_n_0 ), + .O(\current_mem_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[2]_i_2 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[2]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[2]), + .O(\current_mem_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[2]_i_3 + (.I0(in30[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[2]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[2]_i_4 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[2]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[2]), + .O(\current_mem_addr[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF0FFB0)) + \current_mem_addr[3]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\current_mem_addr[3]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[3]), + .I3(\current_mem_addr[3]_i_3_n_0 ), + .I4(\current_mem_addr[3]_i_4_n_0 ), + .I5(\current_mem_addr[3]_i_5_n_0 ), + .O(\current_mem_addr[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_10 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[3]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_11 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[3]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_12 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_12_n_0 )); + LUT5 #( + .INIT(32'h0000008A)) + \current_mem_addr[3]_i_2 + (.I0(\current_mem_addr[14]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[3]_i_3 + (.I0(\current_mem_addr[3]_i_6_n_0 ), + .I1(in23[3]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[3]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[3]), + .O(\current_mem_addr[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[3]_i_4 + (.I0(in23[3]), + .I1(\current_mem_addr[15]_i_8_n_0 ), + .O(\current_mem_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[3]_i_5 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[3]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[3]), + .O(\current_mem_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[3]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_mem_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[4]_i_1 + (.I0(\current_mem_addr[4]_i_2_n_0 ), + .I1(\current_mem_addr[4]_i_3_n_0 ), + .I2(\current_mem_addr[4]_i_4_n_0 ), + .I3(\current_mem_addr[4]_i_5_n_0 ), + .I4(\current_mem_addr[4]_i_6_n_0 ), + .I5(\current_mem_addr[4]_i_7_n_0 ), + .O(\current_mem_addr[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_10 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[4]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_11 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[4]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_12 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[4]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_13 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[4]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[4]_i_2 + (.I0(current_task_count[4]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[4]_i_3 + (.I0(in26[4]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[4]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[4]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[4]), + .O(\current_mem_addr[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[4]_i_5 + (.I0(in30[4]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in26[4]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in27[4]), + .O(\current_mem_addr[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hAA8A)) + \current_mem_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\current_mem_addr[14]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[5]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\current_mem_addr[5]_i_2_n_0 ), + .I3(\current_mem_addr[5]_i_3_n_0 ), + .I4(\current_mem_addr[5]_i_4_n_0 ), + .I5(\current_mem_addr[5]_i_5_n_0 ), + .O(\current_mem_addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[5]_i_2 + (.I0(in26[5]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[5]_i_3 + (.I0(in26[5]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[5]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[5]), + .O(\current_mem_addr[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[5]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[5]), + .O(\current_mem_addr[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[5]_i_5 + (.I0(current_task_count[5]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[6]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\current_mem_addr[6]_i_2_n_0 ), + .I3(\current_mem_addr[6]_i_3_n_0 ), + .I4(\current_mem_addr[6]_i_4_n_0 ), + .I5(\current_mem_addr[6]_i_5_n_0 ), + .O(\current_mem_addr[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[6]_i_2 + (.I0(in26[6]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[6]_i_3 + (.I0(in26[6]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[6]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[6]), + .O(\current_mem_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[6]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[6]), + .O(\current_mem_addr[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[6]_i_5 + (.I0(current_task_count[6]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[7]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\current_mem_addr[7]_i_2_n_0 ), + .I3(\current_mem_addr[7]_i_3_n_0 ), + .I4(\current_mem_addr[7]_i_4_n_0 ), + .I5(\current_mem_addr[7]_i_5_n_0 ), + .O(\current_mem_addr[7]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[7]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_11 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[7]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[7]_i_2 + (.I0(in26[7]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[7]_i_3 + (.I0(in26[7]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[7]), + .O(\current_mem_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[7]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[7]), + .O(\current_mem_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[7]_i_5 + (.I0(current_task_count[7]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[7]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[7]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[8]_i_1 + (.I0(\current_mem_addr[8]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[8]), + .I3(\current_mem_addr[8]_i_3_n_0 ), + .I4(\current_mem_addr[8]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[8]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[8]_i_2 + (.I0(in26[8]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[8]_i_3 + (.I0(in30[8]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[8]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[8]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[8]), + .O(\current_mem_addr[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[8]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[8]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[9]_i_1 + (.I0(\current_mem_addr[9]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[9]), + .I3(\current_mem_addr[9]_i_3_n_0 ), + .I4(\current_mem_addr[9]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[9]_i_2 + (.I0(in26[9]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[9]_i_3 + (.I0(in30[9]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[9]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[9]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[9]), + .O(\current_mem_addr[9]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_5 + (.CI(\current_mem_addr_reg[7]_i_6_n_0 ), + .CO({\current_mem_addr_reg[11]_i_5_n_0 ,\current_mem_addr_reg[11]_i_5_n_1 ,\current_mem_addr_reg[11]_i_5_n_2 ,\current_mem_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_6 + (.CI(\current_mem_addr_reg[7]_i_7_n_0 ), + .CO({\current_mem_addr_reg[11]_i_6_n_0 ,\current_mem_addr_reg[11]_i_6_n_1 ,\current_mem_addr_reg[11]_i_6_n_2 ,\current_mem_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in30[11:8]), + .S({\current_mem_addr[11]_i_7_n_0 ,\current_mem_addr[11]_i_8_n_0 ,\current_mem_addr[11]_i_9_n_0 ,\current_mem_addr[11]_i_10_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[12]_i_5 + (.CI(\current_mem_addr_reg[8]_i_6_n_0 ), + .CO({\current_mem_addr_reg[12]_i_5_n_0 ,\current_mem_addr_reg[12]_i_5_n_1 ,\current_mem_addr_reg[12]_i_5_n_2 ,\current_mem_addr_reg[12]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_10 + (.CI(\current_mem_addr_reg[11]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_10_n_1 ,\current_mem_addr_reg[15]_i_10_n_2 ,\current_mem_addr_reg[15]_i_10_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[15:12]), + .S(o_mem_addr_OBUF[15:12])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_11 + (.CI(\current_mem_addr_reg[11]_i_6_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_11_n_1 ,\current_mem_addr_reg[15]_i_11_n_2 ,\current_mem_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in30[15:12]), + .S({\current_mem_addr[15]_i_17_n_0 ,\current_mem_addr[15]_i_18_n_0 ,\current_mem_addr[15]_i_19_n_0 ,\current_mem_addr[15]_i_20_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_12 + (.CI(\current_mem_addr_reg[8]_i_5_n_0 ), + .CO({\current_mem_addr_reg[15]_i_12_n_0 ,\current_mem_addr_reg[15]_i_12_n_1 ,\current_mem_addr_reg[15]_i_12_n_2 ,\current_mem_addr_reg[15]_i_12_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in26[12:9]), + .S({\current_mem_addr[15]_i_21_n_0 ,\current_mem_addr[15]_i_22_n_0 ,\current_mem_addr[15]_i_23_n_0 ,\current_mem_addr[15]_i_24_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_6 + (.CI(\current_mem_addr_reg[15]_i_12_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_6_n_2 ,\current_mem_addr_reg[15]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED [3],in26[15:13]}), + .S({1'b0,\current_mem_addr[15]_i_13_n_0 ,\current_mem_addr[15]_i_14_n_0 ,\current_mem_addr[15]_i_15_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_9 + (.CI(\current_mem_addr_reg[12]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_9_n_2 ,\current_mem_addr_reg[15]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED [3],in23[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_7 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_7_n_0 ,\current_mem_addr_reg[3]_i_7_n_1 ,\current_mem_addr_reg[3]_i_7_n_2 ,\current_mem_addr_reg[3]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in27[3:1],in30[0]}), + .S({o_mem_addr_OBUF[3:2],\current_mem_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_8_n_0 ,\current_mem_addr_reg[3]_i_8_n_1 ,\current_mem_addr_reg[3]_i_8_n_2 ,\current_mem_addr_reg[3]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in30[3:1],\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED [0]}), + .S({\current_mem_addr[3]_i_10_n_0 ,\current_mem_addr[3]_i_11_n_0 ,\current_mem_addr[3]_i_12_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_8_n_0 ,\current_mem_addr_reg[4]_i_8_n_1 ,\current_mem_addr_reg[4]_i_8_n_2 ,\current_mem_addr_reg[4]_i_8_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in26[4:1]), + .S({\current_mem_addr[4]_i_10_n_0 ,\current_mem_addr[4]_i_11_n_0 ,\current_mem_addr[4]_i_12_n_0 ,\current_mem_addr[4]_i_13_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_9 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_9_n_0 ,\current_mem_addr_reg[4]_i_9_n_1 ,\current_mem_addr_reg[4]_i_9_n_2 ,\current_mem_addr_reg[4]_i_9_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_6 + (.CI(\current_mem_addr_reg[3]_i_7_n_0 ), + .CO({\current_mem_addr_reg[7]_i_6_n_0 ,\current_mem_addr_reg[7]_i_6_n_1 ,\current_mem_addr_reg[7]_i_6_n_2 ,\current_mem_addr_reg[7]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_7 + (.CI(\current_mem_addr_reg[3]_i_8_n_0 ), + .CO({\current_mem_addr_reg[7]_i_7_n_0 ,\current_mem_addr_reg[7]_i_7_n_1 ,\current_mem_addr_reg[7]_i_7_n_2 ,\current_mem_addr_reg[7]_i_7_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in30[7:4]), + .S({\current_mem_addr[7]_i_8_n_0 ,\current_mem_addr[7]_i_9_n_0 ,\current_mem_addr[7]_i_10_n_0 ,\current_mem_addr[7]_i_11_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_5 + (.CI(\current_mem_addr_reg[4]_i_8_n_0 ), + .CO({\current_mem_addr_reg[8]_i_5_n_0 ,\current_mem_addr_reg[8]_i_5_n_1 ,\current_mem_addr_reg[8]_i_5_n_2 ,\current_mem_addr_reg[8]_i_5_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in26[8:5]), + .S({\current_mem_addr[8]_i_7_n_0 ,\current_mem_addr[8]_i_8_n_0 ,\current_mem_addr[8]_i_9_n_0 ,\current_mem_addr[8]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_6 + (.CI(\current_mem_addr_reg[4]_i_9_n_0 ), + .CO({\current_mem_addr_reg[8]_i_6_n_0 ,\current_mem_addr_reg[8]_i_6_n_1 ,\current_mem_addr_reg[8]_i_6_n_2 ,\current_mem_addr_reg[8]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000EA)) + \current_popped_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555540)) + \current_popped_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(i_start_IBUF), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_popped_id[0]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_popped_id[1]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_popped_id[2]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_popped_id[3]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_popped_id[4]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_popped_id[5]), + .R(\current_popped_id[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'h54)) + \current_task_count[0]_i_1 + (.I0(current_task_count[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_task_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_task_count[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_task_count[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_task_count[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[3]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[2]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBEAA)) + \current_task_count[4]_i_1 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_task_count[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[4]), + .O(\current_task_count[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF44FF4F444444444)) + \current_task_count[5]_i_1 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[5]), + .I3(current_task_count[4]), + .I4(\current_task_count[5]_i_3_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_task_count[5]_i_2 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[2]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[3]), + .O(\current_task_count[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + \current_task_count[5]_i_3 + (.I0(current_task_count[3]), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(current_task_count[2]), + .O(\current_task_count[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h8FF48484)) + \current_task_count[6]_i_1 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[6]), + .I3(\current_task_count[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_task_count[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[0] ), + .O(\current_task_count[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4CFF4F084C084C0)) + \current_task_count[7]_i_2 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \current_task_count[7]_i_3 + (.I0(current_task_count[4]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[5]), + .O(\current_task_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_task_count[7]_i_4 + (.I0(current_task_count[2]), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[3]), + .I4(current_task_count[5]), + .I5(current_task_count[4]), + .O(\current_task_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[0]_i_1_n_0 ), + .Q(current_task_count[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[1]_i_1_n_0 ), + .Q(current_task_count[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[2]_i_1_n_0 ), + .Q(current_task_count[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[3]_i_1_n_0 ), + .Q(current_task_count[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[4]_i_1_n_0 ), + .Q(current_task_count[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[5]_i_1_n_0 ), + .Q(current_task_count[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[6]_i_1_n_0 ), + .Q(current_task_count[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[7]_i_2_n_0 ), + .Q(current_task_count[7]), + .R(1'b0)); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT6 #( + .INIT(64'hFFE0FFE0FFFFFFE0)) + \o_mem_data[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .I2(i_mem_data_IBUF[0]), + .I3(\o_mem_data[0]_i_2_n_0 ), + .I4(i_task_priority_IBUF[0]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_task_count[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFBAFFBAFFFFFFBA)) + \o_mem_data[1]_i_1 + (.I0(\o_mem_data[1]_i_2_n_0 ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[11]_i_1_n_0 ), + .I3(\o_mem_data[1]_i_4_n_0 ), + .I4(i_mem_data_IBUF[1]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAA8880)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[0]), + .I4(i_task_priority_IBUF[1]), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_3 + (.I0(current_task_count[0]), + .I1(current_task_count[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888F8888888888)) + \o_mem_data[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(\o_mem_data[3]_i_3_n_0 ), + .I4(i_task_id_IBUF[1]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h2AAA8000)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[2]), + .I4(current_task_count[3]), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888888000000008)) + \o_mem_data[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(current_task_count[3]), + .O(\o_mem_data[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\o_mem_data[4]_i_2_n_0 ), + .I3(i_task_id_IBUF[2]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBEAAAAAA)) + \o_mem_data[4]_i_2 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[5]), + .I2(\o_mem_data[5]_i_2_n_0 ), + .I3(i_task_id_IBUF[3]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4F444444)) + \o_mem_data[5]_i_2 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\o_mem_data[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5555555555555556)) + \o_mem_data[5]_i_3 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[3]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[2]), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[6]_i_1 + (.I0(\o_mem_data[6]_i_2_n_0 ), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_3_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_2 + (.I0(current_task_count[6]), + .I1(current_task_count[4]), + .I2(current_task_count[5]), + .I3(\current_task_count[5]_i_3_n_0 ), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h55554055)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h82)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_task_count[7]_i_3_n_0 ), + .I2(current_task_count[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'hE200)) + \o_mem_data[6]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(\FSM_onehot_state[21]_i_2_n_0 ), + .I2(i_mem_data_IBUF[6]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(i_task_id_IBUF[5]), + .I4(\o_mem_data[7]_i_3_n_0 ), + .I5(\o_mem_data[7]_i_4_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FB00FB)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\o_mem_data[7]_i_5_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\FSM_onehot_state[21]_i_2_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h88080080)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\current_task_count[7]_i_4_n_0 ), + .I3(current_task_count[6]), + .I4(current_task_count[7]), + .O(\o_mem_data[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA208)) + \o_mem_data[7]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[6]), + .I2(\current_task_count[7]_i_3_n_0 ), + .I3(current_task_count[7]), + .O(\o_mem_data[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \o_mem_data[7]_i_5 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_we_i_3_n_0), + .I3(o_mem_en_i_2_n_0), + .I4(o_mem_en_i_3_n_0), + .I5(\FSM_onehot_state[17]_i_3_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(\FSM_onehot_state[10]_i_1_n_0 ), + .I3(o_mem_en_i_4_n_0), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(o_mem_en_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + o_mem_en_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[22] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .O(o_mem_en_i_4_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hFFFD)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(o_mem_we_i_3_n_0), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(ctrl_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000111)) + o_mem_we_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[22] ), + .O(o_mem_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0444)) + o_mem_we_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(o_mem_we_i_3_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 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zZ_-GoNTZr`y} zhu_G}Qf-QD%x}9Hu2LU9GIRXE0hL6RM?Q3~*u=%M_U8__18+6u^rDykcbZqJ+* z&XjPJZ*ZN?x0yT;f2=O)^qr-aw*m@>oo$m!#|EU=CN6yOd~p0^UDNfYuT9&Hrfs?- z?)*q|OUklcEZ4Zbuj%pdt|&iE*AtmJx~<(wErKU49pxW9RO)xiwJomAoJbrJoV72l z>Ce0(GC%iZj8AD>Zt3}33%ZL 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v new file mode 100644 index 0000000..876045e --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v @@ -0,0 +1,3225 @@ +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 +// Date : Fri Jun 12 14:53:04 2026 +// Host : cachyos-x8664 running 64-bit CachyOS +// Command : write_verilog -mode funcsim -nolib -force -file +// /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.v +// Design : project_reti_logiche +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7a200tfbg484-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* NotValidForBitStream *) +module project_reti_logiche + (i_clk, + i_rst, + i_start, + i_task_id, + i_task_priority, + i_op, + o_done, + o_task_id, + o_mem_addr, + i_mem_data, + o_mem_data, + o_mem_we, + o_mem_en); + input i_clk; + input i_rst; + input i_start; + input [5:0]i_task_id; + input [1:0]i_task_priority; + input [1:0]i_op; + output o_done; + output [5:0]o_task_id; + output [15:0]o_mem_addr; + input [7:0]i_mem_data; + output [7:0]o_mem_data; + output o_mem_we; + output o_mem_en; + + wire \FSM_onehot_state[10]_i_1_n_0 ; + wire \FSM_onehot_state[11]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_10_n_0 ; + wire \FSM_onehot_state[12]_i_11_n_0 ; + wire \FSM_onehot_state[12]_i_1_n_0 ; + wire \FSM_onehot_state[12]_i_4_n_0 ; + wire \FSM_onehot_state[12]_i_5_n_0 ; + wire \FSM_onehot_state[12]_i_6_n_0 ; + wire \FSM_onehot_state[12]_i_7_n_0 ; + wire \FSM_onehot_state[12]_i_8_n_0 ; + wire \FSM_onehot_state[12]_i_9_n_0 ; + wire \FSM_onehot_state[14]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_1_n_0 ; + wire \FSM_onehot_state[15]_i_2_n_0 ; + wire \FSM_onehot_state[15]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_1_n_0 ; + wire \FSM_onehot_state[17]_i_2_n_0 ; + wire \FSM_onehot_state[17]_i_3_n_0 ; + wire \FSM_onehot_state[17]_i_4_n_0 ; + wire \FSM_onehot_state[17]_i_5_n_0 ; + wire \FSM_onehot_state[19]_i_1_n_0 ; + wire \FSM_onehot_state[19]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_1_n_0 ; + wire \FSM_onehot_state[1]_i_2_n_0 ; + wire \FSM_onehot_state[1]_i_3_n_0 ; + wire \FSM_onehot_state[1]_i_4_n_0 ; + wire \FSM_onehot_state[1]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_1_n_0 ; + wire \FSM_onehot_state[21]_i_2_n_0 ; + wire \FSM_onehot_state[21]_i_3_n_0 ; + wire \FSM_onehot_state[21]_i_4_n_0 ; + wire \FSM_onehot_state[21]_i_5_n_0 ; + wire \FSM_onehot_state[21]_i_6_n_0 ; + wire \FSM_onehot_state[21]_i_7_n_0 ; + wire \FSM_onehot_state[22]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_1_n_0 ; + wire \FSM_onehot_state[23]_i_2_n_0 ; + wire \FSM_onehot_state[23]_i_3_n_0 ; + wire \FSM_onehot_state[23]_i_4_n_0 ; + wire \FSM_onehot_state[23]_i_5_n_0 ; + wire \FSM_onehot_state[23]_i_6_n_0 ; + wire \FSM_onehot_state[3]_i_1_n_0 ; + wire \FSM_onehot_state[4]_i_1_n_0 ; + wire \FSM_onehot_state[6]_i_1_n_0 ; + wire \FSM_onehot_state[7]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_1_n_0 ; + wire \FSM_onehot_state[8]_i_2_n_0 ; + wire \FSM_onehot_state_reg[12]_i_2_n_2 ; + wire \FSM_onehot_state_reg[12]_i_2_n_3 ; + wire \FSM_onehot_state_reg[12]_i_3_n_0 ; + wire \FSM_onehot_state_reg[12]_i_3_n_1 ; + wire \FSM_onehot_state_reg[12]_i_3_n_2 ; + wire \FSM_onehot_state_reg[12]_i_3_n_3 ; + wire \FSM_onehot_state_reg_n_0_[0] ; + wire \FSM_onehot_state_reg_n_0_[10] ; + wire \FSM_onehot_state_reg_n_0_[11] ; + wire \FSM_onehot_state_reg_n_0_[12] ; + wire \FSM_onehot_state_reg_n_0_[13] ; + wire \FSM_onehot_state_reg_n_0_[14] ; + wire \FSM_onehot_state_reg_n_0_[15] ; + wire \FSM_onehot_state_reg_n_0_[16] ; + wire \FSM_onehot_state_reg_n_0_[17] ; + wire \FSM_onehot_state_reg_n_0_[18] ; + wire \FSM_onehot_state_reg_n_0_[19] ; + wire \FSM_onehot_state_reg_n_0_[1] ; + wire \FSM_onehot_state_reg_n_0_[20] ; + wire \FSM_onehot_state_reg_n_0_[21] ; + wire \FSM_onehot_state_reg_n_0_[22] ; + wire \FSM_onehot_state_reg_n_0_[23] ; + wire \FSM_onehot_state_reg_n_0_[2] ; + wire \FSM_onehot_state_reg_n_0_[3] ; + wire \FSM_onehot_state_reg_n_0_[4] ; + wire \FSM_onehot_state_reg_n_0_[5] ; + wire \FSM_onehot_state_reg_n_0_[6] ; + wire \FSM_onehot_state_reg_n_0_[7] ; + wire \FSM_onehot_state_reg_n_0_[8] ; + wire \FSM_onehot_state_reg_n_0_[9] ; + wire ctrl_done; + wire ctrl_mem_en; + wire ctrl_mem_we; + wire \current_mem_addr[0]_i_10_n_0 ; + wire \current_mem_addr[0]_i_11_n_0 ; + wire \current_mem_addr[0]_i_1_n_0 ; + wire \current_mem_addr[0]_i_2_n_0 ; + wire \current_mem_addr[0]_i_3_n_0 ; + wire \current_mem_addr[0]_i_4_n_0 ; + wire \current_mem_addr[0]_i_5_n_0 ; + wire \current_mem_addr[0]_i_6_n_0 ; + wire \current_mem_addr[0]_i_7_n_0 ; + wire \current_mem_addr[0]_i_8_n_0 ; + wire \current_mem_addr[0]_i_9_n_0 ; + wire \current_mem_addr[10]_i_1_n_0 ; + wire \current_mem_addr[10]_i_2_n_0 ; + wire \current_mem_addr[10]_i_3_n_0 ; + wire \current_mem_addr[10]_i_4_n_0 ; + wire \current_mem_addr[11]_i_10_n_0 ; + wire \current_mem_addr[11]_i_1_n_0 ; + wire \current_mem_addr[11]_i_2_n_0 ; + wire \current_mem_addr[11]_i_3_n_0 ; + wire \current_mem_addr[11]_i_4_n_0 ; + wire \current_mem_addr[11]_i_7_n_0 ; + wire \current_mem_addr[11]_i_8_n_0 ; + wire \current_mem_addr[11]_i_9_n_0 ; + wire \current_mem_addr[12]_i_1_n_0 ; + wire \current_mem_addr[12]_i_2_n_0 ; + wire \current_mem_addr[12]_i_3_n_0 ; + wire \current_mem_addr[12]_i_4_n_0 ; + wire \current_mem_addr[13]_i_1_n_0 ; + wire \current_mem_addr[13]_i_2_n_0 ; + wire \current_mem_addr[13]_i_3_n_0 ; + wire \current_mem_addr[13]_i_4_n_0 ; + wire \current_mem_addr[14]_i_1_n_0 ; + wire \current_mem_addr[14]_i_2_n_0 ; + wire \current_mem_addr[14]_i_3_n_0 ; + wire \current_mem_addr[14]_i_4_n_0 ; + wire \current_mem_addr[14]_i_5_n_0 ; + wire \current_mem_addr[14]_i_6_n_0 ; + wire \current_mem_addr[14]_i_7_n_0 ; + wire \current_mem_addr[14]_i_8_n_0 ; + wire \current_mem_addr[15]_i_13_n_0 ; + wire \current_mem_addr[15]_i_14_n_0 ; + wire \current_mem_addr[15]_i_15_n_0 ; + wire \current_mem_addr[15]_i_16_n_0 ; + wire \current_mem_addr[15]_i_17_n_0 ; + wire \current_mem_addr[15]_i_18_n_0 ; + wire \current_mem_addr[15]_i_19_n_0 ; + wire \current_mem_addr[15]_i_1_n_0 ; + wire \current_mem_addr[15]_i_20_n_0 ; + wire \current_mem_addr[15]_i_21_n_0 ; + wire \current_mem_addr[15]_i_22_n_0 ; + wire \current_mem_addr[15]_i_23_n_0 ; + wire \current_mem_addr[15]_i_24_n_0 ; + wire \current_mem_addr[15]_i_2_n_0 ; + wire \current_mem_addr[15]_i_3_n_0 ; + wire \current_mem_addr[15]_i_4_n_0 ; + wire \current_mem_addr[15]_i_5_n_0 ; + wire \current_mem_addr[15]_i_7_n_0 ; + wire \current_mem_addr[15]_i_8_n_0 ; + wire \current_mem_addr[1]_i_1_n_0 ; + wire \current_mem_addr[1]_i_2_n_0 ; + wire \current_mem_addr[1]_i_3_n_0 ; + wire \current_mem_addr[1]_i_4_n_0 ; + wire \current_mem_addr[1]_i_5_n_0 ; + wire \current_mem_addr[1]_i_6_n_0 ; + wire \current_mem_addr[1]_i_7_n_0 ; + wire \current_mem_addr[2]_i_1_n_0 ; + wire \current_mem_addr[2]_i_2_n_0 ; + wire \current_mem_addr[2]_i_3_n_0 ; + wire \current_mem_addr[2]_i_4_n_0 ; + wire \current_mem_addr[3]_i_10_n_0 ; + wire \current_mem_addr[3]_i_11_n_0 ; + wire \current_mem_addr[3]_i_12_n_0 ; + wire \current_mem_addr[3]_i_1_n_0 ; + wire \current_mem_addr[3]_i_2_n_0 ; + wire \current_mem_addr[3]_i_3_n_0 ; + wire \current_mem_addr[3]_i_4_n_0 ; + wire \current_mem_addr[3]_i_5_n_0 ; + wire \current_mem_addr[3]_i_6_n_0 ; + wire \current_mem_addr[3]_i_9_n_0 ; + wire \current_mem_addr[4]_i_10_n_0 ; + wire \current_mem_addr[4]_i_11_n_0 ; + wire \current_mem_addr[4]_i_12_n_0 ; + wire \current_mem_addr[4]_i_13_n_0 ; + wire \current_mem_addr[4]_i_1_n_0 ; + wire \current_mem_addr[4]_i_2_n_0 ; + wire \current_mem_addr[4]_i_3_n_0 ; + wire \current_mem_addr[4]_i_4_n_0 ; + wire \current_mem_addr[4]_i_5_n_0 ; + wire \current_mem_addr[4]_i_6_n_0 ; + wire \current_mem_addr[4]_i_7_n_0 ; + wire \current_mem_addr[5]_i_1_n_0 ; + wire \current_mem_addr[5]_i_2_n_0 ; + wire \current_mem_addr[5]_i_3_n_0 ; + wire \current_mem_addr[5]_i_4_n_0 ; + wire \current_mem_addr[5]_i_5_n_0 ; + wire \current_mem_addr[6]_i_1_n_0 ; + wire \current_mem_addr[6]_i_2_n_0 ; + wire \current_mem_addr[6]_i_3_n_0 ; + wire \current_mem_addr[6]_i_4_n_0 ; + wire \current_mem_addr[6]_i_5_n_0 ; + wire \current_mem_addr[7]_i_10_n_0 ; + wire \current_mem_addr[7]_i_11_n_0 ; + wire \current_mem_addr[7]_i_1_n_0 ; + wire \current_mem_addr[7]_i_2_n_0 ; + wire \current_mem_addr[7]_i_3_n_0 ; + wire \current_mem_addr[7]_i_4_n_0 ; + wire \current_mem_addr[7]_i_5_n_0 ; + wire \current_mem_addr[7]_i_8_n_0 ; + wire \current_mem_addr[7]_i_9_n_0 ; + wire \current_mem_addr[8]_i_10_n_0 ; + wire \current_mem_addr[8]_i_1_n_0 ; + wire \current_mem_addr[8]_i_2_n_0 ; + wire \current_mem_addr[8]_i_3_n_0 ; + wire \current_mem_addr[8]_i_4_n_0 ; + wire \current_mem_addr[8]_i_7_n_0 ; + wire \current_mem_addr[8]_i_8_n_0 ; + wire \current_mem_addr[8]_i_9_n_0 ; + wire \current_mem_addr[9]_i_1_n_0 ; + wire \current_mem_addr[9]_i_2_n_0 ; + wire \current_mem_addr[9]_i_3_n_0 ; + wire \current_mem_addr[9]_i_4_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_0 ; + wire \current_mem_addr_reg[11]_i_5_n_1 ; + wire \current_mem_addr_reg[11]_i_5_n_2 ; + wire \current_mem_addr_reg[11]_i_5_n_3 ; + wire \current_mem_addr_reg[11]_i_6_n_0 ; + wire \current_mem_addr_reg[11]_i_6_n_1 ; + wire \current_mem_addr_reg[11]_i_6_n_2 ; + wire \current_mem_addr_reg[11]_i_6_n_3 ; + wire \current_mem_addr_reg[12]_i_5_n_0 ; + wire \current_mem_addr_reg[12]_i_5_n_1 ; + wire \current_mem_addr_reg[12]_i_5_n_2 ; + wire \current_mem_addr_reg[12]_i_5_n_3 ; + wire \current_mem_addr_reg[15]_i_10_n_1 ; + wire \current_mem_addr_reg[15]_i_10_n_2 ; + wire \current_mem_addr_reg[15]_i_10_n_3 ; + wire \current_mem_addr_reg[15]_i_11_n_1 ; + wire \current_mem_addr_reg[15]_i_11_n_2 ; + wire \current_mem_addr_reg[15]_i_11_n_3 ; + wire \current_mem_addr_reg[15]_i_12_n_0 ; + wire \current_mem_addr_reg[15]_i_12_n_1 ; + wire \current_mem_addr_reg[15]_i_12_n_2 ; + wire \current_mem_addr_reg[15]_i_12_n_3 ; + wire \current_mem_addr_reg[15]_i_6_n_2 ; + wire \current_mem_addr_reg[15]_i_6_n_3 ; + wire \current_mem_addr_reg[15]_i_9_n_2 ; + wire \current_mem_addr_reg[15]_i_9_n_3 ; + wire \current_mem_addr_reg[3]_i_7_n_0 ; + wire \current_mem_addr_reg[3]_i_7_n_1 ; + wire \current_mem_addr_reg[3]_i_7_n_2 ; + wire \current_mem_addr_reg[3]_i_7_n_3 ; + wire \current_mem_addr_reg[3]_i_8_n_0 ; + wire \current_mem_addr_reg[3]_i_8_n_1 ; + wire \current_mem_addr_reg[3]_i_8_n_2 ; + wire \current_mem_addr_reg[3]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_8_n_0 ; + wire \current_mem_addr_reg[4]_i_8_n_1 ; + wire \current_mem_addr_reg[4]_i_8_n_2 ; + wire \current_mem_addr_reg[4]_i_8_n_3 ; + wire \current_mem_addr_reg[4]_i_9_n_0 ; + wire \current_mem_addr_reg[4]_i_9_n_1 ; + wire \current_mem_addr_reg[4]_i_9_n_2 ; + wire \current_mem_addr_reg[4]_i_9_n_3 ; + wire \current_mem_addr_reg[7]_i_6_n_0 ; + wire \current_mem_addr_reg[7]_i_6_n_1 ; + wire \current_mem_addr_reg[7]_i_6_n_2 ; + wire \current_mem_addr_reg[7]_i_6_n_3 ; + wire \current_mem_addr_reg[7]_i_7_n_0 ; + wire \current_mem_addr_reg[7]_i_7_n_1 ; + wire \current_mem_addr_reg[7]_i_7_n_2 ; + wire \current_mem_addr_reg[7]_i_7_n_3 ; + wire \current_mem_addr_reg[8]_i_5_n_0 ; + wire \current_mem_addr_reg[8]_i_5_n_1 ; + wire \current_mem_addr_reg[8]_i_5_n_2 ; + wire \current_mem_addr_reg[8]_i_5_n_3 ; + wire \current_mem_addr_reg[8]_i_6_n_0 ; + wire \current_mem_addr_reg[8]_i_6_n_1 ; + wire \current_mem_addr_reg[8]_i_6_n_2 ; + wire \current_mem_addr_reg[8]_i_6_n_3 ; + wire [5:0]current_popped_id; + wire \current_popped_id[5]_i_1_n_0 ; + wire \current_popped_id[5]_i_2_n_0 ; + wire [7:0]current_task_count; + wire \current_task_count[0]_i_1_n_0 ; + wire \current_task_count[1]_i_1_n_0 ; + wire \current_task_count[2]_i_1_n_0 ; + wire \current_task_count[3]_i_1_n_0 ; + wire \current_task_count[4]_i_1_n_0 ; + wire \current_task_count[4]_i_2_n_0 ; + wire \current_task_count[5]_i_1_n_0 ; + wire \current_task_count[5]_i_2_n_0 ; + wire \current_task_count[5]_i_3_n_0 ; + wire \current_task_count[6]_i_1_n_0 ; + wire \current_task_count[7]_i_1_n_0 ; + wire \current_task_count[7]_i_2_n_0 ; + wire \current_task_count[7]_i_3_n_0 ; + wire \current_task_count[7]_i_4_n_0 ; + wire i_clk; + wire i_clk_IBUF; + wire i_clk_IBUF_BUFG; + wire [7:0]i_mem_data; + wire [7:0]i_mem_data_IBUF; + wire [1:0]i_op; + wire [1:0]i_op_IBUF; + wire i_rst; + wire i_rst_IBUF; + wire i_start; + wire i_start_IBUF; + wire [5:0]i_task_id; + wire [5:0]i_task_id_IBUF; + wire [1:0]i_task_priority; + wire [1:0]i_task_priority_IBUF; + wire [15:1]in23; + wire [15:1]in26; + wire [15:1]in27; + wire [15:0]in30; + wire o_done; + wire o_done_OBUF; + wire [15:0]o_mem_addr; + wire [15:0]o_mem_addr_OBUF; + wire [7:0]o_mem_data; + wire \o_mem_data[0]_i_1_n_0 ; + wire \o_mem_data[0]_i_2_n_0 ; + wire \o_mem_data[1]_i_1_n_0 ; + wire \o_mem_data[1]_i_2_n_0 ; + wire \o_mem_data[1]_i_3_n_0 ; + wire \o_mem_data[1]_i_4_n_0 ; + wire \o_mem_data[2]_i_1_n_0 ; + wire \o_mem_data[2]_i_2_n_0 ; + wire \o_mem_data[3]_i_1_n_0 ; + wire \o_mem_data[3]_i_2_n_0 ; + wire \o_mem_data[3]_i_3_n_0 ; + wire \o_mem_data[4]_i_1_n_0 ; + wire \o_mem_data[4]_i_2_n_0 ; + wire \o_mem_data[5]_i_1_n_0 ; + wire \o_mem_data[5]_i_2_n_0 ; + wire \o_mem_data[5]_i_3_n_0 ; + wire \o_mem_data[6]_i_1_n_0 ; + wire \o_mem_data[6]_i_2_n_0 ; + wire \o_mem_data[6]_i_3_n_0 ; + wire \o_mem_data[6]_i_4_n_0 ; + wire \o_mem_data[6]_i_5_n_0 ; + wire \o_mem_data[7]_i_1_n_0 ; + wire \o_mem_data[7]_i_2_n_0 ; + wire \o_mem_data[7]_i_3_n_0 ; + wire \o_mem_data[7]_i_4_n_0 ; + wire \o_mem_data[7]_i_5_n_0 ; + wire [7:0]o_mem_data_OBUF; + wire o_mem_en; + wire o_mem_en_OBUF; + wire o_mem_en_i_2_n_0; + wire o_mem_en_i_3_n_0; + wire o_mem_en_i_4_n_0; + wire o_mem_we; + wire o_mem_we_OBUF; + wire o_mem_we_i_2_n_0; + wire o_mem_we_i_3_n_0; + wire [5:0]o_task_id; + wire \o_task_id[5]_i_1_n_0 ; + wire [5:0]o_task_id_OBUF; + wire [3:2]\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED ; + wire [3:0]\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED ; + wire [3:2]\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED ; + wire [3:3]\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED ; + wire [0:0]\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED ; + + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[10]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[9] ), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .O(\FSM_onehot_state[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[11]_i_1 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[11]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[12]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT4 #( + .INIT(16'h9555)) + \FSM_onehot_state[12]_i_10 + (.I0(current_task_count[3]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .O(\FSM_onehot_state[12]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair5" *) + LUT5 #( + .INIT(32'h95555555)) + \FSM_onehot_state[12]_i_11 + (.I0(current_task_count[4]), + .I1(current_task_count[3]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(current_task_count[2]), + .O(\FSM_onehot_state[12]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[12]_i_4 + (.I0(o_mem_addr_OBUF[15]), + .O(\FSM_onehot_state[12]_i_4_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_5 + (.I0(o_mem_addr_OBUF[13]), + .I1(o_mem_addr_OBUF[12]), + .I2(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[12]_i_5_n_0 )); + LUT3 #( + .INIT(8'h01)) + \FSM_onehot_state[12]_i_6 + (.I0(o_mem_addr_OBUF[9]), + .I1(o_mem_addr_OBUF[10]), + .I2(o_mem_addr_OBUF[11]), + .O(\FSM_onehot_state[12]_i_6_n_0 )); + LUT6 #( + .INIT(64'h2100002100214200)) + \FSM_onehot_state[12]_i_7 + (.I0(o_mem_addr_OBUF[7]), + .I1(o_mem_addr_OBUF[8]), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_3_n_0 ), + .I5(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[12]_i_7_n_0 )); + LUT6 #( + .INIT(64'h0000066006600000)) + \FSM_onehot_state[12]_i_8 + (.I0(\FSM_onehot_state[12]_i_10_n_0 ), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[5]), + .I3(\current_task_count[5]_i_2_n_0 ), + .I4(o_mem_addr_OBUF[4]), + .I5(\FSM_onehot_state[12]_i_11_n_0 ), + .O(\FSM_onehot_state[12]_i_8_n_0 )); + LUT6 #( + .INIT(64'h0000900906900000)) + \FSM_onehot_state[12]_i_9 + (.I0(current_task_count[2]), + .I1(o_mem_addr_OBUF[2]), + .I2(o_mem_addr_OBUF[1]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(o_mem_addr_OBUF[0]), + .O(\FSM_onehot_state[12]_i_9_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h40)) + \FSM_onehot_state[14]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF2)) + \FSM_onehot_state[15]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\FSM_onehot_state[15]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[15]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[15]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[15]_i_3 + (.I0(i_task_id_IBUF[5]), + .I1(i_task_id_IBUF[2]), + .I2(i_task_id_IBUF[3]), + .I3(i_task_id_IBUF[4]), + .I4(i_task_id_IBUF[1]), + .I5(i_task_id_IBUF[0]), + .O(\FSM_onehot_state[15]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair36" *) + LUT3 #( + .INIT(8'hF1)) + \FSM_onehot_state[17]_i_1 + (.I0(\FSM_onehot_state[17]_i_2_n_0 ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .O(\FSM_onehot_state[17]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + \FSM_onehot_state[17]_i_2 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .I3(\FSM_onehot_state[21]_i_4_n_0 ), + .I4(\FSM_onehot_state[21]_i_5_n_0 ), + .I5(\FSM_onehot_state[21]_i_6_n_0 ), + .O(\FSM_onehot_state[17]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h4F)) + \FSM_onehot_state[17]_i_3 + (.I0(\FSM_onehot_state[17]_i_4_n_0 ), + .I1(\FSM_onehot_state[17]_i_5_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .O(\FSM_onehot_state[17]_i_3_n_0 )); + LUT6 #( + .INIT(64'h6FF6FFFFFFFF6FF6)) + \FSM_onehot_state[17]_i_4 + (.I0(i_task_id_IBUF[0]), + .I1(i_mem_data_IBUF[2]), + .I2(i_mem_data_IBUF[3]), + .I3(i_task_id_IBUF[1]), + .I4(i_mem_data_IBUF[4]), + .I5(i_task_id_IBUF[2]), + .O(\FSM_onehot_state[17]_i_4_n_0 )); + LUT6 #( + .INIT(64'h9009000000009009)) + \FSM_onehot_state[17]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(i_mem_data_IBUF[6]), + .I2(i_task_id_IBUF[5]), + .I3(i_mem_data_IBUF[7]), + .I4(i_mem_data_IBUF[5]), + .I5(i_task_id_IBUF[3]), + .O(\FSM_onehot_state[17]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \FSM_onehot_state[19]_i_1 + (.I0(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\FSM_onehot_state[19]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT2 #( + .INIT(4'hB)) + \FSM_onehot_state[19]_i_2 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[19]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[1]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state[1]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair34" *) + LUT3 #( + .INIT(8'h20)) + \FSM_onehot_state[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[16] ), + .I1(\FSM_onehot_state[17]_i_4_n_0 ), + .I2(\FSM_onehot_state[17]_i_5_n_0 ), + .O(\FSM_onehot_state[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'h00000002)) + \FSM_onehot_state[1]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[1]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair37" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[14] ), + .I1(\FSM_onehot_state[15]_i_3_n_0 ), + .O(\FSM_onehot_state[1]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[1]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .O(\FSM_onehot_state[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT2 #( + .INIT(4'h8)) + \FSM_onehot_state[21]_i_1 + (.I0(\FSM_onehot_state[21]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[18] ), + .O(\FSM_onehot_state[21]_i_1_n_0 )); + LUT6 #( + .INIT(64'h00000000FFFFFEFF)) + \FSM_onehot_state[21]_i_2 + (.I0(\FSM_onehot_state[21]_i_3_n_0 ), + .I1(\FSM_onehot_state[21]_i_4_n_0 ), + .I2(\FSM_onehot_state[21]_i_5_n_0 ), + .I3(\FSM_onehot_state[21]_i_6_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state[21]_i_7_n_0 ), + .O(\FSM_onehot_state[21]_i_2_n_0 )); + LUT3 #( + .INIT(8'hFE)) + \FSM_onehot_state[21]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(o_mem_addr_OBUF[3]), + .I2(o_mem_addr_OBUF[2]), + .O(\FSM_onehot_state[21]_i_3_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_4 + (.I0(o_mem_addr_OBUF[5]), + .I1(o_mem_addr_OBUF[4]), + .I2(o_mem_addr_OBUF[7]), + .I3(o_mem_addr_OBUF[6]), + .O(\FSM_onehot_state[21]_i_4_n_0 )); + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[21]_i_5 + (.I0(o_mem_addr_OBUF[12]), + .I1(o_mem_addr_OBUF[13]), + .I2(o_mem_addr_OBUF[15]), + .I3(o_mem_addr_OBUF[14]), + .O(\FSM_onehot_state[21]_i_5_n_0 )); + LUT4 #( + .INIT(16'h0001)) + \FSM_onehot_state[21]_i_6 + (.I0(o_mem_addr_OBUF[10]), + .I1(o_mem_addr_OBUF[11]), + .I2(o_mem_addr_OBUF[9]), + .I3(o_mem_addr_OBUF[8]), + .O(\FSM_onehot_state[21]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT4 #( + .INIT(16'hBF0B)) + \FSM_onehot_state[21]_i_7 + (.I0(i_task_priority_IBUF[0]), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(i_task_priority_IBUF[1]), + .O(\FSM_onehot_state[21]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h80)) + \FSM_onehot_state[22]_i_1 + (.I0(i_op_IBUF[0]), + .I1(i_op_IBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\FSM_onehot_state[22]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFEFEFE)) + \FSM_onehot_state[23]_i_1 + (.I0(\FSM_onehot_state[23]_i_2_n_0 ), + .I1(\FSM_onehot_state[23]_i_3_n_0 ), + .I2(\FSM_onehot_state[23]_i_4_n_0 ), + .I3(i_start_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[2] ), + .I5(\FSM_onehot_state[23]_i_5_n_0 ), + .O(\FSM_onehot_state[23]_i_1_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_2 + (.I0(o_mem_en_i_2_n_0), + .I1(\FSM_onehot_state[23]_i_6_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[16] ), + .I3(\FSM_onehot_state_reg_n_0_[7] ), + .I4(\FSM_onehot_state_reg_n_0_[14] ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\FSM_onehot_state[23]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT4 #( + .INIT(16'hFFFE)) + \FSM_onehot_state[23]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[11] ), + .I3(\FSM_onehot_state_reg_n_0_[8] ), + .O(\FSM_onehot_state[23]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[23]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[15] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .O(\FSM_onehot_state[23]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \FSM_onehot_state[23]_i_5 + (.I0(\FSM_onehot_state_reg_n_0_[13] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[22] ), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\FSM_onehot_state[23]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT4 #( + .INIT(16'hEFEE)) + \FSM_onehot_state[23]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[4] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(i_start_IBUF), + .I3(\FSM_onehot_state_reg_n_0_[1] ), + .O(\FSM_onehot_state[23]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair33" *) + LUT3 #( + .INIT(8'h04)) + \FSM_onehot_state[3]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair23" *) + LUT2 #( + .INIT(4'hE)) + \FSM_onehot_state[4]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .O(\FSM_onehot_state[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT2 #( + .INIT(4'h2)) + \FSM_onehot_state[6]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\FSM_onehot_state[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair30" *) + LUT3 #( + .INIT(8'h08)) + \FSM_onehot_state[7]_i_1 + (.I0(i_op_IBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_op_IBUF[1]), + .O(\FSM_onehot_state[7]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair7" *) + LUT5 #( + .INIT(32'hAAAAAAA8)) + \FSM_onehot_state[8]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[7] ), + .I1(\FSM_onehot_state[8]_i_2_n_0 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .O(\FSM_onehot_state[8]_i_1_n_0 )); + LUT5 #( + .INIT(32'hFFFFFFFE)) + \FSM_onehot_state[8]_i_2 + (.I0(current_task_count[7]), + .I1(current_task_count[6]), + .I2(current_task_count[3]), + .I3(current_task_count[4]), + .I4(current_task_count[5]), + .O(\FSM_onehot_state[8]_i_2_n_0 )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDPE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .D(1'b0), + .PRE(i_rst_IBUF), + .Q(\FSM_onehot_state_reg_n_0_[0] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[10]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[10] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[11]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[11] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[12]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[12] )); + CARRY4 \FSM_onehot_state_reg[12]_i_2 + (.CI(\FSM_onehot_state_reg[12]_i_3_n_0 ), + .CO({\NLW_FSM_onehot_state_reg[12]_i_2_CO_UNCONNECTED [3:2],\FSM_onehot_state_reg[12]_i_2_n_2 ,\FSM_onehot_state_reg[12]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_2_O_UNCONNECTED [3:0]), + .S({1'b0,1'b0,\FSM_onehot_state[12]_i_4_n_0 ,\FSM_onehot_state[12]_i_5_n_0 })); + CARRY4 \FSM_onehot_state_reg[12]_i_3 + (.CI(1'b0), + .CO({\FSM_onehot_state_reg[12]_i_3_n_0 ,\FSM_onehot_state_reg[12]_i_3_n_1 ,\FSM_onehot_state_reg[12]_i_3_n_2 ,\FSM_onehot_state_reg[12]_i_3_n_3 }), + .CYINIT(1'b1), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(\NLW_FSM_onehot_state_reg[12]_i_3_O_UNCONNECTED [3:0]), + .S({\FSM_onehot_state[12]_i_6_n_0 ,\FSM_onehot_state[12]_i_7_n_0 ,\FSM_onehot_state[12]_i_8_n_0 ,\FSM_onehot_state[12]_i_9_n_0 })); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[12] ), + .Q(\FSM_onehot_state_reg_n_0_[13] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[14]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[14] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[15]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[15] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[16] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[15] ), + .Q(\FSM_onehot_state_reg_n_0_[16] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[17] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[17]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[17] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[18] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[17] ), + .Q(\FSM_onehot_state_reg_n_0_[18] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[19] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[19]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[19] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[1]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[1] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[20] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[19] ), + .Q(\FSM_onehot_state_reg_n_0_[20] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[21] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[21]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[21] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[22] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[22]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[22] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[23] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[22] ), + .Q(\FSM_onehot_state_reg_n_0_[23] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b1)) + \FSM_onehot_state_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[1] ), + .Q(\FSM_onehot_state_reg_n_0_[2] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[3]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[3] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[4]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[4] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[4] ), + .Q(\FSM_onehot_state_reg_n_0_[5] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[6]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[6] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[7]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[7] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state[8]_i_1_n_0 ), + .Q(\FSM_onehot_state_reg_n_0_[8] )); + (* FSM_ENCODED_STATES = "s_10_place_at_start:000000000100000000000000,s_01_wait_for_count:000000000000100000000000,s_01_go_next:000000000010000000000000,s_10_go_next:001000000000000000000000,s_10_compare:000001000000000000000000,s_00_read:000000000000000000001000,s_done:000000000000000000000010,s_10_wait:000000100000000000000000,s_10_check_id:000000010000000000000000,s_reset:000000000000000000000001,s_11_wait_for_count:100000000000000000000000,s_11_update_count:010000000000000000000000,s_01_copy:000000000001000000000000,s_idle:000000000000000000000100,s_01_check_end:000000000000010000000000,s_01_check_number:000000000000000010000000,s_10_wait_for_count:000100000000000000000000,s_00_go_next:000000000000000001000000,s_01_write:000000000000001000000000,s_10_update_count:000010000000000000000000,s_01_wait:000000000000000100000000,s_00_check:000000000000000000100000,s_00_wait:000000000000000000010000,s_10_wait_for_check:000000001000000000000000" *) + FDCE #( + .INIT(1'b0)) + \FSM_onehot_state_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\FSM_onehot_state[23]_i_1_n_0 ), + .CLR(i_rst_IBUF), + .D(\FSM_onehot_state_reg_n_0_[8] ), + .Q(\FSM_onehot_state_reg_n_0_[9] )); + LUT6 #( + .INIT(64'hFF54FF54FFFFFF54)) + \current_mem_addr[0]_i_1 + (.I0(\current_mem_addr[0]_i_2_n_0 ), + .I1(\current_mem_addr[0]_i_3_n_0 ), + .I2(\current_mem_addr[0]_i_4_n_0 ), + .I3(\current_mem_addr[0]_i_5_n_0 ), + .I4(current_task_count[0]), + .I5(\current_mem_addr[0]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair22" *) + LUT2 #( + .INIT(4'hE)) + \current_mem_addr[0]_i_10 + (.I0(\FSM_onehot_state_reg_n_0_[5] ), + .I1(\FSM_onehot_state_reg_n_0_[20] ), + .O(\current_mem_addr[0]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT4 #( + .INIT(16'hFEEE)) + \current_mem_addr[0]_i_11 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[0]_i_11_n_0 )); + LUT6 #( + .INIT(64'h0000000000000777)) + \current_mem_addr[0]_i_2 + (.I0(in30[0]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(o_mem_addr_OBUF[0]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .I4(\current_mem_addr[0]_i_7_n_0 ), + .I5(\current_mem_addr[3]_i_6_n_0 ), + .O(\current_mem_addr[0]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair21" *) + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[0]_i_3 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFEEE)) + \current_mem_addr[0]_i_4 + (.I0(\current_mem_addr[0]_i_8_n_0 ), + .I1(\current_mem_addr[0]_i_9_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[21] ), + .I3(in30[0]), + .I4(\current_mem_addr[0]_i_10_n_0 ), + .I5(\current_mem_addr[0]_i_11_n_0 ), + .O(\current_mem_addr[0]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFAEAEFF00AEAE)) + \current_mem_addr[0]_i_5 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(o_mem_addr_OBUF[0]), + .I5(\FSM_onehot_state_reg_n_0_[7] ), + .O(\current_mem_addr[0]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT3 #( + .INIT(8'h0E)) + \current_mem_addr[0]_i_6 + (.I0(\FSM_onehot_state[17]_i_3_n_0 ), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[15]_i_2_n_0 ), + .O(\current_mem_addr[0]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[0]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(o_mem_addr_OBUF[0]), + .O(\current_mem_addr[0]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT5 #( + .INIT(32'h55555554)) + \current_mem_addr[0]_i_8 + (.I0(o_mem_addr_OBUF[0]), + .I1(\FSM_onehot_state_reg_n_0_[6] ), + .I2(\FSM_onehot_state_reg_n_0_[9] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .I4(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[0]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[0]_i_9 + (.I0(\FSM_onehot_state[23]_i_4_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[23] ), + .I2(\FSM_onehot_state_reg_n_0_[8] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[3] ), + .I5(\FSM_onehot_state_reg_n_0_[4] ), + .O(\current_mem_addr[0]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[10]_i_1 + (.I0(\current_mem_addr[10]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[10]), + .I3(\current_mem_addr[10]_i_3_n_0 ), + .I4(\current_mem_addr[10]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[10]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[10]_i_2 + (.I0(in26[10]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[10]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[10]_i_3 + (.I0(in30[10]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[10]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[10]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[10]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[10]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[10]), + .O(\current_mem_addr[10]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[11]_i_1 + (.I0(\current_mem_addr[11]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[11]), + .I3(\current_mem_addr[11]_i_3_n_0 ), + .I4(\current_mem_addr[11]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[11]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_10 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[11]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[11]_i_2 + (.I0(in26[11]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[11]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[11]_i_3 + (.I0(in27[11]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[11]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[11]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[11]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[11]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[11]), + .O(\current_mem_addr[11]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_7 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[11]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_8 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[11]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[11]_i_9 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[11]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[12]_i_1 + (.I0(\current_mem_addr[12]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[12]), + .I3(\current_mem_addr[12]_i_3_n_0 ), + .I4(\current_mem_addr[12]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[12]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair13" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[12]_i_2 + (.I0(in26[12]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[12]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[12]_i_3 + (.I0(in30[12]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[12]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[12]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[12]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[12]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[12]), + .O(\current_mem_addr[12]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[13]_i_1 + (.I0(\current_mem_addr[13]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[13]), + .I3(\current_mem_addr[13]_i_3_n_0 ), + .I4(\current_mem_addr[13]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[13]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[13]_i_2 + (.I0(in26[13]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[13]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[13]_i_3 + (.I0(in30[13]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[13]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[13]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[13]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[13]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[13]), + .O(\current_mem_addr[13]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[14]_i_1 + (.I0(\current_mem_addr[14]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[14]), + .I3(\current_mem_addr[14]_i_4_n_0 ), + .I4(\current_mem_addr[14]_i_5_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[14]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair12" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[14]_i_2 + (.I0(in26[14]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[14]_i_2_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_mem_addr[14]_i_3 + (.I0(\current_mem_addr[14]_i_7_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[11] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[20] ), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\current_mem_addr[14]_i_8_n_0 ), + .O(\current_mem_addr[14]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[14]_i_4 + (.I0(in30[14]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[14]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[14]_i_4_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[14]_i_5 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[14]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[14]), + .O(\current_mem_addr[14]_i_5_n_0 )); + LUT5 #( + .INIT(32'h00000045)) + \current_mem_addr[14]_i_6 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[14]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair26" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[8] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .O(\current_mem_addr[14]_i_7_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair31" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[14]_i_8 + (.I0(\FSM_onehot_state_reg_n_0_[23] ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .O(\current_mem_addr[14]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_1 + (.I0(i_rst_IBUF), + .O(\current_mem_addr[15]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_13 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_13_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_14 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_14_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_15 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_15_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_16 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\FSM_onehot_state_reg_n_0_[4] ), + .I3(\FSM_onehot_state_reg_n_0_[11] ), + .I4(\FSM_onehot_state_reg_n_0_[20] ), + .I5(\FSM_onehot_state_reg_n_0_[23] ), + .O(\current_mem_addr[15]_i_16_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_17 + (.I0(o_mem_addr_OBUF[15]), + .O(\current_mem_addr[15]_i_17_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_18 + (.I0(o_mem_addr_OBUF[14]), + .O(\current_mem_addr[15]_i_18_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_19 + (.I0(o_mem_addr_OBUF[13]), + .O(\current_mem_addr[15]_i_19_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \current_mem_addr[15]_i_2 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\current_mem_addr[15]_i_4_n_0 ), + .I3(\current_mem_addr[15]_i_5_n_0 ), + .I4(in26[15]), + .I5(\current_mem_addr[15]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_2_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_20 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_20_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_21 + (.I0(o_mem_addr_OBUF[12]), + .O(\current_mem_addr[15]_i_21_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_22 + (.I0(o_mem_addr_OBUF[11]), + .O(\current_mem_addr[15]_i_22_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_23 + (.I0(o_mem_addr_OBUF[10]), + .O(\current_mem_addr[15]_i_23_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[15]_i_24 + (.I0(o_mem_addr_OBUF[9]), + .O(\current_mem_addr[15]_i_24_n_0 )); + LUT6 #( + .INIT(64'h0000000011010000)) + \current_mem_addr[15]_i_3 + (.I0(\FSM_onehot_state[1]_i_3_n_0 ), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\current_mem_addr[14]_i_3_n_0 ), + .I5(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[15]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[15]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[15]), + .O(\current_mem_addr[15]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair25" *) + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[15]_i_5 + (.I0(in27[15]), + .I1(\FSM_onehot_state_reg_n_0_[13] ), + .I2(in30[15]), + .I3(\FSM_onehot_state_reg_n_0_[21] ), + .O(\current_mem_addr[15]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair32" *) + LUT3 #( + .INIT(8'h45)) + \current_mem_addr[15]_i_7 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[15]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[15]_i_8 + (.I0(\current_mem_addr[15]_i_16_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[17] ), + .I2(\FSM_onehot_state_reg_n_0_[15] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\current_mem_addr[14]_i_7_n_0 ), + .O(\current_mem_addr[15]_i_8_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[1]_i_1 + (.I0(\current_mem_addr[1]_i_2_n_0 ), + .I1(\current_mem_addr[1]_i_3_n_0 ), + .I2(\current_mem_addr[1]_i_4_n_0 ), + .I3(\current_mem_addr[1]_i_5_n_0 ), + .I4(\current_mem_addr[1]_i_6_n_0 ), + .I5(\current_mem_addr[1]_i_7_n_0 ), + .O(\current_mem_addr[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[1]_i_2 + (.I0(current_task_count[1]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_2_n_0 )); + LUT6 #( + .INIT(64'hA8A8AAA8AAAAAAAA)) + \current_mem_addr[1]_i_3 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[1]_i_4_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\current_mem_addr[14]_i_3_n_0 ), + .O(\current_mem_addr[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[1]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[1]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[1]), + .O(\current_mem_addr[1]_i_4_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[1]_i_5 + (.I0(in30[1]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[1]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[1]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[1]_i_6 + (.I0(o_mem_addr_OBUF[1]), + .I1(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[1]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[1]_i_7 + (.I0(in26[1]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[1]_i_7_n_0 )); + LUT5 #( + .INIT(32'hFFFFEEFE)) + \current_mem_addr[2]_i_1 + (.I0(\current_mem_addr[2]_i_2_n_0 ), + .I1(\current_mem_addr[2]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[2]), + .I3(\current_mem_addr[15]_i_3_n_0 ), + .I4(\current_mem_addr[2]_i_4_n_0 ), + .O(\current_mem_addr[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[2]_i_2 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[2]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[2]), + .O(\current_mem_addr[2]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[2]_i_3 + (.I0(in30[2]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[2]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[2]_i_3_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[2]_i_4 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[2]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[2]), + .O(\current_mem_addr[2]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFF0FFB0)) + \current_mem_addr[3]_i_1 + (.I0(\FSM_onehot_state[1]_i_2_n_0 ), + .I1(\current_mem_addr[3]_i_2_n_0 ), + .I2(o_mem_addr_OBUF[3]), + .I3(\current_mem_addr[3]_i_3_n_0 ), + .I4(\current_mem_addr[3]_i_4_n_0 ), + .I5(\current_mem_addr[3]_i_5_n_0 ), + .O(\current_mem_addr[3]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_10 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[3]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_11 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[3]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_12 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_12_n_0 )); + LUT5 #( + .INIT(32'h0000008A)) + \current_mem_addr[3]_i_2 + (.I0(\current_mem_addr[14]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state[1]_i_4_n_0 ), + .I4(\FSM_onehot_state[1]_i_3_n_0 ), + .O(\current_mem_addr[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[3]_i_3 + (.I0(\current_mem_addr[3]_i_6_n_0 ), + .I1(in23[3]), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[3]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[3]), + .O(\current_mem_addr[3]_i_3_n_0 )); + LUT2 #( + .INIT(4'h8)) + \current_mem_addr[3]_i_4 + (.I0(in23[3]), + .I1(\current_mem_addr[15]_i_8_n_0 ), + .O(\current_mem_addr[3]_i_4_n_0 )); + LUT6 #( + .INIT(64'hF8FFF8FC888888CC)) + \current_mem_addr[3]_i_5 + (.I0(\FSM_onehot_state[15]_i_2_n_0 ), + .I1(current_task_count[3]), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .I4(\FSM_onehot_state[17]_i_2_n_0 ), + .I5(in26[3]), + .O(\current_mem_addr[3]_i_5_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair9" *) + LUT3 #( + .INIT(8'hFE)) + \current_mem_addr[3]_i_6 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[9] ), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .O(\current_mem_addr[3]_i_6_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[3]_i_9 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[3]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFFE)) + \current_mem_addr[4]_i_1 + (.I0(\current_mem_addr[4]_i_2_n_0 ), + .I1(\current_mem_addr[4]_i_3_n_0 ), + .I2(\current_mem_addr[4]_i_4_n_0 ), + .I3(\current_mem_addr[4]_i_5_n_0 ), + .I4(\current_mem_addr[4]_i_6_n_0 ), + .I5(\current_mem_addr[4]_i_7_n_0 ), + .O(\current_mem_addr[4]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_10 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[4]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_11 + (.I0(o_mem_addr_OBUF[3]), + .O(\current_mem_addr[4]_i_11_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_12 + (.I0(o_mem_addr_OBUF[2]), + .O(\current_mem_addr[4]_i_12_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[4]_i_13 + (.I0(o_mem_addr_OBUF[1]), + .O(\current_mem_addr[4]_i_13_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair16" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[4]_i_2 + (.I0(current_task_count[4]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[4]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[4]_i_3 + (.I0(in26[4]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[4]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[4]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[4]), + .O(\current_mem_addr[4]_i_4_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[4]_i_5 + (.I0(in30[4]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(in26[4]), + .I4(\FSM_onehot_state_reg_n_0_[13] ), + .I5(in27[4]), + .O(\current_mem_addr[4]_i_5_n_0 )); + LUT4 #( + .INIT(16'h88A8)) + \current_mem_addr[4]_i_6 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_4_n_0 ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\current_mem_addr[4]_i_6_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair20" *) + LUT4 #( + .INIT(16'hAA8A)) + \current_mem_addr[4]_i_7 + (.I0(o_mem_addr_OBUF[4]), + .I1(\FSM_onehot_state[1]_i_3_n_0 ), + .I2(\current_mem_addr[14]_i_3_n_0 ), + .I3(\FSM_onehot_state[1]_i_2_n_0 ), + .O(\current_mem_addr[4]_i_7_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[5]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\current_mem_addr[5]_i_2_n_0 ), + .I3(\current_mem_addr[5]_i_3_n_0 ), + .I4(\current_mem_addr[5]_i_4_n_0 ), + .I5(\current_mem_addr[5]_i_5_n_0 ), + .O(\current_mem_addr[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair28" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[5]_i_2 + (.I0(in26[5]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[5]_i_3 + (.I0(in26[5]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[5]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[5]), + .O(\current_mem_addr[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[5]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[5]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[5]), + .O(\current_mem_addr[5]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[5]_i_5 + (.I0(current_task_count[5]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[5]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[6]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\current_mem_addr[6]_i_2_n_0 ), + .I3(\current_mem_addr[6]_i_3_n_0 ), + .I4(\current_mem_addr[6]_i_4_n_0 ), + .I5(\current_mem_addr[6]_i_5_n_0 ), + .O(\current_mem_addr[6]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[6]_i_2 + (.I0(in26[6]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[6]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[6]_i_3 + (.I0(in26[6]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[6]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[6]), + .O(\current_mem_addr[6]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[6]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[6]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[6]), + .O(\current_mem_addr[6]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair17" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[6]_i_5 + (.I0(current_task_count[6]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFFFFF4)) + \current_mem_addr[7]_i_1 + (.I0(\current_mem_addr[15]_i_3_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\current_mem_addr[7]_i_2_n_0 ), + .I3(\current_mem_addr[7]_i_3_n_0 ), + .I4(\current_mem_addr[7]_i_4_n_0 ), + .I5(\current_mem_addr[7]_i_5_n_0 ), + .O(\current_mem_addr[7]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[7]_i_10_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_11 + (.I0(o_mem_addr_OBUF[4]), + .O(\current_mem_addr[7]_i_11_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair29" *) + LUT3 #( + .INIT(8'h20)) + \current_mem_addr[7]_i_2 + (.I0(in26[7]), + .I1(\FSM_onehot_state[17]_i_3_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .O(\current_mem_addr[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFFFF888F888F888)) + \current_mem_addr[7]_i_3 + (.I0(in26[7]), + .I1(\FSM_onehot_state_reg_n_0_[12] ), + .I2(\FSM_onehot_state_reg_n_0_[13] ), + .I3(in27[7]), + .I4(\FSM_onehot_state_reg_n_0_[21] ), + .I5(in30[7]), + .O(\current_mem_addr[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[7]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[7]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[7]), + .O(\current_mem_addr[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair18" *) + LUT4 #( + .INIT(16'h888A)) + \current_mem_addr[7]_i_5 + (.I0(current_task_count[7]), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(\FSM_onehot_state[17]_i_3_n_0 ), + .O(\current_mem_addr[7]_i_5_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[7]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[7]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[7]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[8]_i_1 + (.I0(\current_mem_addr[8]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[8]), + .I3(\current_mem_addr[8]_i_3_n_0 ), + .I4(\current_mem_addr[8]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[8]_i_1_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_10 + (.I0(o_mem_addr_OBUF[5]), + .O(\current_mem_addr[8]_i_10_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair15" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[8]_i_2 + (.I0(in26[8]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[8]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[8]_i_3 + (.I0(in30[8]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[8]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[8]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[8]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[8]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[8]), + .O(\current_mem_addr[8]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_7 + (.I0(o_mem_addr_OBUF[8]), + .O(\current_mem_addr[8]_i_7_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_8 + (.I0(o_mem_addr_OBUF[7]), + .O(\current_mem_addr[8]_i_8_n_0 )); + LUT1 #( + .INIT(2'h1)) + \current_mem_addr[8]_i_9 + (.I0(o_mem_addr_OBUF[6]), + .O(\current_mem_addr[8]_i_9_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFBAFFFFFFFA)) + \current_mem_addr[9]_i_1 + (.I0(\current_mem_addr[9]_i_2_n_0 ), + .I1(\current_mem_addr[14]_i_3_n_0 ), + .I2(o_mem_addr_OBUF[9]), + .I3(\current_mem_addr[9]_i_3_n_0 ), + .I4(\current_mem_addr[9]_i_4_n_0 ), + .I5(\current_mem_addr[14]_i_6_n_0 ), + .O(\current_mem_addr[9]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair14" *) + LUT4 #( + .INIT(16'hAA08)) + \current_mem_addr[9]_i_2 + (.I0(in26[9]), + .I1(\FSM_onehot_state[17]_i_2_n_0 ), + .I2(\FSM_onehot_state[17]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(\current_mem_addr[9]_i_2_n_0 )); + LUT4 #( + .INIT(16'hF888)) + \current_mem_addr[9]_i_3 + (.I0(in30[9]), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .I2(in27[9]), + .I3(\FSM_onehot_state_reg_n_0_[13] ), + .O(\current_mem_addr[9]_i_3_n_0 )); + LUT6 #( + .INIT(64'hAAAAAAA800000000)) + \current_mem_addr[9]_i_4 + (.I0(\current_mem_addr[15]_i_8_n_0 ), + .I1(o_mem_addr_OBUF[9]), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[9] ), + .I4(\FSM_onehot_state_reg_n_0_[6] ), + .I5(in23[9]), + .O(\current_mem_addr[9]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[0]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[10] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[10]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[10]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[11] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[11]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[11]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_5 + (.CI(\current_mem_addr_reg[7]_i_6_n_0 ), + .CO({\current_mem_addr_reg[11]_i_5_n_0 ,\current_mem_addr_reg[11]_i_5_n_1 ,\current_mem_addr_reg[11]_i_5_n_2 ,\current_mem_addr_reg[11]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[11:8]), + .S(o_mem_addr_OBUF[11:8])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[11]_i_6 + (.CI(\current_mem_addr_reg[7]_i_7_n_0 ), + .CO({\current_mem_addr_reg[11]_i_6_n_0 ,\current_mem_addr_reg[11]_i_6_n_1 ,\current_mem_addr_reg[11]_i_6_n_2 ,\current_mem_addr_reg[11]_i_6_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[11:8]), + .O(in30[11:8]), + .S({\current_mem_addr[11]_i_7_n_0 ,\current_mem_addr[11]_i_8_n_0 ,\current_mem_addr[11]_i_9_n_0 ,\current_mem_addr[11]_i_10_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[12] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[12]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[12]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[12]_i_5 + (.CI(\current_mem_addr_reg[8]_i_6_n_0 ), + .CO({\current_mem_addr_reg[12]_i_5_n_0 ,\current_mem_addr_reg[12]_i_5_n_1 ,\current_mem_addr_reg[12]_i_5_n_2 ,\current_mem_addr_reg[12]_i_5_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[12:9]), + .S(o_mem_addr_OBUF[12:9])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[13] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[13]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[13]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[14] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[14]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[14]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[15] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[15]_i_2_n_0 ), + .Q(o_mem_addr_OBUF[15]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_10 + (.CI(\current_mem_addr_reg[11]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_10_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_10_n_1 ,\current_mem_addr_reg[15]_i_10_n_2 ,\current_mem_addr_reg[15]_i_10_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[15:12]), + .S(o_mem_addr_OBUF[15:12])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_11 + (.CI(\current_mem_addr_reg[11]_i_6_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_11_CO_UNCONNECTED [3],\current_mem_addr_reg[15]_i_11_n_1 ,\current_mem_addr_reg[15]_i_11_n_2 ,\current_mem_addr_reg[15]_i_11_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,o_mem_addr_OBUF[14:12]}), + .O(in30[15:12]), + .S({\current_mem_addr[15]_i_17_n_0 ,\current_mem_addr[15]_i_18_n_0 ,\current_mem_addr[15]_i_19_n_0 ,\current_mem_addr[15]_i_20_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_12 + (.CI(\current_mem_addr_reg[8]_i_5_n_0 ), + .CO({\current_mem_addr_reg[15]_i_12_n_0 ,\current_mem_addr_reg[15]_i_12_n_1 ,\current_mem_addr_reg[15]_i_12_n_2 ,\current_mem_addr_reg[15]_i_12_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[12:9]), + .O(in26[12:9]), + .S({\current_mem_addr[15]_i_21_n_0 ,\current_mem_addr[15]_i_22_n_0 ,\current_mem_addr[15]_i_23_n_0 ,\current_mem_addr[15]_i_24_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_6 + (.CI(\current_mem_addr_reg[15]_i_12_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_6_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_6_n_2 ,\current_mem_addr_reg[15]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[14:13]}), + .O({\NLW_current_mem_addr_reg[15]_i_6_O_UNCONNECTED [3],in26[15:13]}), + .S({1'b0,\current_mem_addr[15]_i_13_n_0 ,\current_mem_addr[15]_i_14_n_0 ,\current_mem_addr[15]_i_15_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[15]_i_9 + (.CI(\current_mem_addr_reg[12]_i_5_n_0 ), + .CO({\NLW_current_mem_addr_reg[15]_i_9_CO_UNCONNECTED [3:2],\current_mem_addr_reg[15]_i_9_n_2 ,\current_mem_addr_reg[15]_i_9_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_current_mem_addr_reg[15]_i_9_O_UNCONNECTED [3],in23[15:13]}), + .S({1'b0,o_mem_addr_OBUF[15:13]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[1]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[2]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[3]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[3]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_7 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_7_n_0 ,\current_mem_addr_reg[3]_i_7_n_1 ,\current_mem_addr_reg[3]_i_7_n_2 ,\current_mem_addr_reg[3]_i_7_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,o_mem_addr_OBUF[1],1'b0}), + .O({in27[3:1],in30[0]}), + .S({o_mem_addr_OBUF[3:2],\current_mem_addr[3]_i_9_n_0 ,o_mem_addr_OBUF[0]})); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[3]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[3]_i_8_n_0 ,\current_mem_addr_reg[3]_i_8_n_1 ,\current_mem_addr_reg[3]_i_8_n_2 ,\current_mem_addr_reg[3]_i_8_n_3 }), + .CYINIT(1'b0), + .DI({o_mem_addr_OBUF[3:1],1'b0}), + .O({in30[3:1],\NLW_current_mem_addr_reg[3]_i_8_O_UNCONNECTED [0]}), + .S({\current_mem_addr[3]_i_10_n_0 ,\current_mem_addr[3]_i_11_n_0 ,\current_mem_addr[3]_i_12_n_0 ,o_mem_addr_OBUF[0]})); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[4]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[4]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_8 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_8_n_0 ,\current_mem_addr_reg[4]_i_8_n_1 ,\current_mem_addr_reg[4]_i_8_n_2 ,\current_mem_addr_reg[4]_i_8_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI(o_mem_addr_OBUF[4:1]), + .O(in26[4:1]), + .S({\current_mem_addr[4]_i_10_n_0 ,\current_mem_addr[4]_i_11_n_0 ,\current_mem_addr[4]_i_12_n_0 ,\current_mem_addr[4]_i_13_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[4]_i_9 + (.CI(1'b0), + .CO({\current_mem_addr_reg[4]_i_9_n_0 ,\current_mem_addr_reg[4]_i_9_n_1 ,\current_mem_addr_reg[4]_i_9_n_2 ,\current_mem_addr_reg[4]_i_9_n_3 }), + .CYINIT(o_mem_addr_OBUF[0]), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[4:1]), + .S(o_mem_addr_OBUF[4:1])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[5]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[6]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[7]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[7]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_6 + (.CI(\current_mem_addr_reg[3]_i_7_n_0 ), + .CO({\current_mem_addr_reg[7]_i_6_n_0 ,\current_mem_addr_reg[7]_i_6_n_1 ,\current_mem_addr_reg[7]_i_6_n_2 ,\current_mem_addr_reg[7]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in27[7:4]), + .S(o_mem_addr_OBUF[7:4])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[7]_i_7 + (.CI(\current_mem_addr_reg[3]_i_8_n_0 ), + .CO({\current_mem_addr_reg[7]_i_7_n_0 ,\current_mem_addr_reg[7]_i_7_n_1 ,\current_mem_addr_reg[7]_i_7_n_2 ,\current_mem_addr_reg[7]_i_7_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[7:4]), + .O(in30[7:4]), + .S({\current_mem_addr[7]_i_8_n_0 ,\current_mem_addr[7]_i_9_n_0 ,\current_mem_addr[7]_i_10_n_0 ,\current_mem_addr[7]_i_11_n_0 })); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[8] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[8]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[8]), + .R(1'b0)); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_5 + (.CI(\current_mem_addr_reg[4]_i_8_n_0 ), + .CO({\current_mem_addr_reg[8]_i_5_n_0 ,\current_mem_addr_reg[8]_i_5_n_1 ,\current_mem_addr_reg[8]_i_5_n_2 ,\current_mem_addr_reg[8]_i_5_n_3 }), + .CYINIT(1'b0), + .DI(o_mem_addr_OBUF[8:5]), + .O(in26[8:5]), + .S({\current_mem_addr[8]_i_7_n_0 ,\current_mem_addr[8]_i_8_n_0 ,\current_mem_addr[8]_i_9_n_0 ,\current_mem_addr[8]_i_10_n_0 })); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \current_mem_addr_reg[8]_i_6 + (.CI(\current_mem_addr_reg[4]_i_9_n_0 ), + .CO({\current_mem_addr_reg[8]_i_6_n_0 ,\current_mem_addr_reg[8]_i_6_n_1 ,\current_mem_addr_reg[8]_i_6_n_2 ,\current_mem_addr_reg[8]_i_6_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O(in23[8:5]), + .S(o_mem_addr_OBUF[8:5])); + FDRE #( + .INIT(1'b0)) + \current_mem_addr_reg[9] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\current_mem_addr[9]_i_1_n_0 ), + .Q(o_mem_addr_OBUF[9]), + .R(1'b0)); + LUT5 #( + .INIT(32'h000000EA)) + \current_popped_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[2] ), + .I2(i_start_IBUF), + .I3(i_rst_IBUF), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h55555540)) + \current_popped_id[5]_i_2 + (.I0(i_rst_IBUF), + .I1(i_start_IBUF), + .I2(\FSM_onehot_state_reg_n_0_[2] ), + .I3(\FSM_onehot_state_reg_n_0_[0] ), + .I4(\FSM_onehot_state_reg_n_0_[9] ), + .O(\current_popped_id[5]_i_2_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[2]), + .Q(current_popped_id[0]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[3]), + .Q(current_popped_id[1]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[4]), + .Q(current_popped_id[2]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[5]), + .Q(current_popped_id[3]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[6]), + .Q(current_popped_id[4]), + .R(\current_popped_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_popped_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_popped_id[5]_i_2_n_0 ), + .D(i_mem_data_IBUF[7]), + .Q(current_popped_id[5]), + .R(\current_popped_id[5]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT3 #( + .INIT(8'h54)) + \current_task_count[0]_i_1 + (.I0(current_task_count[0]), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(\FSM_onehot_state_reg_n_0_[19] ), + .O(\current_task_count[0]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT4 #( + .INIT(16'hEB28)) + \current_task_count[1]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[1]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair3" *) + LUT5 #( + .INIT(32'hECCB2888)) + \current_task_count[2]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCCCCCB28888888)) + \current_task_count[3]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[3]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[2]), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT4 #( + .INIT(16'hBEAA)) + \current_task_count[4]_i_1 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[4]_i_1_n_0 )); + LUT6 #( + .INIT(64'h2AAAAAAA80000000)) + \current_task_count[4]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[4]), + .O(\current_task_count[4]_i_2_n_0 )); + LUT6 #( + .INIT(64'hF44FF4F444444444)) + \current_task_count[5]_i_1 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[5]), + .I3(current_task_count[4]), + .I4(\current_task_count[5]_i_3_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[5]_i_1_n_0 )); + LUT6 #( + .INIT(64'h9555555555555555)) + \current_task_count[5]_i_2 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[2]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[3]), + .O(\current_task_count[5]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT4 #( + .INIT(16'h0001)) + \current_task_count[5]_i_3 + (.I0(current_task_count[3]), + .I1(current_task_count[0]), + .I2(current_task_count[1]), + .I3(current_task_count[2]), + .O(\current_task_count[5]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT5 #( + .INIT(32'h8FF48484)) + \current_task_count[6]_i_1 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[6]), + .I3(\current_task_count[7]_i_4_n_0 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[6]_i_1_n_0 )); + LUT6 #( + .INIT(64'h5555555555555444)) + \current_task_count[7]_i_1 + (.I0(i_rst_IBUF), + .I1(\FSM_onehot_state_reg_n_0_[22] ), + .I2(\FSM_onehot_state_reg_n_0_[10] ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[19] ), + .I5(\FSM_onehot_state_reg_n_0_[0] ), + .O(\current_task_count[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'hF4CFF4F084C084C0)) + \current_task_count[7]_i_2 + (.I0(\current_task_count[7]_i_3_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(current_task_count[7]), + .I3(current_task_count[6]), + .I4(\current_task_count[7]_i_4_n_0 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\current_task_count[7]_i_2_n_0 )); + LUT6 #( + .INIT(64'h7FFFFFFFFFFFFFFF)) + \current_task_count[7]_i_3 + (.I0(current_task_count[4]), + .I1(current_task_count[2]), + .I2(current_task_count[0]), + .I3(current_task_count[1]), + .I4(current_task_count[3]), + .I5(current_task_count[5]), + .O(\current_task_count[7]_i_3_n_0 )); + LUT6 #( + .INIT(64'h0000000000000001)) + \current_task_count[7]_i_4 + (.I0(current_task_count[2]), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[3]), + .I4(current_task_count[5]), + .I5(current_task_count[4]), + .O(\current_task_count[7]_i_4_n_0 )); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[0]_i_1_n_0 ), + .Q(current_task_count[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[1]_i_1_n_0 ), + .Q(current_task_count[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[2]_i_1_n_0 ), + .Q(current_task_count[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[3]_i_1_n_0 ), + .Q(current_task_count[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[4]_i_1_n_0 ), + .Q(current_task_count[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[5]_i_1_n_0 ), + .Q(current_task_count[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[6]_i_1_n_0 ), + .Q(current_task_count[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \current_task_count_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_task_count[7]_i_1_n_0 ), + .D(\current_task_count[7]_i_2_n_0 ), + .Q(current_task_count[7]), + .R(1'b0)); + BUFG i_clk_IBUF_BUFG_inst + (.I(i_clk_IBUF), + .O(i_clk_IBUF_BUFG)); + IBUF i_clk_IBUF_inst + (.I(i_clk), + .O(i_clk_IBUF)); + IBUF \i_mem_data_IBUF[0]_inst + (.I(i_mem_data[0]), + .O(i_mem_data_IBUF[0])); + IBUF \i_mem_data_IBUF[1]_inst + (.I(i_mem_data[1]), + .O(i_mem_data_IBUF[1])); + IBUF \i_mem_data_IBUF[2]_inst + (.I(i_mem_data[2]), + .O(i_mem_data_IBUF[2])); + IBUF \i_mem_data_IBUF[3]_inst + (.I(i_mem_data[3]), + .O(i_mem_data_IBUF[3])); + IBUF \i_mem_data_IBUF[4]_inst + (.I(i_mem_data[4]), + .O(i_mem_data_IBUF[4])); + IBUF \i_mem_data_IBUF[5]_inst + (.I(i_mem_data[5]), + .O(i_mem_data_IBUF[5])); + IBUF \i_mem_data_IBUF[6]_inst + (.I(i_mem_data[6]), + .O(i_mem_data_IBUF[6])); + IBUF \i_mem_data_IBUF[7]_inst + (.I(i_mem_data[7]), + .O(i_mem_data_IBUF[7])); + IBUF \i_op_IBUF[0]_inst + (.I(i_op[0]), + .O(i_op_IBUF[0])); + IBUF \i_op_IBUF[1]_inst + (.I(i_op[1]), + .O(i_op_IBUF[1])); + IBUF i_rst_IBUF_inst + (.I(i_rst), + .O(i_rst_IBUF)); + IBUF i_start_IBUF_inst + (.I(i_start), + .O(i_start_IBUF)); + IBUF \i_task_id_IBUF[0]_inst + (.I(i_task_id[0]), + .O(i_task_id_IBUF[0])); + IBUF \i_task_id_IBUF[1]_inst + (.I(i_task_id[1]), + .O(i_task_id_IBUF[1])); + IBUF \i_task_id_IBUF[2]_inst + (.I(i_task_id[2]), + .O(i_task_id_IBUF[2])); + IBUF \i_task_id_IBUF[3]_inst + (.I(i_task_id[3]), + .O(i_task_id_IBUF[3])); + IBUF \i_task_id_IBUF[4]_inst + (.I(i_task_id[4]), + .O(i_task_id_IBUF[4])); + IBUF \i_task_id_IBUF[5]_inst + (.I(i_task_id[5]), + .O(i_task_id_IBUF[5])); + IBUF \i_task_priority_IBUF[0]_inst + (.I(i_task_priority[0]), + .O(i_task_priority_IBUF[0])); + IBUF \i_task_priority_IBUF[1]_inst + (.I(i_task_priority[1]), + .O(i_task_priority_IBUF[1])); + OBUF o_done_OBUF_inst + (.I(o_done_OBUF), + .O(o_done)); + (* SOFT_HLUTNM = "soft_lutpair24" *) + LUT3 #( + .INIT(8'hEA)) + o_done_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[1] ), + .I2(i_start_IBUF), + .O(ctrl_done)); + FDPE #( + .INIT(1'b1)) + o_done_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .D(ctrl_done), + .PRE(i_rst_IBUF), + .Q(o_done_OBUF)); + OBUF \o_mem_addr_OBUF[0]_inst + (.I(o_mem_addr_OBUF[0]), + .O(o_mem_addr[0])); + OBUF \o_mem_addr_OBUF[10]_inst + (.I(o_mem_addr_OBUF[10]), + .O(o_mem_addr[10])); + OBUF \o_mem_addr_OBUF[11]_inst + (.I(o_mem_addr_OBUF[11]), + .O(o_mem_addr[11])); + OBUF \o_mem_addr_OBUF[12]_inst + (.I(o_mem_addr_OBUF[12]), + .O(o_mem_addr[12])); + OBUF \o_mem_addr_OBUF[13]_inst + (.I(o_mem_addr_OBUF[13]), + .O(o_mem_addr[13])); + OBUF \o_mem_addr_OBUF[14]_inst + (.I(o_mem_addr_OBUF[14]), + .O(o_mem_addr[14])); + OBUF \o_mem_addr_OBUF[15]_inst + (.I(o_mem_addr_OBUF[15]), + .O(o_mem_addr[15])); + OBUF \o_mem_addr_OBUF[1]_inst + (.I(o_mem_addr_OBUF[1]), + .O(o_mem_addr[1])); + OBUF \o_mem_addr_OBUF[2]_inst + (.I(o_mem_addr_OBUF[2]), + .O(o_mem_addr[2])); + OBUF \o_mem_addr_OBUF[3]_inst + (.I(o_mem_addr_OBUF[3]), + .O(o_mem_addr[3])); + OBUF \o_mem_addr_OBUF[4]_inst + (.I(o_mem_addr_OBUF[4]), + .O(o_mem_addr[4])); + OBUF \o_mem_addr_OBUF[5]_inst + (.I(o_mem_addr_OBUF[5]), + .O(o_mem_addr[5])); + OBUF \o_mem_addr_OBUF[6]_inst + (.I(o_mem_addr_OBUF[6]), + .O(o_mem_addr[6])); + OBUF \o_mem_addr_OBUF[7]_inst + (.I(o_mem_addr_OBUF[7]), + .O(o_mem_addr[7])); + OBUF \o_mem_addr_OBUF[8]_inst + (.I(o_mem_addr_OBUF[8]), + .O(o_mem_addr[8])); + OBUF \o_mem_addr_OBUF[9]_inst + (.I(o_mem_addr_OBUF[9]), + .O(o_mem_addr[9])); + LUT6 #( + .INIT(64'hFFE0FFE0FFFFFFE0)) + \o_mem_data[0]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(\FSM_onehot_state[21]_i_1_n_0 ), + .I2(i_mem_data_IBUF[0]), + .I3(\o_mem_data[0]_i_2_n_0 ), + .I4(i_task_priority_IBUF[0]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[0]_i_1_n_0 )); + LUT6 #( + .INIT(64'h0E0E0E0E0AFF0A0A)) + \o_mem_data[0]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\FSM_onehot_state_reg_n_0_[10] ), + .I2(current_task_count[0]), + .I3(i_mem_data_IBUF[0]), + .I4(\FSM_onehot_state_reg_n_0_[5] ), + .I5(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[0]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFBAFFBAFFFFFFBA)) + \o_mem_data[1]_i_1 + (.I0(\o_mem_data[1]_i_2_n_0 ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state[11]_i_1_n_0 ), + .I3(\o_mem_data[1]_i_4_n_0 ), + .I4(i_mem_data_IBUF[1]), + .I5(\o_mem_data[6]_i_3_n_0 ), + .O(\o_mem_data[1]_i_1_n_0 )); + LUT5 #( + .INIT(32'hAAAA8880)) + \o_mem_data[1]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[18] ), + .I1(i_mem_data_IBUF[1]), + .I2(\FSM_onehot_state[17]_i_2_n_0 ), + .I3(o_mem_addr_OBUF[0]), + .I4(i_task_priority_IBUF[1]), + .O(\o_mem_data[1]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair35" *) + LUT2 #( + .INIT(4'h6)) + \o_mem_data[1]_i_3 + (.I0(current_task_count[0]), + .I1(current_task_count[1]), + .O(\o_mem_data[1]_i_3_n_0 )); + LUT6 #( + .INIT(64'h88888F8888888888)) + \o_mem_data[1]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\o_mem_data[1]_i_3_n_0 ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(i_mem_data_IBUF[1]), + .I5(i_mem_data_IBUF[0]), + .O(\o_mem_data[1]_i_4_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[2]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[2]), + .I2(\o_mem_data[2]_i_2_n_0 ), + .I3(i_task_id_IBUF[0]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[2]_i_1_n_0 )); + LUT6 #( + .INIT(64'hECCB288828882888)) + \o_mem_data[2]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[2]), + .I2(current_task_count[1]), + .I3(current_task_count[0]), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[2]_i_2_n_0 )); + LUT6 #( + .INIT(64'hFFF4FFF4FFFFFFF4)) + \o_mem_data[3]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[3]), + .I2(\o_mem_data[3]_i_2_n_0 ), + .I3(\o_mem_data[3]_i_3_n_0 ), + .I4(i_task_id_IBUF[1]), + .I5(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[3]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair6" *) + LUT5 #( + .INIT(32'h2AAA8000)) + \o_mem_data[3]_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[1]), + .I2(current_task_count[0]), + .I3(current_task_count[2]), + .I4(current_task_count[3]), + .O(\o_mem_data[3]_i_2_n_0 )); + LUT6 #( + .INIT(64'h8888888000000008)) + \o_mem_data[3]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(current_task_count[2]), + .I3(current_task_count[1]), + .I4(current_task_count[0]), + .I5(current_task_count[3]), + .O(\o_mem_data[3]_i_3_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[4]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[4]), + .I2(\o_mem_data[4]_i_2_n_0 ), + .I3(i_task_id_IBUF[2]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[4]_i_1_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair2" *) + LUT5 #( + .INIT(32'hBEAAAAAA)) + \o_mem_data[4]_i_2 + (.I0(\current_task_count[4]_i_2_n_0 ), + .I1(current_task_count[4]), + .I2(\current_task_count[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[4]_i_2_n_0 )); + LUT5 #( + .INIT(32'hF4F4FFF4)) + \o_mem_data[5]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[5]), + .I2(\o_mem_data[5]_i_2_n_0 ), + .I3(i_task_id_IBUF[3]), + .I4(\FSM_onehot_state[19]_i_2_n_0 ), + .O(\o_mem_data[5]_i_1_n_0 )); + LUT5 #( + .INIT(32'h4F444444)) + \o_mem_data[5]_i_2 + (.I0(\current_task_count[5]_i_2_n_0 ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\o_mem_data[5]_i_3_n_0 ), + .I3(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I4(\FSM_onehot_state_reg_n_0_[10] ), + .O(\o_mem_data[5]_i_2_n_0 )); + LUT6 #( + .INIT(64'h5555555555555556)) + \o_mem_data[5]_i_3 + (.I0(current_task_count[5]), + .I1(current_task_count[4]), + .I2(current_task_count[3]), + .I3(current_task_count[0]), + .I4(current_task_count[1]), + .I5(current_task_count[2]), + .O(\o_mem_data[5]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[6]_i_1 + (.I0(\o_mem_data[6]_i_2_n_0 ), + .I1(\FSM_onehot_state[11]_i_1_n_0 ), + .I2(\o_mem_data[6]_i_3_n_0 ), + .I3(i_mem_data_IBUF[6]), + .I4(\o_mem_data[6]_i_4_n_0 ), + .I5(\o_mem_data[6]_i_5_n_0 ), + .O(\o_mem_data[6]_i_1_n_0 )); + LUT4 #( + .INIT(16'h5655)) + \o_mem_data[6]_i_2 + (.I0(current_task_count[6]), + .I1(current_task_count[4]), + .I2(current_task_count[5]), + .I3(\current_task_count[5]_i_3_n_0 ), + .O(\o_mem_data[6]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT5 #( + .INIT(32'h55554055)) + \o_mem_data[6]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[12] ), + .I1(i_mem_data_IBUF[0]), + .I2(i_mem_data_IBUF[1]), + .I3(\FSM_onehot_state_reg_n_0_[5] ), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .O(\o_mem_data[6]_i_3_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair4" *) + LUT3 #( + .INIT(8'h82)) + \o_mem_data[6]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(\current_task_count[7]_i_3_n_0 ), + .I2(current_task_count[6]), + .O(\o_mem_data[6]_i_4_n_0 )); + LUT4 #( + .INIT(16'hE200)) + \o_mem_data[6]_i_5 + (.I0(i_task_id_IBUF[4]), + .I1(\FSM_onehot_state[21]_i_2_n_0 ), + .I2(i_mem_data_IBUF[6]), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(\o_mem_data[6]_i_5_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFFFFFF4F44)) + \o_mem_data[7]_i_1 + (.I0(\o_mem_data[7]_i_2_n_0 ), + .I1(i_mem_data_IBUF[7]), + .I2(\FSM_onehot_state[19]_i_2_n_0 ), + .I3(i_task_id_IBUF[5]), + .I4(\o_mem_data[7]_i_3_n_0 ), + .I5(\o_mem_data[7]_i_4_n_0 ), + .O(\o_mem_data[7]_i_1_n_0 )); + LUT6 #( + .INIT(64'h000000FB00FB00FB)) + \o_mem_data[7]_i_2 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(\o_mem_data[7]_i_5_n_0 ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .I4(\FSM_onehot_state_reg_n_0_[18] ), + .I5(\FSM_onehot_state[21]_i_2_n_0 ), + .O(\o_mem_data[7]_i_2_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair1" *) + LUT5 #( + .INIT(32'h88080080)) + \o_mem_data[7]_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[10] ), + .I1(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I2(\current_task_count[7]_i_4_n_0 ), + .I3(current_task_count[6]), + .I4(current_task_count[7]), + .O(\o_mem_data[7]_i_3_n_0 )); + LUT4 #( + .INIT(16'hA208)) + \o_mem_data[7]_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[19] ), + .I1(current_task_count[6]), + .I2(\current_task_count[7]_i_3_n_0 ), + .I3(current_task_count[7]), + .O(\o_mem_data[7]_i_4_n_0 )); + (* SOFT_HLUTNM = "soft_lutpair19" *) + LUT2 #( + .INIT(4'h8)) + \o_mem_data[7]_i_5 + (.I0(i_mem_data_IBUF[0]), + .I1(i_mem_data_IBUF[1]), + .O(\o_mem_data[7]_i_5_n_0 )); + OBUF \o_mem_data_OBUF[0]_inst + (.I(o_mem_data_OBUF[0]), + .O(o_mem_data[0])); + OBUF \o_mem_data_OBUF[1]_inst + (.I(o_mem_data_OBUF[1]), + .O(o_mem_data[1])); + OBUF \o_mem_data_OBUF[2]_inst + (.I(o_mem_data_OBUF[2]), + .O(o_mem_data[2])); + OBUF \o_mem_data_OBUF[3]_inst + (.I(o_mem_data_OBUF[3]), + .O(o_mem_data[3])); + OBUF \o_mem_data_OBUF[4]_inst + (.I(o_mem_data_OBUF[4]), + .O(o_mem_data[4])); + OBUF \o_mem_data_OBUF[5]_inst + (.I(o_mem_data_OBUF[5]), + .O(o_mem_data[5])); + OBUF \o_mem_data_OBUF[6]_inst + (.I(o_mem_data_OBUF[6]), + .O(o_mem_data[6])); + OBUF \o_mem_data_OBUF[7]_inst + (.I(o_mem_data_OBUF[7]), + .O(o_mem_data[7])); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[0]_i_1_n_0 ), + .Q(o_mem_data_OBUF[0]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[1]_i_1_n_0 ), + .Q(o_mem_data_OBUF[1]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[2]_i_1_n_0 ), + .Q(o_mem_data_OBUF[2]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[3]_i_1_n_0 ), + .Q(o_mem_data_OBUF[3]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[4]_i_1_n_0 ), + .Q(o_mem_data_OBUF[4]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[5]_i_1_n_0 ), + .Q(o_mem_data_OBUF[5]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[6] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[6]_i_1_n_0 ), + .Q(o_mem_data_OBUF[6]), + .R(1'b0)); + FDRE #( + .INIT(1'b0)) + \o_mem_data_reg[7] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(\o_mem_data[7]_i_1_n_0 ), + .Q(o_mem_data_OBUF[7]), + .R(1'b0)); + OBUF o_mem_en_OBUF_inst + (.I(o_mem_en_OBUF), + .O(o_mem_en)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFFFFFF)) + o_mem_en_i_1 + (.I0(\FSM_onehot_state[8]_i_1_n_0 ), + .I1(\FSM_onehot_state[15]_i_2_n_0 ), + .I2(o_mem_we_i_3_n_0), + .I3(o_mem_en_i_2_n_0), + .I4(o_mem_en_i_3_n_0), + .I5(\FSM_onehot_state[17]_i_3_n_0 ), + .O(ctrl_mem_en)); + (* SOFT_HLUTNM = "soft_lutpair11" *) + LUT4 #( + .INIT(16'hFFFE)) + o_mem_en_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg_n_0_[12] ), + .I3(\FSM_onehot_state_reg_n_0_[18] ), + .O(o_mem_en_i_2_n_0)); + LUT6 #( + .INIT(64'hFFFFFFFEFFFEFFFE)) + o_mem_en_i_3 + (.I0(\FSM_onehot_state_reg_n_0_[6] ), + .I1(\FSM_onehot_state_reg_n_0_[3] ), + .I2(\FSM_onehot_state[10]_i_1_n_0 ), + .I3(o_mem_en_i_4_n_0), + .I4(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I5(\FSM_onehot_state_reg_n_0_[10] ), + .O(o_mem_en_i_3_n_0)); + (* SOFT_HLUTNM = "soft_lutpair27" *) + LUT2 #( + .INIT(4'hE)) + o_mem_en_i_4 + (.I0(\FSM_onehot_state_reg_n_0_[22] ), + .I1(\FSM_onehot_state_reg_n_0_[21] ), + .O(o_mem_en_i_4_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_en_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_en), + .Q(o_mem_en_OBUF)); + OBUF o_mem_we_OBUF_inst + (.I(o_mem_we_OBUF), + .O(o_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair10" *) + LUT4 #( + .INIT(16'hFFFD)) + o_mem_we_i_1 + (.I0(o_mem_we_i_2_n_0), + .I1(o_mem_we_i_3_n_0), + .I2(\FSM_onehot_state_reg_n_0_[18] ), + .I3(\FSM_onehot_state_reg_n_0_[12] ), + .O(ctrl_mem_we)); + (* SOFT_HLUTNM = "soft_lutpair0" *) + LUT5 #( + .INIT(32'h00000111)) + o_mem_we_i_2 + (.I0(\FSM_onehot_state_reg_n_0_[0] ), + .I1(\FSM_onehot_state_reg_n_0_[19] ), + .I2(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I3(\FSM_onehot_state_reg_n_0_[10] ), + .I4(\FSM_onehot_state_reg_n_0_[22] ), + .O(o_mem_we_i_2_n_0)); + (* SOFT_HLUTNM = "soft_lutpair8" *) + LUT4 #( + .INIT(16'h0444)) + o_mem_we_i_3 + (.I0(\FSM_onehot_state_reg[12]_i_2_n_2 ), + .I1(\FSM_onehot_state_reg_n_0_[5] ), + .I2(i_mem_data_IBUF[1]), + .I3(i_mem_data_IBUF[0]), + .O(o_mem_we_i_3_n_0)); + FDCE #( + .INIT(1'b0)) + o_mem_we_reg + (.C(i_clk_IBUF_BUFG), + .CE(1'b1), + .CLR(i_rst_IBUF), + .D(ctrl_mem_we), + .Q(o_mem_we_OBUF)); + LUT3 #( + .INIT(8'h07)) + \o_task_id[5]_i_1 + (.I0(\FSM_onehot_state_reg_n_0_[1] ), + .I1(i_start_IBUF), + .I2(i_rst_IBUF), + .O(\o_task_id[5]_i_1_n_0 )); + OBUF \o_task_id_OBUF[0]_inst + (.I(o_task_id_OBUF[0]), + .O(o_task_id[0])); + OBUF \o_task_id_OBUF[1]_inst + (.I(o_task_id_OBUF[1]), + .O(o_task_id[1])); + OBUF \o_task_id_OBUF[2]_inst + (.I(o_task_id_OBUF[2]), + .O(o_task_id[2])); + OBUF \o_task_id_OBUF[3]_inst + (.I(o_task_id_OBUF[3]), + .O(o_task_id[3])); + OBUF \o_task_id_OBUF[4]_inst + (.I(o_task_id_OBUF[4]), + .O(o_task_id[4])); + OBUF \o_task_id_OBUF[5]_inst + (.I(o_task_id_OBUF[5]), + .O(o_task_id[5])); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[0] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[0]), + .Q(o_task_id_OBUF[0]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[1] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[1]), + .Q(o_task_id_OBUF[1]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[2] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[2]), + .Q(o_task_id_OBUF[2]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[3] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[3]), + .Q(o_task_id_OBUF[3]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[4] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[4]), + .Q(o_task_id_OBUF[4]), + .R(\o_task_id[5]_i_1_n_0 )); + FDRE #( + .INIT(1'b0)) + \o_task_id_reg[5] + (.C(i_clk_IBUF_BUFG), + .CE(\current_mem_addr[15]_i_1_n_0 ), + .D(current_popped_id[5]), + .Q(o_task_id_OBUF[5]), + .R(\o_task_id[5]_i_1_n_0 )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.wdb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_timing_func_synth.wdb new file mode 100644 index 0000000000000000000000000000000000000000..8ce283463b29faac7f0c0d08f25fb667f416019e GIT binary patch literal 68544 zcmeI5d3;<|`M7VPg#rRaKx2y%DAEX}+1hl<)}%?g(6kL%+Mx^6GzrbL*+|lM3Y3OD ztd`ZVS4FLeS^;%Lg%P)+s8v~_B8<326b!3_3;n(CIq#jmd2`=;#4r8l_sRM6zo`dsqLN=Xp)gx~yW( zw91Xm?LC6behP>_A2grZ>GMSk-~&dv@G+vw+_?*?;Dbl-$)g>UX255Q4gqe*ex7#{ zM3~z4){eFDMsFP1*eg!9z$^5Ydr`9$=L_xIyBix?8@gg~m++wE$`%)a6i@L9K#1AL=Pn%&Zo&p6dT^UFAYoxIl}`>gsFCs?2m? zlLvD)t5XKIG1=^-V@oT`>z33Qa15*#$YxFlP=sKLzgoF)4+mJVxUOAY_E zVM}MX=?d?(cYA}l-cUAld!=&@H#ggW{m~t#;qC6`MwroOo*IPPZSi)`OMUs78%sQ| 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a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log new file mode 100644 index 0000000..b0f8eb8 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.log @@ -0,0 +1,152 @@ +Time resolution is 1 ps +Note: === GRUPPO 0: Reset === +Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.0 OK: reset base +Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 0.1 OK: reset asincrono durante operazione +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 1: Inserimento === +Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.0 OK: insert in lista vuota +Time: 3670100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.1 OK: insert con priorità massima in testa +Time: 6010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.2 OK: insert con priorità minima in fondo +Time: 8230100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali +Time: 10450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo +Time: 12950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 1.5 OK: insert con ID duplicato ignorato +Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 2: Rimozione === +Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0 +Time: 16990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto +Time: 18930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato +Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 3: Decremento priorità === +Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.0 OK: decremento su lista vuota +Time: 23130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.1 OK: saturazione a priorità 3 +Time: 25350100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica +Time: 27870100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino) +Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 4: Svuota lista === +Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.0 OK: svuota lista popolata +Time: 33050100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.1 OK: svuota lista già vuota +Time: 34730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0 +Time: 36690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto +Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 5: Sequenze composite === +Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto +Time: 41490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 5.1 OK: ordinamento completo con priorità miste +Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 6: Rimozione multipla e ordinamento === +Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota +Time: 48310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1 +Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 7: Decremento ripetuto === +Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3 +Time: 53430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente +Time: 57010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.1 OK: decremento su lista con un solo task +Time: 59330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota +Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 8: Insert dopo rimozione e casi limite === +Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto +Time: 64950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato +Time: 67830100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato +Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 9: o_task_id per OP diverso da 01 === +Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1 +Time: 72490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1 +Time: 74450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1 +Time: 76330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1 +Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 10: Protocollo, reset avanzato, stress === +Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset +Time: 79750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert) +Time: 92030100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato +Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 11: Insert con ID=0 === +Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato +Time: 96290100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato +Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 12: Capacita' massima 63 task === +Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata +Time: 231450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati +Time: 235970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 12.2 OK: drain di 63 task nell'ordine atteso +Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 13: Stale memory e duplicati ai bordi === +Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.0 OK: re-insert di ID appena rimosso +Time: 365710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.1 OK: duplicato in prima posizione ignorato +Time: 368130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.2 OK: duplicato in ultima posizione ignorato +Time: 368250100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 13.3 OK: re-insert stesso ID dopo clear +Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 14: Reset asincrono avanzato === +Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.0 OK: reset a meta' shift di OP=01 +Time: 373150100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.1 OK: reset durante la scrittura del count +Time: 375930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.2 OK: reset durante OP=00 +Time: 378470100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.3 OK: reset mentre DONE=1 +Time: 380550100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 14.4 OK: reset corto non allineato +Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: === GRUPPO 15: START lento dopo DONE=1 === +Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.0 OK: nessun doppio pop con START lento +Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.1 OK: nessun doppio age con START lento +Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Note: Test 15.2 OK: insert con START tenuto 2 cicli extra +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: ====================================== + Tutti i test edge case sono PASSATI +====================================== +Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616 +Note: === GRUPPO 0: Reset === +Time: 389890 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +Failure: FAIL [0.0 reset-addr0] addr=0 expected=0x0 actual=0x1 +Time: 390040 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd +$finish called at time : 390040 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 420 +INFO: xsimkernel Simulation Memory Usage: 294496 KB (Peak: 343308 KB), Simulation CPU Usage: 890 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh new file mode 100755 index 0000000..4f29b67 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Fri Jun 12 15:48:20 CEST 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log" +xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log + diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xelab.pb b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xelab.pb new file mode 100644 index 0000000000000000000000000000000000000000..5689620fd97d2f80bad56253e55c0ce377628ecb GIT binary patch literal 3278 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b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt new file mode 100644 index 0000000..1de1768 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_edge_func_synth" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git 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a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c new file mode 100644 index 0000000..22669a6 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.c @@ -0,0 +1,479 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void execute_1264(char*, char *); +IKI_DLLESPEC extern void execute_1265(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2351(char*, char *); +IKI_DLLESPEC extern void execute_2353(char*, char *); +IKI_DLLESPEC extern void execute_2354(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_2407(char*, char *); +IKI_DLLESPEC extern void execute_2408(char*, char *); +IKI_DLLESPEC extern void execute_2409(char*, char *); +IKI_DLLESPEC extern void execute_2410(char*, char *); +IKI_DLLESPEC extern void execute_2411(char*, char *); +IKI_DLLESPEC extern void execute_2412(char*, char *); +IKI_DLLESPEC extern void execute_2413(char*, char *); +IKI_DLLESPEC extern void execute_2414(char*, char *); +IKI_DLLESPEC extern void execute_2415(char*, char *); +IKI_DLLESPEC extern void execute_29(char*, char *); +IKI_DLLESPEC extern void execute_1276(char*, char *); +IKI_DLLESPEC extern void execute_1277(char*, char *); +IKI_DLLESPEC extern void execute_1278(char*, char *); +IKI_DLLESPEC extern void execute_1279(char*, char *); +IKI_DLLESPEC extern void execute_1275(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void execute_39(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_43(char*, char *); +IKI_DLLESPEC extern void execute_44(char*, char *); +IKI_DLLESPEC extern void execute_47(char*, char *); +IKI_DLLESPEC extern void execute_1293(char*, char *); +IKI_DLLESPEC extern void execute_1294(char*, char *); +IKI_DLLESPEC extern void execute_1292(char*, char *); +IKI_DLLESPEC extern void execute_50(char*, char *); +IKI_DLLESPEC extern void execute_1296(char*, char *); +IKI_DLLESPEC extern void execute_1297(char*, char *); +IKI_DLLESPEC extern void execute_1298(char*, char *); +IKI_DLLESPEC extern void execute_1299(char*, char *); +IKI_DLLESPEC extern void execute_1300(char*, char *); +IKI_DLLESPEC extern void execute_1301(char*, char *); +IKI_DLLESPEC extern void execute_1302(char*, char *); +IKI_DLLESPEC extern void execute_1303(char*, char *); +IKI_DLLESPEC extern void execute_1295(char*, char *); +IKI_DLLESPEC extern void execute_56(char*, char *); +IKI_DLLESPEC extern void execute_57(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_198(char*, char *); +IKI_DLLESPEC extern void execute_199(char*, char *); +IKI_DLLESPEC extern void execute_1454(char*, char *); +IKI_DLLESPEC extern void execute_1455(char*, char *); +IKI_DLLESPEC extern void execute_1456(char*, char *); +IKI_DLLESPEC extern void execute_1457(char*, char *); +IKI_DLLESPEC extern void execute_201(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_203(char*, char *); +IKI_DLLESPEC extern void execute_1458(char*, char *); +IKI_DLLESPEC extern void execute_1459(char*, char *); +IKI_DLLESPEC extern void execute_1460(char*, char *); +IKI_DLLESPEC extern void execute_1461(char*, char *); +IKI_DLLESPEC extern void execute_1470(char*, char *); +IKI_DLLESPEC extern void execute_1471(char*, char *); +IKI_DLLESPEC extern void execute_1472(char*, char *); +IKI_DLLESPEC extern void execute_1475(char*, char *); +IKI_DLLESPEC extern void execute_1476(char*, char *); +IKI_DLLESPEC extern void execute_1477(char*, char *); +IKI_DLLESPEC extern void execute_1478(char*, char *); +IKI_DLLESPEC extern void execute_738(char*, char *); +IKI_DLLESPEC extern void execute_739(char*, char *); +IKI_DLLESPEC extern void execute_740(char*, char *); +IKI_DLLESPEC extern void execute_1845(char*, char *); +IKI_DLLESPEC extern void execute_1846(char*, char *); +IKI_DLLESPEC extern void execute_1847(char*, char *); +IKI_DLLESPEC extern void execute_2103(char*, char *); +IKI_DLLESPEC extern void execute_942(char*, char *); +IKI_DLLESPEC extern void execute_2104(char*, char *); +IKI_DLLESPEC extern void execute_984(char*, char *); +IKI_DLLESPEC extern void execute_2125(char*, char *); +IKI_DLLESPEC extern void execute_2126(char*, char *); +IKI_DLLESPEC extern void execute_2127(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_44(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_45(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_54(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_57(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_58(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_77(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_78(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_79(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_117(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_118(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_119(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_165(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_171(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_172(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_194(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_195(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_199(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_219(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_220(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_221(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_228(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_229(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_230(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_250(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_251(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_257(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_258(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_259(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_264(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_265(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_266(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_271(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_272(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_355(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_356(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_357(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_397(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_401(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_402(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_785(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_791(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_797(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_803(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_827(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_833(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_839(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_845(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_851(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_857(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_863(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_869(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_875(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_881(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_887(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_893(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_899(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_905(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_911(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_917(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_923(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_929(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_935(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_941(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1741(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1747(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1753(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1776(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1790(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1796(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1802(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1852(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1858(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1864(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1892(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1915(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1921(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1927(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1950(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1973(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2000(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2005(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2010(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2015(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2020(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2025(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2140(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2146(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2152(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2158(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2164(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2170(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2176(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2182(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2449(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2455(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2461(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2467(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2473(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2479(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2485(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2491(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2526(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2559(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2580(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2585(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2590(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2595(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2600(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2605(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[350] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)execute_1264, (funcp)execute_1265, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_2350, (funcp)execute_2351, (funcp)execute_2353, (funcp)execute_2354, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_2407, (funcp)execute_2408, (funcp)execute_2409, (funcp)execute_2410, (funcp)execute_2411, (funcp)execute_2412, (funcp)execute_2413, (funcp)execute_2414, (funcp)execute_2415, (funcp)execute_29, (funcp)execute_1276, (funcp)execute_1277, (funcp)execute_1278, (funcp)execute_1279, (funcp)execute_1275, (funcp)execute_38, (funcp)execute_39, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_43, (funcp)execute_44, (funcp)execute_47, (funcp)execute_1293, (funcp)execute_1294, (funcp)execute_1292, (funcp)execute_50, (funcp)execute_1296, (funcp)execute_1297, (funcp)execute_1298, (funcp)execute_1299, (funcp)execute_1300, (funcp)execute_1301, (funcp)execute_1302, (funcp)execute_1303, (funcp)execute_1295, (funcp)execute_56, (funcp)execute_57, (funcp)execute_197, (funcp)execute_198, (funcp)execute_199, (funcp)execute_1454, (funcp)execute_1455, (funcp)execute_1456, (funcp)execute_1457, (funcp)execute_201, (funcp)execute_202, (funcp)execute_203, (funcp)execute_1458, (funcp)execute_1459, (funcp)execute_1460, (funcp)execute_1461, (funcp)execute_1470, (funcp)execute_1471, (funcp)execute_1472, (funcp)execute_1475, (funcp)execute_1476, (funcp)execute_1477, (funcp)execute_1478, (funcp)execute_738, (funcp)execute_739, (funcp)execute_740, (funcp)execute_1845, (funcp)execute_1846, (funcp)execute_1847, (funcp)execute_2103, (funcp)execute_942, (funcp)execute_2104, (funcp)execute_984, (funcp)execute_2125, (funcp)execute_2126, (funcp)execute_2127, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)transaction_42, (funcp)transaction_43, (funcp)transaction_44, (funcp)transaction_45, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_54, (funcp)transaction_57, (funcp)transaction_58, (funcp)transaction_59, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_77, (funcp)transaction_78, (funcp)transaction_79, (funcp)transaction_80, (funcp)transaction_117, (funcp)transaction_118, (funcp)transaction_119, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_165, (funcp)transaction_170, (funcp)transaction_171, (funcp)transaction_172, (funcp)transaction_193, (funcp)transaction_194, (funcp)transaction_195, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_199, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_219, (funcp)transaction_220, (funcp)transaction_221, (funcp)transaction_228, (funcp)transaction_229, (funcp)transaction_230, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_250, (funcp)transaction_251, (funcp)transaction_257, (funcp)transaction_258, (funcp)transaction_259, (funcp)transaction_264, (funcp)transaction_265, (funcp)transaction_266, (funcp)transaction_271, (funcp)transaction_272, (funcp)transaction_273, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_355, (funcp)transaction_356, (funcp)transaction_357, (funcp)transaction_358, (funcp)transaction_360, (funcp)transaction_397, (funcp)transaction_400, (funcp)transaction_401, (funcp)transaction_402, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_785, (funcp)transaction_791, (funcp)transaction_797, (funcp)transaction_803, (funcp)transaction_827, (funcp)transaction_833, (funcp)transaction_839, (funcp)transaction_845, (funcp)transaction_851, (funcp)transaction_857, (funcp)transaction_863, (funcp)transaction_869, (funcp)transaction_875, (funcp)transaction_881, (funcp)transaction_887, (funcp)transaction_893, (funcp)transaction_899, (funcp)transaction_905, (funcp)transaction_911, (funcp)transaction_917, (funcp)transaction_923, (funcp)transaction_929, (funcp)transaction_935, (funcp)transaction_941, (funcp)transaction_1741, (funcp)transaction_1747, (funcp)transaction_1753, (funcp)transaction_1776, (funcp)transaction_1790, (funcp)transaction_1796, (funcp)transaction_1802, (funcp)transaction_1852, (funcp)transaction_1858, (funcp)transaction_1864, (funcp)transaction_1892, (funcp)transaction_1915, (funcp)transaction_1921, (funcp)transaction_1927, (funcp)transaction_1950, (funcp)transaction_1973, (funcp)transaction_2000, (funcp)transaction_2005, (funcp)transaction_2010, (funcp)transaction_2015, (funcp)transaction_2020, (funcp)transaction_2025, (funcp)transaction_2140, (funcp)transaction_2146, (funcp)transaction_2152, (funcp)transaction_2158, (funcp)transaction_2164, (funcp)transaction_2170, (funcp)transaction_2176, (funcp)transaction_2182, (funcp)transaction_2200, (funcp)transaction_2449, (funcp)transaction_2455, (funcp)transaction_2461, (funcp)transaction_2467, (funcp)transaction_2473, (funcp)transaction_2479, (funcp)transaction_2485, (funcp)transaction_2491, (funcp)transaction_2526, (funcp)transaction_2559, (funcp)transaction_2580, (funcp)transaction_2585, (funcp)transaction_2590, (funcp)transaction_2595, (funcp)transaction_2600, (funcp)transaction_2605}; +const int NumRelocateId= 350; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc", (void **)funcTab, 350); + iki_vhdl_file_variable_register(dp + 1091216); + iki_vhdl_file_variable_register(dp + 1091272); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096624, dp + 1639704, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096680, dp + 1640096, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096736, dp + 1640208, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096968, dp + 1640320, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096888, dp + 1640432, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1096928, dp + 1639984, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1097584, dp + 1639872, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_edge_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..e0ed8d7f0f11662b56aaa26888ea237bf80f9873 GIT binary patch literal 29528 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HcmV?d00001 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log new file mode 100644 index 0000000..3a44e3d --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_tb_edge_func_synth/xsimk -simmode gui -wdb project_tb_edge_func_synth.wdb -simrunnum 0 -socket 41063 +Design successfully loaded +Design Loading Memory Usage: 199732 KB (Peak: 199732 KB) +Design Loading CPU Usage: 700 ms +Simulation completed +Simulation Memory Usage: 294496 KB (Peak: 343308 KB) +Simulation CPU Usage: 890 ms diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt new file mode 100644 index 0000000..be910a6 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_func_synth" "xil_defaultlib.project_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o new file 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zjpvo|V=`X5vfKj|gDSiur0p`TtnhYLmV01OdHm?gfgY&x+8M81SuVi&RquKx6R|qh z`AV-{A#HaUpUbrJ4wUw;z)Cb^N%11R_Q3e=iW&jCl&a8>c@+<>#7>!4-p&f_l{JN; zRZ&AGM*O%;v=2{ZB1F7eo^!@zD!q0^6f0vJ-&s{2Z)c?Kx;rqqqPf1Meo%G!z=0JR zxv88zu6|(5s%Fr@UC}al@tu`ky8^*{E`#SCC~cR6tO@a*GVF0sStY=Q%kX-8z4pNP z?iy*kV`bHd8Zx?3Lq;=d42UaKR10ttGO+QzRna~?m9-$^GUV}NGVx}Ow4J_;dwl1h z%6L2Dw=1H9W$fd@HRbVkm9(8xrD?=w6?P5?!WSDdH5#j%CRU6e7fy`Huvf<3+v~MusA5SBjFe@#qsD-En0Q3{WQ5~;D=V;9 z29}}HV5c+jrbxwiSH{~FUOQ9a?XM}1gDPpeQpxzmcV@7&DslX(0y)9u?sHQ8^m^&X zz=;(T8wU;?H)ufB#G3lb0pl76RaBMNSH*I!9u#j^RteaZL&o2WofVa6RF->@H8qrx z2J2XfoiZgDS?xu7?Fz3w& z#zDqwS9U ztnk{EJ{TAsEEkse!5Qq7l?RcPUS!3f0nuJrFycCuUb`xam8Y?8SNI?k56D!;+m&9s z!fVSdW&D6lMZ7IHjUE_S9tTy@-Zj3a!GtqjyV7s(2FfXyI4vtb)wHaPlFAIKj3rem zZI`i3y7Bo zcvD{ZL`oHG$TW=hRK<^~k+#c4R!Gch4&28D~q)pz^4*8EJ55C3ebujqj}CfzpT_=(Vf8 z-BkkIP|0n7)TpTRLI=i=tnu0zX-7idPI+5n*G`$gaV2>%fxT5|$b^lDR>hkYgEDbY z_^Uq`}+bamVB`7Wb z!2D!82*&n}@3cSdjM&}s)G(2WZCP!-yD)x4Nh~S|ZkKj +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + +#if defined(_WIN32) + #include "stdio.h" + #define IKI_DLLESPEC __declspec(dllimport) +#else + #define IKI_DLLESPEC +#endif +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +IKI_DLLESPEC extern void execute_2(char*, char *); +IKI_DLLESPEC extern void execute_3(char*, char *); +IKI_DLLESPEC extern void execute_4(char*, char *); +IKI_DLLESPEC extern void execute_5(char*, char *); +IKI_DLLESPEC extern void execute_6(char*, char *); +IKI_DLLESPEC extern void execute_7(char*, char *); +IKI_DLLESPEC extern void execute_8(char*, char *); +IKI_DLLESPEC extern void execute_9(char*, char *); +IKI_DLLESPEC extern void execute_10(char*, char *); +IKI_DLLESPEC extern void execute_11(char*, char *); +IKI_DLLESPEC extern void execute_1260(char*, char *); +IKI_DLLESPEC extern void execute_1261(char*, char *); +IKI_DLLESPEC extern void execute_1262(char*, char *); +IKI_DLLESPEC extern void execute_1263(char*, char *); +IKI_DLLESPEC extern void vlog_const_rhs_process_execute_0_fast_for_reg(char*, char*, char*); +IKI_DLLESPEC extern void execute_2341(char*, char *); +IKI_DLLESPEC extern void execute_2342(char*, char *); +IKI_DLLESPEC extern void execute_2344(char*, char *); +IKI_DLLESPEC extern void execute_2345(char*, char *); +IKI_DLLESPEC extern void execute_2346(char*, char *); +IKI_DLLESPEC extern void execute_2347(char*, char *); +IKI_DLLESPEC extern void execute_2348(char*, char *); +IKI_DLLESPEC extern void execute_2349(char*, char *); +IKI_DLLESPEC extern void execute_2350(char*, char *); +IKI_DLLESPEC extern void execute_2351(char*, char *); +IKI_DLLESPEC extern void execute_2352(char*, char *); +IKI_DLLESPEC extern void execute_2353(char*, char *); +IKI_DLLESPEC extern void execute_2354(char*, char *); +IKI_DLLESPEC extern void execute_2355(char*, char *); +IKI_DLLESPEC extern void execute_2356(char*, char *); +IKI_DLLESPEC extern void execute_2357(char*, char *); +IKI_DLLESPEC extern void execute_2358(char*, char *); +IKI_DLLESPEC extern void execute_2359(char*, char *); +IKI_DLLESPEC extern void execute_2360(char*, char *); +IKI_DLLESPEC extern void execute_2361(char*, char *); +IKI_DLLESPEC extern void execute_2362(char*, char *); +IKI_DLLESPEC extern void execute_2363(char*, char *); +IKI_DLLESPEC extern void execute_2364(char*, char *); +IKI_DLLESPEC extern void execute_2365(char*, char *); +IKI_DLLESPEC extern void execute_2366(char*, char *); +IKI_DLLESPEC extern void execute_2367(char*, char *); +IKI_DLLESPEC extern void execute_2368(char*, char *); +IKI_DLLESPEC extern void execute_2369(char*, char *); +IKI_DLLESPEC extern void execute_2370(char*, char *); +IKI_DLLESPEC extern void execute_2371(char*, char *); +IKI_DLLESPEC extern void execute_2372(char*, char *); +IKI_DLLESPEC extern void execute_2373(char*, char *); +IKI_DLLESPEC extern void execute_2374(char*, char *); +IKI_DLLESPEC extern void execute_2375(char*, char *); +IKI_DLLESPEC extern void execute_2376(char*, char *); +IKI_DLLESPEC extern void execute_2377(char*, char *); +IKI_DLLESPEC extern void execute_2378(char*, char *); +IKI_DLLESPEC extern void execute_2379(char*, char *); +IKI_DLLESPEC extern void execute_2380(char*, char *); +IKI_DLLESPEC extern void execute_2381(char*, char *); +IKI_DLLESPEC extern void execute_2382(char*, char *); +IKI_DLLESPEC extern void execute_2383(char*, char *); +IKI_DLLESPEC extern void execute_2384(char*, char *); +IKI_DLLESPEC extern void execute_2385(char*, char *); +IKI_DLLESPEC extern void execute_2386(char*, char *); +IKI_DLLESPEC extern void execute_2387(char*, char *); +IKI_DLLESPEC extern void execute_2388(char*, char *); +IKI_DLLESPEC extern void execute_2389(char*, char *); +IKI_DLLESPEC extern void execute_2390(char*, char *); +IKI_DLLESPEC extern void execute_2391(char*, char *); +IKI_DLLESPEC extern void execute_2392(char*, char *); +IKI_DLLESPEC extern void execute_2393(char*, char *); +IKI_DLLESPEC extern void execute_2394(char*, char *); +IKI_DLLESPEC extern void execute_2395(char*, char *); +IKI_DLLESPEC extern void execute_2396(char*, char *); +IKI_DLLESPEC extern void execute_2397(char*, char *); +IKI_DLLESPEC extern void execute_2398(char*, char *); +IKI_DLLESPEC extern void execute_2399(char*, char *); +IKI_DLLESPEC extern void execute_2400(char*, char *); +IKI_DLLESPEC extern void execute_2401(char*, char *); +IKI_DLLESPEC extern void execute_2402(char*, char *); +IKI_DLLESPEC extern void execute_2403(char*, char *); +IKI_DLLESPEC extern void execute_2404(char*, char *); +IKI_DLLESPEC extern void execute_2405(char*, char *); +IKI_DLLESPEC extern void execute_2406(char*, char *); +IKI_DLLESPEC extern void execute_28(char*, char *); +IKI_DLLESPEC extern void execute_1267(char*, char *); +IKI_DLLESPEC extern void execute_1268(char*, char *); +IKI_DLLESPEC extern void execute_1269(char*, char *); +IKI_DLLESPEC extern void execute_1270(char*, char *); +IKI_DLLESPEC extern void execute_1266(char*, char *); +IKI_DLLESPEC extern void execute_37(char*, char *); +IKI_DLLESPEC extern void execute_38(char*, char *); +IKI_DLLESPEC extern void vlog_simple_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +IKI_DLLESPEC extern void execute_42(char*, char *); +IKI_DLLESPEC extern void execute_43(char*, char *); +IKI_DLLESPEC extern void execute_46(char*, char *); +IKI_DLLESPEC extern void execute_1284(char*, char *); +IKI_DLLESPEC extern void execute_1285(char*, char *); +IKI_DLLESPEC extern void execute_1283(char*, char *); +IKI_DLLESPEC extern void execute_49(char*, char *); +IKI_DLLESPEC extern void execute_1287(char*, char *); +IKI_DLLESPEC extern void execute_1288(char*, char *); +IKI_DLLESPEC extern void execute_1289(char*, char *); +IKI_DLLESPEC extern void execute_1290(char*, char *); +IKI_DLLESPEC extern void execute_1291(char*, char *); +IKI_DLLESPEC extern void execute_1292(char*, char *); +IKI_DLLESPEC extern void execute_1293(char*, char *); +IKI_DLLESPEC extern void execute_1294(char*, char *); +IKI_DLLESPEC extern void execute_1286(char*, char *); +IKI_DLLESPEC extern void execute_55(char*, char *); +IKI_DLLESPEC extern void execute_56(char*, char *); +IKI_DLLESPEC extern void execute_196(char*, char *); +IKI_DLLESPEC extern void execute_197(char*, char *); +IKI_DLLESPEC extern void execute_198(char*, char *); +IKI_DLLESPEC extern void execute_1445(char*, char *); +IKI_DLLESPEC extern void execute_1446(char*, char *); +IKI_DLLESPEC extern void execute_1447(char*, char *); +IKI_DLLESPEC extern void execute_1448(char*, char *); +IKI_DLLESPEC extern void execute_200(char*, char *); +IKI_DLLESPEC extern void execute_201(char*, char *); +IKI_DLLESPEC extern void execute_202(char*, char *); +IKI_DLLESPEC extern void execute_1449(char*, char *); +IKI_DLLESPEC extern void execute_1450(char*, char *); +IKI_DLLESPEC extern void execute_1451(char*, char *); +IKI_DLLESPEC extern void execute_1452(char*, char *); +IKI_DLLESPEC extern void execute_1461(char*, char *); +IKI_DLLESPEC extern void execute_1462(char*, char *); +IKI_DLLESPEC extern void execute_1463(char*, char *); +IKI_DLLESPEC extern void execute_1466(char*, char *); +IKI_DLLESPEC extern void execute_1467(char*, char *); +IKI_DLLESPEC extern void execute_1468(char*, char *); +IKI_DLLESPEC extern void execute_1469(char*, char *); +IKI_DLLESPEC extern void execute_737(char*, char *); +IKI_DLLESPEC extern void execute_738(char*, char *); +IKI_DLLESPEC extern void execute_739(char*, char *); +IKI_DLLESPEC extern void execute_1836(char*, char *); +IKI_DLLESPEC extern void execute_1837(char*, char *); +IKI_DLLESPEC extern void execute_1838(char*, char *); +IKI_DLLESPEC extern void execute_2094(char*, char *); +IKI_DLLESPEC extern void execute_941(char*, char *); +IKI_DLLESPEC extern void execute_2095(char*, char *); +IKI_DLLESPEC extern void execute_983(char*, char *); +IKI_DLLESPEC extern void execute_2116(char*, char *); +IKI_DLLESPEC extern void execute_2117(char*, char *); +IKI_DLLESPEC extern void execute_2118(char*, char *); +IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_34(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_35(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_36(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_37(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_38(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_39(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_40(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_41(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +IKI_DLLESPEC extern void transaction_43(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_46(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_48(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_51(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_52(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_60(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_61(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_62(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_63(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_64(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_65(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_66(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_67(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_68(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_69(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_70(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_71(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_72(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_80(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_81(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_82(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_83(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_120(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_121(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_122(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_123(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_124(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_125(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_168(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_174(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_175(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_197(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_198(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_200(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_201(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_202(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_222(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_223(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_224(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_231(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_232(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_233(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_234(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_235(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_253(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_254(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_260(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_261(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_262(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_267(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_268(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_269(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_274(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_275(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_276(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_277(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_278(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_279(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_280(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_281(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_282(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_283(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_284(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_285(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_286(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_287(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_288(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_289(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_290(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_291(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_295(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_296(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_297(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_298(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_299(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_300(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_301(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_302(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_303(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_305(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_306(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_307(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_308(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_309(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_310(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_311(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_312(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_313(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_314(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_315(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_316(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_317(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_318(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_319(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_320(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_321(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_322(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_323(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_324(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_325(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_326(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_327(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_328(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_329(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_330(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_331(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_358(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_359(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_360(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_361(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_363(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_400(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_403(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_404(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_405(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_406(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_407(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_408(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_409(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_788(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_794(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_800(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_806(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_830(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_836(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_842(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_848(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_854(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_860(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_866(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_872(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_878(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_884(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_890(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_896(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_902(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_908(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_914(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_920(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_926(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_932(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_938(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_944(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1744(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1750(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1756(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1779(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1793(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1799(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1805(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1855(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1861(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1867(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1895(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1918(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1924(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1930(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1953(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_1976(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2003(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2008(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2013(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2018(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2023(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2028(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2143(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2149(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2155(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2161(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2167(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2173(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2179(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2185(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2203(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2452(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2458(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2464(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2470(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2476(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2482(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2488(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2494(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2529(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2562(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2583(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2588(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2593(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2598(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2603(char*, char*, unsigned, unsigned, unsigned); +IKI_DLLESPEC extern void transaction_2608(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[349] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_1260, (funcp)execute_1261, (funcp)execute_1262, (funcp)execute_1263, (funcp)vlog_const_rhs_process_execute_0_fast_for_reg, (funcp)execute_2341, (funcp)execute_2342, (funcp)execute_2344, (funcp)execute_2345, (funcp)execute_2346, (funcp)execute_2347, (funcp)execute_2348, (funcp)execute_2349, (funcp)execute_2350, (funcp)execute_2351, (funcp)execute_2352, (funcp)execute_2353, (funcp)execute_2354, (funcp)execute_2355, (funcp)execute_2356, (funcp)execute_2357, (funcp)execute_2358, (funcp)execute_2359, (funcp)execute_2360, (funcp)execute_2361, (funcp)execute_2362, (funcp)execute_2363, (funcp)execute_2364, (funcp)execute_2365, (funcp)execute_2366, (funcp)execute_2367, (funcp)execute_2368, (funcp)execute_2369, (funcp)execute_2370, (funcp)execute_2371, (funcp)execute_2372, (funcp)execute_2373, (funcp)execute_2374, (funcp)execute_2375, (funcp)execute_2376, (funcp)execute_2377, (funcp)execute_2378, (funcp)execute_2379, (funcp)execute_2380, (funcp)execute_2381, (funcp)execute_2382, (funcp)execute_2383, (funcp)execute_2384, (funcp)execute_2385, (funcp)execute_2386, (funcp)execute_2387, (funcp)execute_2388, (funcp)execute_2389, (funcp)execute_2390, (funcp)execute_2391, (funcp)execute_2392, (funcp)execute_2393, (funcp)execute_2394, (funcp)execute_2395, (funcp)execute_2396, (funcp)execute_2397, (funcp)execute_2398, (funcp)execute_2399, (funcp)execute_2400, (funcp)execute_2401, (funcp)execute_2402, (funcp)execute_2403, (funcp)execute_2404, (funcp)execute_2405, (funcp)execute_2406, (funcp)execute_28, (funcp)execute_1267, (funcp)execute_1268, (funcp)execute_1269, (funcp)execute_1270, (funcp)execute_1266, (funcp)execute_37, (funcp)execute_38, (funcp)vlog_simple_process_execute_0_fast_no_reg_no_agg, (funcp)execute_42, (funcp)execute_43, (funcp)execute_46, (funcp)execute_1284, (funcp)execute_1285, (funcp)execute_1283, (funcp)execute_49, (funcp)execute_1287, (funcp)execute_1288, (funcp)execute_1289, (funcp)execute_1290, (funcp)execute_1291, (funcp)execute_1292, (funcp)execute_1293, (funcp)execute_1294, (funcp)execute_1286, (funcp)execute_55, (funcp)execute_56, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_1445, (funcp)execute_1446, (funcp)execute_1447, (funcp)execute_1448, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_1449, (funcp)execute_1450, (funcp)execute_1451, (funcp)execute_1452, (funcp)execute_1461, (funcp)execute_1462, (funcp)execute_1463, (funcp)execute_1466, (funcp)execute_1467, (funcp)execute_1468, (funcp)execute_1469, (funcp)execute_737, (funcp)execute_738, (funcp)execute_739, (funcp)execute_1836, (funcp)execute_1837, (funcp)execute_1838, (funcp)execute_2094, (funcp)execute_941, (funcp)execute_2095, (funcp)execute_983, (funcp)execute_2116, (funcp)execute_2117, (funcp)execute_2118, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_34, (funcp)transaction_35, (funcp)transaction_36, (funcp)transaction_37, (funcp)transaction_38, (funcp)transaction_39, (funcp)transaction_40, (funcp)transaction_41, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_43, (funcp)transaction_46, (funcp)transaction_48, (funcp)transaction_51, (funcp)transaction_52, (funcp)transaction_60, (funcp)transaction_61, (funcp)transaction_62, (funcp)transaction_63, (funcp)transaction_64, (funcp)transaction_65, (funcp)transaction_66, (funcp)transaction_67, (funcp)transaction_68, (funcp)transaction_69, (funcp)transaction_70, (funcp)transaction_71, (funcp)transaction_72, (funcp)transaction_80, (funcp)transaction_81, (funcp)transaction_82, (funcp)transaction_83, (funcp)transaction_120, (funcp)transaction_121, (funcp)transaction_122, (funcp)transaction_123, (funcp)transaction_124, (funcp)transaction_125, (funcp)transaction_168, (funcp)transaction_173, (funcp)transaction_174, (funcp)transaction_175, (funcp)transaction_196, (funcp)transaction_197, (funcp)transaction_198, (funcp)transaction_200, (funcp)transaction_201, (funcp)transaction_202, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_222, (funcp)transaction_223, (funcp)transaction_224, (funcp)transaction_231, (funcp)transaction_232, (funcp)transaction_233, (funcp)transaction_234, (funcp)transaction_235, (funcp)transaction_253, (funcp)transaction_254, (funcp)transaction_260, (funcp)transaction_261, (funcp)transaction_262, (funcp)transaction_267, (funcp)transaction_268, (funcp)transaction_269, (funcp)transaction_274, (funcp)transaction_275, (funcp)transaction_276, (funcp)transaction_277, (funcp)transaction_278, (funcp)transaction_279, (funcp)transaction_280, (funcp)transaction_281, (funcp)transaction_282, (funcp)transaction_283, (funcp)transaction_284, (funcp)transaction_285, (funcp)transaction_286, (funcp)transaction_287, (funcp)transaction_288, (funcp)transaction_289, (funcp)transaction_290, (funcp)transaction_291, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_295, (funcp)transaction_296, (funcp)transaction_297, (funcp)transaction_298, (funcp)transaction_299, (funcp)transaction_300, (funcp)transaction_301, (funcp)transaction_302, (funcp)transaction_303, (funcp)transaction_304, (funcp)transaction_305, (funcp)transaction_306, (funcp)transaction_307, (funcp)transaction_308, (funcp)transaction_309, (funcp)transaction_310, (funcp)transaction_311, (funcp)transaction_312, (funcp)transaction_313, (funcp)transaction_314, (funcp)transaction_315, (funcp)transaction_316, (funcp)transaction_317, (funcp)transaction_318, (funcp)transaction_319, (funcp)transaction_320, (funcp)transaction_321, (funcp)transaction_322, (funcp)transaction_323, (funcp)transaction_324, (funcp)transaction_325, (funcp)transaction_326, (funcp)transaction_327, (funcp)transaction_328, (funcp)transaction_329, (funcp)transaction_330, (funcp)transaction_331, (funcp)transaction_358, (funcp)transaction_359, (funcp)transaction_360, (funcp)transaction_361, (funcp)transaction_363, (funcp)transaction_400, (funcp)transaction_403, (funcp)transaction_404, (funcp)transaction_405, (funcp)transaction_406, (funcp)transaction_407, (funcp)transaction_408, (funcp)transaction_409, (funcp)transaction_788, (funcp)transaction_794, (funcp)transaction_800, (funcp)transaction_806, (funcp)transaction_830, (funcp)transaction_836, (funcp)transaction_842, (funcp)transaction_848, (funcp)transaction_854, (funcp)transaction_860, (funcp)transaction_866, (funcp)transaction_872, (funcp)transaction_878, (funcp)transaction_884, (funcp)transaction_890, (funcp)transaction_896, (funcp)transaction_902, (funcp)transaction_908, (funcp)transaction_914, (funcp)transaction_920, (funcp)transaction_926, (funcp)transaction_932, (funcp)transaction_938, (funcp)transaction_944, (funcp)transaction_1744, (funcp)transaction_1750, (funcp)transaction_1756, (funcp)transaction_1779, (funcp)transaction_1793, (funcp)transaction_1799, (funcp)transaction_1805, (funcp)transaction_1855, (funcp)transaction_1861, (funcp)transaction_1867, (funcp)transaction_1895, (funcp)transaction_1918, (funcp)transaction_1924, (funcp)transaction_1930, (funcp)transaction_1953, (funcp)transaction_1976, (funcp)transaction_2003, (funcp)transaction_2008, (funcp)transaction_2013, (funcp)transaction_2018, (funcp)transaction_2023, (funcp)transaction_2028, (funcp)transaction_2143, (funcp)transaction_2149, (funcp)transaction_2155, (funcp)transaction_2161, (funcp)transaction_2167, (funcp)transaction_2173, (funcp)transaction_2179, (funcp)transaction_2185, (funcp)transaction_2203, (funcp)transaction_2452, (funcp)transaction_2458, (funcp)transaction_2464, (funcp)transaction_2470, (funcp)transaction_2476, (funcp)transaction_2482, (funcp)transaction_2488, (funcp)transaction_2494, (funcp)transaction_2529, (funcp)transaction_2562, (funcp)transaction_2583, (funcp)transaction_2588, (funcp)transaction_2593, (funcp)transaction_2598, (funcp)transaction_2603, (funcp)transaction_2608}; +const int NumRelocateId= 349; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/project_tb_func_synth/xsim.reloc", (void **)funcTab, 349); + iki_vhdl_file_variable_register(dp + 1118456); + iki_vhdl_file_variable_register(dp + 1118512); + + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/project_tb_func_synth/xsim.reloc"); +} + + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + +void wrapper_func_0(char *dp) + +{ + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123864, dp + 1666144, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123920, dp + 1666536, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1123976, dp + 1666648, 0, 0, 0, 0, 1, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124208, dp + 1666760, 0, 5, 0, 5, 6, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124128, dp + 1666872, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124168, dp + 1666424, 0, 1, 0, 1, 2, 1); + + iki_vlog_schedule_transaction_signal_fast_vhdl_value_time_0(dp + 1124488, dp + 1666312, 0, 7, 0, 7, 8, 1); + +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_func_synth/xsim.reloc"); + wrapper_func_0(dp); + + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_xsimdir_location_if_remapped(argc, argv) ; + iki_set_sv_type_file_path_name("xsim.dir/project_tb_func_synth/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_func_synth/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/project_tb_func_synth/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o b/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o new file mode 100644 index 0000000000000000000000000000000000000000..f0103bf49279109d4f53377ebc0ecbc9f4de2519 GIT binary patch literal 29440 zcmeI*eRy0|oxt%)ff5m73cdspnDS;+2y(S~*Ojm8YAMDzC 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