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aleandro
2026-06-12 20:37:03 +02:00
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progetto_reti_logiche.sim/sim_1/behav/xsim/compile.log
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INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'project_reti_logiche'
progetto_reti_logiche.sim/sim_1/behav/xsim/compile.sh
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#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename : compile.sh
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Fri Jun 12 15:55:43 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: compile.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# compile VHDL design sources
echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj"
xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee compile.log
echo "Waiting for jobs to finish..."
echo "No pending jobs, compilation finished."
progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.log
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Vivado Simulator v2025.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture fsm of entity xil_defaultlib.project_reti_logiche [project_reti_logiche_default]
Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
Built simulation snapshot project_tb_edge_behav
progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh
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#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename : elaborate.sh
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Fri Jun 12 15:55:44 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: elaborate.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# elaborate design
echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log"
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log
progetto_reti_logiche.sim/sim_1/behav/xsim/hs_err_pid256439.log
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#
# An unexpected error has occurred (11) Segmentation fault
#
Stack:
/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7fd51747195c]
/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7fd51747242e]
/usr/lib/libc.so.6(+0x3e2d0) [0x7fd556e4d2d0]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7fd52434ebcb]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector<SimBridge::IDataObj const*, std::allocator<SimBridge::IDataObj const*> > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7fd52434f1e1]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0x6f) [0x7fd52436a6ff]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0xb7) [0x7fd5243c2cd7]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0x128) [0x7fd5243c60c8]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7fd5243a9596]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7fd5243a3f64]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7fd5243f1b2f]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7fd5243f1ca4]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7fd5242391a7]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7fd52423922c]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7fd52423a8e8]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7fd5243f137e]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7fd5244037da]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7fd524403c62]
/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7fd5242050dc]
[0x7fd506f7a1ea]
progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche.tcl
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns
progetto_reti_logiche.sim/sim_1/behav/xsim/project_reti_logiche_behav.wdb
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progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb.tcl
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns
progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_behav.wdb
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progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge.tcl
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run all
progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_behav.wdb
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progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_edge_vhdl.prj
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# compile vhdl design source files
vhdl xil_defaultlib \
"../../../../progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" \
"../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \
# Do not sort compile order
nosort
progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing.tcl
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns
progetto_reti_logiche.sim/sim_1/behav/xsim/project_tb_timing_behav.wdb
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progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.log
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Time resolution is 1 ps
Note: === GRUPPO 0: Reset ===
Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.0 OK: reset base
Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.1 OK: reset asincrono durante operazione
Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 1: Inserimento ===
Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.0 OK: insert in lista vuota
Time: 3670 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.1 OK: insert con priorità massima in testa
Time: 6010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.2 OK: insert con priorità minima in fondo
Time: 8230 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali
Time: 10450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo
Time: 12950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.5 OK: insert con ID duplicato ignorato
Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 2: Rimozione ===
Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0
Time: 16990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto
Time: 18930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato
Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 3: Decremento priorità ===
Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.0 OK: decremento su lista vuota
Time: 23130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.1 OK: saturazione a priorità 3
Time: 25350 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica
Time: 27870 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)
Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 4: Svuota lista ===
Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.0 OK: svuota lista popolata
Time: 33050 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.1 OK: svuota lista già vuota
Time: 34730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0
Time: 36690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto
Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 5: Sequenze composite ===
Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto
Time: 41490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 5.1 OK: ordinamento completo con priorità miste
Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 6: Rimozione multipla e ordinamento ===
Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota
Time: 48310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1
Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 7: Decremento ripetuto ===
Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3
Time: 53430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente
Time: 57010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.1 OK: decremento su lista con un solo task
Time: 59330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota
Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 8: Insert dopo rimozione e casi limite ===
Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto
Time: 64950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato
Time: 67830 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato
Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 9: o_task_id per OP diverso da 01 ===
Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1
Time: 72490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1
Time: 74450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1
Time: 76330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1
Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 10: Protocollo, reset avanzato, stress ===
Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset
Time: 79750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert)
Time: 92030 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato
Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 11: Insert con ID=0 ===
Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato
Time: 96290 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato
Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 12: Capacita' massima 63 task ===
Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata
Time: 231450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati
Time: 235970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.2 OK: drain di 63 task nell'ordine atteso
Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 13: Stale memory e duplicati ai bordi ===
Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.0 OK: re-insert di ID appena rimosso
Time: 365710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.1 OK: duplicato in prima posizione ignorato
Time: 368130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.2 OK: duplicato in ultima posizione ignorato
Time: 368250 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.3 OK: re-insert stesso ID dopo clear
Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 14: Reset asincrono avanzato ===
Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.0 OK: reset a meta' shift di OP=01
Time: 373150 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.1 OK: reset durante la scrittura del count
Time: 375930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.2 OK: reset durante OP=00
Time: 378470 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.3 OK: reset mentre DONE=1
Time: 380550 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.4 OK: reset corto non allineato
Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 15: START lento dopo DONE=1 ===
Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.0 OK: nessun doppio pop con START lento
Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.1 OK: nessun doppio age con START lento
Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.2 OK: insert con START tenuto 2 cicli extra
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Failure: ======================================
Tutti i test edge case sono PASSATI
======================================
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616
INFO: xsimkernel Simulation Memory Usage: 291592 KB (Peak: 337672 KB), Simulation CPU Usage: 710 ms
progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.sh
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#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename : simulate.sh
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Fri Jun 12 15:55:46 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: simulate.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# simulate design
echo "xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log"
xsim project_tb_edge_behav -key {Behavioral:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log
progetto_reti_logiche.sim/sim_1/behav/xsim/xelab.pb
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progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/Compile_Options.txt
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_reti_logiche_behav" "xil_defaultlib.project_reti_logiche" -log "elaborate.log"
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/TempBreakPointFile.txt
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_26(char*, char *);
IKI_DLLESPEC extern void execute_27(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[4] = {(funcp)execute_26, (funcp)execute_27, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 4;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc", (void **)funcTab, 4);
iki_vhdl_file_variable_register(dp + 9192);
iki_vhdl_file_variable_register(dp + 9248);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_reti_logiche_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o
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progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rlx
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{
crc : 13885744666178239796 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_reti_logiche_behav xil_defaultlib.project_reti_logiche" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_reti_logiche_behav/xsimk\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o\" -L\"/opt/vivado/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.rtti
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progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsim.version
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hjhoth
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progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimSettings.ini
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[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=173
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=159
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/xsimcrash.log
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Running: xsim.dir/project_reti_logiche_behav/xsimk -simmode gui -wdb project_reti_logiche_behav.wdb -simrunnum 0 -socket 60931
Design successfully loaded
Design Loading Memory Usage: 196484 KB (Peak: 196604 KB)
Design Loading CPU Usage: 750 ms
Simulation completed
Simulation Memory Usage: 278220 KB (Peak: 335752 KB)
Simulation CPU Usage: 770 ms
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_behav" "xil_defaultlib.project_tb" -log "elaborate.log"
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/TempBreakPointFile.txt
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 9;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_behav/xsim.reloc", (void **)funcTab, 9);
iki_vhdl_file_variable_register(dp + 562288);
iki_vhdl_file_variable_register(dp + 562344);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 7473175962787144638 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_behav xil_defaultlib.project_tb" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_behav/xsimk\" \"xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=120
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=181
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_tb_behav/xsimk -simmode gui -wdb project_tb_behav.wdb -simrunnum 0 -socket 39125
Design successfully loaded
Design Loading Memory Usage: 198324 KB (Peak: 198324 KB)
Design Loading CPU Usage: 690 ms
Simulation completed
Simulation Memory Usage: 291512 KB (Peak: 337592 KB)
Simulation CPU Usage: 700 ms
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_edge_behav" "xil_defaultlib.project_tb_edge" -log "elaborate.log"
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_40(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[10] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 10;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc", (void **)funcTab, 10);
iki_vhdl_file_variable_register(dp + 535048);
iki_vhdl_file_variable_register(dp + 535104);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_edge_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 5620043674301555198 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_behav/xsimk\" \"xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=156
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=191
OBJECT_VALUE_COLUMN_WIDTH=1024
OBJECT_DATA_TYPE_COLUMN_WIDTH=76
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_tb_edge_behav/xsimk -simmode gui -wdb project_tb_edge_behav.wdb -simrunnum 0 -socket 59621
Design successfully loaded
Design Loading Memory Usage: 198404 KB (Peak: 198404 KB)
Design Loading CPU Usage: 680 ms
Simulation completed
Simulation Memory Usage: 291592 KB (Peak: 337672 KB)
Simulation CPU Usage: 710 ms
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_timing_behav" "xil_defaultlib.project_tb_timing" -log "elaborate.log"
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 9;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc", (void **)funcTab, 9);
iki_vhdl_file_variable_register(dp + 534752);
iki_vhdl_file_variable_register(dp + 534808);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_timing_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_timing_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_timing_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 6692423544243212696 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_timing_behav xil_defaultlib.project_tb_timing" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_timing_behav/xsimk\" \"xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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hjhoth
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=168
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=191
OBJECT_VALUE_COLUMN_WIDTH=5823
OBJECT_DATA_TYPE_COLUMN_WIDTH=96
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_timing_behav/xsimcrash.log
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Running: xsim.dir/project_tb_timing_behav/xsimk -simmode gui -wdb project_tb_timing_behav.wdb -simrunnum 0 -socket 42147
Design successfully loaded
Design Loading Memory Usage: 198300 KB (Peak: 198300 KB)
Design Loading CPU Usage: 700 ms
Simulation completed
Simulation Memory Usage: 291488 KB (Peak: 337568 KB)
Simulation CPU Usage: 720 ms
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0.7
2020.2
Nov 14 2025
12:36:23
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd,1781272532,vhdl,,,,project_reti_logiche,,,,,,,,
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.ini
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xil_defaultlib=xsim.dir/xil_defaultlib
progetto_reti_logiche.sim/sim_1/behav/xsim/xvhdl.log
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INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'project_reti_logiche'
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progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.log
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module project_reti_logiche
INFO: [VRFC 10-311] analyzing module glbl
progetto_reti_logiche.sim/sim_1/synth/func/xsim/compile.sh
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#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename : compile.sh
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Fri Jun 12 15:48:15 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: compile.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# compile Verilog/System Verilog design sources
echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj"
xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log
# compile VHDL design sources
echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj"
xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log
echo "Waiting for jobs to finish..."
echo "No pending jobs, compilation finished."
progetto_reti_logiche.sim/sim_1/synth/func/xsim/elaborate.log
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Vivado Simulator v2025.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package vl.vl_types
Compiling module xil_defaultlib.glbl
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module unisims_ver.LUT4
Compiling module unisims_ver.LUT5
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3
Compiling module unisims_ver.LUT6
Compiling module unisims_ver.FDPE_default
Compiling module unisims_ver.FDCE_default
Compiling module unisims_ver.CARRY4
Compiling module unisims_ver.FDRE_default
Compiling module unisims_ver.BUFG
Compiling module unisims_ver.IBUF
Compiling module unisims_ver.OBUF
Compiling module xil_defaultlib.project_reti_logiche
Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
Built simulation snapshot project_tb_edge_func_synth

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