Vivado Simulator v2025.2
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT".
INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "project_tb_edge_time_synth.sdf", for root module "project_tb_edge/UUT".
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package vl.vl_types
Compiling module xil_defaultlib.glbl
Compiling module simprims_ver.x_lut2_mux4
Compiling module simprims_ver.LUT2
Compiling module simprims_ver.LUT5
Compiling module simprims_ver.LUT4
Compiling module simprims_ver.x_lut1_mux2
Compiling module simprims_ver.LUT1
Compiling module simprims_ver.x_lut3_mux8
Compiling module simprims_ver.LUT3
Compiling module simprims_ver.LUT6
Compiling module simprims_ver.FDPE_default
Compiling module simprims_ver.FDCE_default
Compiling module simprims_ver.CARRY4
Compiling module simprims_ver.FDRE_default
Compiling module simprims_ver.BUFG
Compiling module simprims_ver.IBUF
Compiling module simprims_ver.OBUF
Compiling module xil_defaultlib.project_reti_logiche
Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
Built simulation snapshot project_tb_edge_time_synth
