Aleandro/Progetto-reti-logiche
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aleandro
2026-06-12 20:37:03 +02:00
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progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xvlog.log
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module project_reti_logiche
INFO: [VRFC 10-311] analyzing module glbl