Initial commit

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/Compile_Options.txt

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+--incr --debug "typical" --relax --mt "8" --maxdelay -L "xil_defaultlib" -L "simprims_ver" -L "secureip" --snapshot "project_tb_edge_time_synth" -transport_int_delays -pulse_r "0" -pulse_int_r "0" -pulse_e "0" -pulse_int_e "0" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log" 

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/TempBreakPointFile.txt

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+Breakpoint File Version 1.0

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.rlx

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+
+{ 
+    crc :  10190631582523672948  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot project_tb_edge_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.project_tb_edge xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/project_tb_edge_time_synth/xsimk\"   \"xsim.dir/project_tb_edge_time_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_1.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_2.lnx64.o\" \"xsim.dir/project_tb_edge_time_synth/obj/xsim_3.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsim.version

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+hjhoth

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimSettings.ini

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+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=150
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=233
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/project_tb_edge_time_synth/xsimkernel.log

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+Running: xsim.dir/project_tb_edge_time_synth/xsimk -simmode gui -wdb project_tb_edge_time_synth.wdb -simrunnum 0 -socket 39331
+Design successfully loaded
+Design Loading Memory Usage: 202828 KB (Peak: 202828 KB)
+Design Loading CPU Usage: 730 ms
+Simulation completed
+Simulation Memory Usage: 296232 KB (Peak: 342096 KB)
+Simulation CPU Usage: 820 ms

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

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+0.7
+2020.2
+Nov 14 2025
+12:36:23
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v,1781182260,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,

progetto_reti_logiche.sim/sim_1/synth/timing/xsim/xsim.dir/xsim.version

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+hjhoth