Initial commit

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_edge_func_synth" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log" 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/TempBreakPointFile.txt

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+Breakpoint File Version 1.0

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  1042013717637638161  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/project_tb_edge_func_synth/xsimk\"   \"xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsim.version

@@ -0,0 +1 @@
+hjhoth

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=156
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109
+OBJECT_NAME_COLUMN_WIDTH=191
+OBJECT_VALUE_COLUMN_WIDTH=1024
+OBJECT_DATA_TYPE_COLUMN_WIDTH=76
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_edge_func_synth/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/project_tb_edge_func_synth/xsimk -simmode gui -wdb project_tb_edge_func_synth.wdb -simrunnum 0 -socket 41063
+Design successfully loaded
+Design Loading Memory Usage: 199732 KB (Peak: 199732 KB)
+Design Loading CPU Usage: 700 ms
+Simulation completed
+Simulation Memory Usage: 294496 KB (Peak: 343308 KB)
+Simulation CPU Usage: 890 ms

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_func_synth" "xil_defaultlib.project_tb" "xil_defaultlib.glbl" -log "elaborate.log" 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  17879923451979115244  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_func_synth xil_defaultlib.project_tb xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/project_tb_func_synth/xsimk\"   \"xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsim.version

@@ -0,0 +1 @@
+hjhoth

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=75
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=240
+OBJECT_VALUE_COLUMN_WIDTH=5823
+OBJECT_DATA_TYPE_COLUMN_WIDTH=96
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_func_synth/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/project_tb_func_synth/xsimk -simmode gui -wdb project_tb_func_synth.wdb -simrunnum 0 -socket 33153
+Design successfully loaded
+Design Loading Memory Usage: 199644 KB (Peak: 199644 KB)
+Design Loading CPU Usage: 710 ms
+Simulation completed
+Simulation Memory Usage: 288764 KB (Peak: 338912 KB)
+Simulation CPU Usage: 720 ms

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_timing_func_synth" "xil_defaultlib.project_tb_timing" "xil_defaultlib.glbl" -log "elaborate.log" 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  6507029321917424264  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_timing_func_synth xil_defaultlib.project_tb_timing xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/project_tb_timing_func_synth/xsimk\"   \"xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsim.version

@@ -0,0 +1 @@
+hjhoth

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=168
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109
+OBJECT_NAME_COLUMN_WIDTH=191
+OBJECT_VALUE_COLUMN_WIDTH=5823
+OBJECT_DATA_TYPE_COLUMN_WIDTH=96
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/project_tb_timing_func_synth/xsimkernel.log

@@ -0,0 +1,7 @@
+Running: xsim.dir/project_tb_timing_func_synth/xsimk -simmode gui -wdb project_tb_timing_func_synth.wdb -simrunnum 0 -socket 53731
+Design successfully loaded
+Design Loading Memory Usage: 199620 KB (Peak: 199620 KB)
+Design Loading CPU Usage: 700 ms
+Simulation completed
+Simulation Memory Usage: 288740 KB (Peak: 338888 KB)
+Simulation CPU Usage: 740 ms

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -0,0 +1,8 @@
+0.7
+2020.2
+Nov 14 2025
+12:36:23
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v,1781272095,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,,
+/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,,

progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir/xsim.version

@@ -0,0 +1 @@
+hjhoth