Initial commit
This commit is contained in:
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module project_reti_logiche
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INFO: [VRFC 10-311] analyzing module glbl
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#!/bin/bash -f
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# ****************************************************************************
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# Vivado (TM) v2025.2 (64-bit)
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#
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# Filename : compile.sh
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# Simulator : AMD Vivado Simulator
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# Description : Script for compiling the simulation design source files
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#
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# Generated by Vivado on Fri Jun 12 15:48:15 CEST 2026
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# usage: compile.sh
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#
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# ****************************************************************************
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export SIM_VER_XSIM=2025.2
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export GCC_VER_XSIM=9.3.0
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# catch pipeline exit status
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set -Eeuo pipefail
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# compile Verilog/System Verilog design sources
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echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj"
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xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log
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# compile VHDL design sources
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echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj"
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xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log
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echo "Waiting for jobs to finish..."
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echo "No pending jobs, compilation finished."
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@@ -0,0 +1,36 @@
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Vivado Simulator v2025.2
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log
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Using 8 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.numeric_std
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Compiling package vl.vl_types
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Compiling module xil_defaultlib.glbl
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.FDPE_default
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Compiling module unisims_ver.FDCE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.BUFG
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Compiling module unisims_ver.IBUF
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Compiling module unisims_ver.OBUF
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Compiling module xil_defaultlib.project_reti_logiche
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Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
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Built simulation snapshot project_tb_edge_func_synth
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@@ -0,0 +1,26 @@
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#!/bin/bash -f
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# ****************************************************************************
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# Vivado (TM) v2025.2 (64-bit)
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#
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# Filename : elaborate.sh
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# Simulator : AMD Vivado Simulator
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# Description : Script for elaborating the compiled design
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#
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# Generated by Vivado on Fri Jun 12 15:48:17 CEST 2026
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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#
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# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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#
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# usage: elaborate.sh
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#
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# ****************************************************************************
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export SIM_VER_XSIM=2025.2
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export GCC_VER_XSIM=9.3.0
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# catch pipeline exit status
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set -Eeuo pipefail
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# elaborate design
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echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log"
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xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl -log elaborate.log
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@@ -0,0 +1,24 @@
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#
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# An unexpected error has occurred (11) Segmentation fault
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#
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Stack:
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/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(+0xe7195c) [0x7ff9b8e7195c]
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/opt/vivado/2025.2/Vivado/tps/lnx64/jre21.0.5_11/lib//server/libjvm.so(JVM_handle_linux_signal+0x23e) [0x7ff9b8e7242e]
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/usr/lib/libc.so.6(+0x3e2d0) [0x7ff9f884d2d0]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x34ebcb) [0x7ff9c5d4ebcb]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataObjMgr::createDrawingBTree(std::vector<SimBridge::IDataObj const*, std::allocator<SimBridge::IDataObj const*> > const&, ISIM::IGuiStatus*, bool)+0x211) [0x7ff9c5d4f1e1]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SimBridge::DataReader::getTransitions(SimBridge::IDataObj const*, long long, long long, long long, SimBridge::ValueFormat const&, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0x6f) [0x7ff9c5d6a6ff]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::ModelImp::getTransitions(SimBridge::IDataObj const*, SG_Model::IDatabase*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0xb7) [0x7ff9c5dc2cd7]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::Model::getTransitions(SG_Model::WVDataObject const*, long long, long long, long long, SimBridge::ValueFormat const&, bool, std::vector<SimBridge::Transition, std::allocator<SimBridge::Transition> >&) const+0x128) [0x7ff9c5dc60c8]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(+0x3a9596) [0x7ff9c5da9596]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(SG_Model::WaveformRender::render(SG_Model::WVDataObject const&)+0x294) [0x7ff9c5da3f64]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::drawWaveform(SG_Model::WVDataObject const*, int, int)+0x2cf) [0x7ff9c5df1b2f]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::WaveformTraverser::handleItemSize(WaveViewer::WVTreeWVObjectModel::ITraverseHandler::TraverseItem const&)+0x54) [0x7ff9c5df1ca4]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x1a7) [0x7ff9c5c391a7]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(SG_Model::WVDataObject const*, WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int, int&, int&) const+0x22c) [0x7ff9c5c3922c]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVTreeWVObjectModel::traverseYRange(WaveViewer::WVTreeWVObjectModel::ITraverseHandler&, int, int) const+0x58) [0x7ff9c5c3a8e8]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WaveViewer::WVWaveformPanel::getGraphics(HDGDStringStream&, long&)+0x3de) [0x7ff9c5df137e]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutiveImp::getGraphicsDataSize()+0x9a) [0x7ff9c5e037da]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(WVExecutive::getGraphicsDataSize()+0x12) [0x7ff9c5e03c62]
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/opt/vivado/2025.2/Vivado/lib/lnx64.o/libxv_wavedata.so(Java_ui_views_waveform_waveformi_WVExecutive_1getGraphicsDataSize+0x1c) [0x7ff9c5c050dc]
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[0x7ff9a937ac6a]
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@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run all
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File diff suppressed because it is too large
Load Diff
Binary file not shown.
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# compile vhdl design source files
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vhdl xil_defaultlib \
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"../../../../../progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" \
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# Do not sort compile order
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nosort
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@@ -0,0 +1,6 @@
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# compile verilog/system verilog design source files
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verilog xil_defaultlib --include "../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \
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"project_tb_edge_func_synth.v" \
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# Do not sort compile order
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nosort
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File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,11 @@
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set curr_wave [current_wave_config]
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if { [string length $curr_wave] == 0 } {
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if { [llength [get_objects]] > 0} {
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add_wave /
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set_property needs_save false [current_wave_config]
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} else {
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send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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}
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}
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run 1000ns
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File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -0,0 +1,152 @@
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Time resolution is 1 ps
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Note: === GRUPPO 0: Reset ===
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Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.0 OK: reset base
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Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.1 OK: reset asincrono durante operazione
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Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 1: Inserimento ===
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Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.0 OK: insert in lista vuota
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Time: 3670100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.1 OK: insert con priorità massima in testa
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Time: 6010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.2 OK: insert con priorità minima in fondo
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Time: 8230100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali
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Time: 10450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo
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Time: 12950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.5 OK: insert con ID duplicato ignorato
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Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 2: Rimozione ===
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Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0
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Time: 16990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto
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Time: 18930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato
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Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 3: Decremento priorità ===
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Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.0 OK: decremento su lista vuota
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Time: 23130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.1 OK: saturazione a priorità 3
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Time: 25350100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica
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Time: 27870100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)
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||||
Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: === GRUPPO 4: Svuota lista ===
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||||
Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 4.0 OK: svuota lista popolata
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||||
Time: 33050100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 4.1 OK: svuota lista già vuota
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||||
Time: 34730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0
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||||
Time: 36690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto
|
||||
Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: === GRUPPO 5: Sequenze composite ===
|
||||
Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto
|
||||
Time: 41490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 5.1 OK: ordinamento completo con priorità miste
|
||||
Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 6: Rimozione multipla e ordinamento ===
|
||||
Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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||||
Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota
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||||
Time: 48310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1
|
||||
Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 7: Decremento ripetuto ===
|
||||
Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3
|
||||
Time: 53430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente
|
||||
Time: 57010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 7.1 OK: decremento su lista con un solo task
|
||||
Time: 59330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota
|
||||
Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 8: Insert dopo rimozione e casi limite ===
|
||||
Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto
|
||||
Time: 64950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato
|
||||
Time: 67830100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato
|
||||
Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 9: o_task_id per OP diverso da 01 ===
|
||||
Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1
|
||||
Time: 72490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1
|
||||
Time: 74450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1
|
||||
Time: 76330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1
|
||||
Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 10: Protocollo, reset avanzato, stress ===
|
||||
Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset
|
||||
Time: 79750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert)
|
||||
Time: 92030100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato
|
||||
Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 11: Insert con ID=0 ===
|
||||
Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato
|
||||
Time: 96290100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato
|
||||
Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 12: Capacita' massima 63 task ===
|
||||
Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata
|
||||
Time: 231450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati
|
||||
Time: 235970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 12.2 OK: drain di 63 task nell'ordine atteso
|
||||
Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 13: Stale memory e duplicati ai bordi ===
|
||||
Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 13.0 OK: re-insert di ID appena rimosso
|
||||
Time: 365710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 13.1 OK: duplicato in prima posizione ignorato
|
||||
Time: 368130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 13.2 OK: duplicato in ultima posizione ignorato
|
||||
Time: 368250100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 13.3 OK: re-insert stesso ID dopo clear
|
||||
Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 14: Reset asincrono avanzato ===
|
||||
Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 14.0 OK: reset a meta' shift di OP=01
|
||||
Time: 373150100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 14.1 OK: reset durante la scrittura del count
|
||||
Time: 375930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 14.2 OK: reset durante OP=00
|
||||
Time: 378470100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 14.3 OK: reset mentre DONE=1
|
||||
Time: 380550100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 14.4 OK: reset corto non allineato
|
||||
Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: === GRUPPO 15: START lento dopo DONE=1 ===
|
||||
Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 15.0 OK: nessun doppio pop con START lento
|
||||
Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 15.1 OK: nessun doppio age con START lento
|
||||
Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Note: Test 15.2 OK: insert con START tenuto 2 cicli extra
|
||||
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Failure: ======================================
|
||||
Tutti i test edge case sono PASSATI
|
||||
======================================
|
||||
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616
|
||||
Note: === GRUPPO 0: Reset ===
|
||||
Time: 389890 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
Failure: FAIL [0.0 reset-addr0] addr=0 expected=0x0 actual=0x1
|
||||
Time: 390040 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
|
||||
$finish called at time : 390040 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 420
|
||||
INFO: xsimkernel Simulation Memory Usage: 294496 KB (Peak: 343308 KB), Simulation CPU Usage: 890 ms
|
||||
@@ -0,0 +1,26 @@
|
||||
#!/bin/bash -f
|
||||
# ****************************************************************************
|
||||
# Vivado (TM) v2025.2 (64-bit)
|
||||
#
|
||||
# Filename : simulate.sh
|
||||
# Simulator : AMD Vivado Simulator
|
||||
# Description : Script for simulating the design by launching the simulator
|
||||
#
|
||||
# Generated by Vivado on Fri Jun 12 15:48:20 CEST 2026
|
||||
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
||||
#
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: simulate.sh
|
||||
#
|
||||
# ****************************************************************************
|
||||
export SIM_VER_XSIM=2025.2
|
||||
export GCC_VER_XSIM=9.3.0
|
||||
|
||||
# catch pipeline exit status
|
||||
set -Eeuo pipefail
|
||||
# simulate design
|
||||
echo "xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log"
|
||||
xsim project_tb_edge_func_synth -key {Post-Synthesis:sim_1:Functional:project_tb_edge} -tclbatch project_tb_edge.tcl -view /home/aleandro/Projects/progetto_reti_logiche/project_tb_edge_behav1.wcfg -log simulate.log
|
||||
|
||||
Binary file not shown.
+1
@@ -0,0 +1 @@
|
||||
--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_edge_func_synth" "xil_defaultlib.project_tb_edge" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
+1
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
BIN
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+479
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BIN
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BIN
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+12
@@ -0,0 +1,12 @@
|
||||
|
||||
{
|
||||
crc : 1042013717637638161 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_edge_func_synth xil_defaultlib.project_tb_edge xil_defaultlib.glbl" ,
|
||||
buildDate : "Nov 14 2025" ,
|
||||
buildTime : "12:36:23" ,
|
||||
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_func_synth/xsimk\" \"xsim.dir/project_tb_edge_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
BIN
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BIN
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BIN
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+1
@@ -0,0 +1 @@
|
||||
hjhoth
|
||||
BIN
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+50
@@ -0,0 +1,50 @@
|
||||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=512
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=2147483647
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
INPUT_PROTOINST_FILTER=true
|
||||
OUTPUT_PROTOINST_FILTER=true
|
||||
INOUT_PROTOINST_FILTER=true
|
||||
INTERNAL_PROTOINST_FILTER=true
|
||||
CONSTANT_PROTOINST_FILTER=true
|
||||
VARIABLE_PROTOINST_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=156
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109
|
||||
OBJECT_NAME_COLUMN_WIDTH=191
|
||||
OBJECT_VALUE_COLUMN_WIDTH=1024
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=76
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
PROTO_VALUE_COLUMN_WIDTH=0
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
Executable
BIN
Binary file not shown.
+7
@@ -0,0 +1,7 @@
|
||||
Running: xsim.dir/project_tb_edge_func_synth/xsimk -simmode gui -wdb project_tb_edge_func_synth.wdb -simrunnum 0 -socket 41063
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 199732 KB (Peak: 199732 KB)
|
||||
Design Loading CPU Usage: 700 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 294496 KB (Peak: 343308 KB)
|
||||
Simulation CPU Usage: 890 ms
|
||||
+1
@@ -0,0 +1 @@
|
||||
--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_func_synth" "xil_defaultlib.project_tb" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
+1
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
BIN
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+478
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BIN
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BIN
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BIN
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BIN
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+12
@@ -0,0 +1,12 @@
|
||||
|
||||
{
|
||||
crc : 17879923451979115244 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_func_synth xil_defaultlib.project_tb xil_defaultlib.glbl" ,
|
||||
buildDate : "Nov 14 2025" ,
|
||||
buildTime : "12:36:23" ,
|
||||
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_func_synth/xsimk\" \"xsim.dir/project_tb_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
BIN
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+1
@@ -0,0 +1 @@
|
||||
hjhoth
|
||||
BIN
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+50
@@ -0,0 +1,50 @@
|
||||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=512
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=2147483647
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
INPUT_PROTOINST_FILTER=true
|
||||
OUTPUT_PROTOINST_FILTER=true
|
||||
INOUT_PROTOINST_FILTER=true
|
||||
INTERNAL_PROTOINST_FILTER=true
|
||||
CONSTANT_PROTOINST_FILTER=true
|
||||
VARIABLE_PROTOINST_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=75
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
|
||||
OBJECT_NAME_COLUMN_WIDTH=240
|
||||
OBJECT_VALUE_COLUMN_WIDTH=5823
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=96
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
PROTO_VALUE_COLUMN_WIDTH=0
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
BIN
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+7
@@ -0,0 +1,7 @@
|
||||
Running: xsim.dir/project_tb_func_synth/xsimk -simmode gui -wdb project_tb_func_synth.wdb -simrunnum 0 -socket 33153
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 199644 KB (Peak: 199644 KB)
|
||||
Design Loading CPU Usage: 710 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 288764 KB (Peak: 338912 KB)
|
||||
Simulation CPU Usage: 720 ms
|
||||
+1
@@ -0,0 +1 @@
|
||||
--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "secureip" --snapshot "project_tb_timing_func_synth" "xil_defaultlib.project_tb_timing" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
+1
@@ -0,0 +1 @@
|
||||
Breakpoint File Version 1.0
|
||||
BIN
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+478
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+12
@@ -0,0 +1,12 @@
|
||||
|
||||
{
|
||||
crc : 6507029321917424264 ,
|
||||
ccp_crc : 0 ,
|
||||
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L secureip --snapshot project_tb_timing_func_synth xil_defaultlib.project_tb_timing xil_defaultlib.glbl" ,
|
||||
buildDate : "Nov 14 2025" ,
|
||||
buildTime : "12:36:23" ,
|
||||
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_timing_func_synth/xsimk\" \"xsim.dir/project_tb_timing_func_synth/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_func_synth/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
|
||||
aggregate_nets :
|
||||
[
|
||||
]
|
||||
}
|
||||
BIN
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BIN
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+1
@@ -0,0 +1 @@
|
||||
hjhoth
|
||||
BIN
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+50
@@ -0,0 +1,50 @@
|
||||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=1024
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=65536
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
INPUT_PROTOINST_FILTER=true
|
||||
OUTPUT_PROTOINST_FILTER=true
|
||||
INOUT_PROTOINST_FILTER=true
|
||||
INTERNAL_PROTOINST_FILTER=true
|
||||
CONSTANT_PROTOINST_FILTER=true
|
||||
VARIABLE_PROTOINST_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=168
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=109
|
||||
OBJECT_NAME_COLUMN_WIDTH=191
|
||||
OBJECT_VALUE_COLUMN_WIDTH=5823
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=96
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=75
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
|
||||
PROTO_NAME_COLUMN_WIDTH=0
|
||||
PROTO_VALUE_COLUMN_WIDTH=0
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
Executable
BIN
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+7
@@ -0,0 +1,7 @@
|
||||
Running: xsim.dir/project_tb_timing_func_synth/xsimk -simmode gui -wdb project_tb_timing_func_synth.wdb -simrunnum 0 -socket 53731
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 199620 KB (Peak: 199620 KB)
|
||||
Design Loading CPU Usage: 700 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 288740 KB (Peak: 338888 KB)
|
||||
Simulation CPU Usage: 740 ms
|
||||
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BIN
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BIN
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+8
@@ -0,0 +1,8 @@
|
||||
0.7
|
||||
2020.2
|
||||
Nov 14 2025
|
||||
12:36:23
|
||||
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v,1781272095,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
|
||||
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
|
||||
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,,
|
||||
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,,
|
||||
@@ -0,0 +1 @@
|
||||
hjhoth
|
||||
@@ -0,0 +1 @@
|
||||
xil_defaultlib=xsim.dir/xil_defaultlib
|
||||
@@ -0,0 +1,4 @@
|
||||
|
||||
|
||||
|
||||
End Record
|
||||
@@ -0,0 +1,3 @@
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module project_reti_logiche
|
||||
INFO: [VRFC 10-311] analyzing module glbl
|
||||
Binary file not shown.
Reference in New Issue
Block a user