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aleandro
2026-06-12 20:37:03 +02:00
commit 259f6d5803
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progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_reti_logiche_behav/Compile_Options.txt
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_reti_logiche_behav" "xil_defaultlib.project_reti_logiche" -log "elaborate.log"
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_26(char*, char *);
IKI_DLLESPEC extern void execute_27(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[4] = {(funcp)execute_26, (funcp)execute_27, (funcp)transaction_0, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 4;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc", (void **)funcTab, 4);
iki_vhdl_file_variable_register(dp + 9192);
iki_vhdl_file_variable_register(dp + 9248);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_reti_logiche_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_reti_logiche_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_reti_logiche_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 13885744666178239796 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_reti_logiche_behav xil_defaultlib.project_reti_logiche" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_reti_logiche_behav/xsimk\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_reti_logiche_behav/obj/xsim_1.lnx64.o\" -L\"/opt/vivado/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/vivado/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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hjhoth
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[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=173
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=159
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=84
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_reti_logiche_behav/xsimk -simmode gui -wdb project_reti_logiche_behav.wdb -simrunnum 0 -socket 60931
Design successfully loaded
Design Loading Memory Usage: 196484 KB (Peak: 196604 KB)
Design Loading CPU Usage: 750 ms
Simulation completed
Simulation Memory Usage: 278220 KB (Peak: 335752 KB)
Simulation CPU Usage: 770 ms
progetto_reti_logiche.sim/sim_1/behav/xsim/xsim.dir/project_tb_behav/Compile_Options.txt
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_behav" "xil_defaultlib.project_tb" -log "elaborate.log"
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 9;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_behav/xsim.reloc", (void **)funcTab, 9);
iki_vhdl_file_variable_register(dp + 562288);
iki_vhdl_file_variable_register(dp + 562344);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 7473175962787144638 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_behav xil_defaultlib.project_tb" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_behav/xsimk\" \"xsim.dir/project_tb_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=120
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=181
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_tb_behav/xsimk -simmode gui -wdb project_tb_behav.wdb -simrunnum 0 -socket 39125
Design successfully loaded
Design Loading Memory Usage: 198324 KB (Peak: 198324 KB)
Design Loading CPU Usage: 690 ms
Simulation completed
Simulation Memory Usage: 291512 KB (Peak: 337592 KB)
Simulation CPU Usage: 700 ms
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_edge_behav" "xil_defaultlib.project_tb_edge" -log "elaborate.log"
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_40(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[10] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 10;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc", (void **)funcTab, 10);
iki_vhdl_file_variable_register(dp + 535048);
iki_vhdl_file_variable_register(dp + 535104);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_edge_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_edge_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_edge_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_edge_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 5620043674301555198 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_edge_behav/xsimk\" \"xsim.dir/project_tb_edge_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_edge_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=156
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=251
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=191
OBJECT_VALUE_COLUMN_WIDTH=1024
OBJECT_DATA_TYPE_COLUMN_WIDTH=76
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_tb_edge_behav/xsimk -simmode gui -wdb project_tb_edge_behav.wdb -simrunnum 0 -socket 59621
Design successfully loaded
Design Loading Memory Usage: 198404 KB (Peak: 198404 KB)
Design Loading CPU Usage: 680 ms
Simulation completed
Simulation Memory Usage: 291592 KB (Peak: 337672 KB)
Simulation CPU Usage: 710 ms
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--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "project_tb_timing_behav" "xil_defaultlib.project_tb_timing" -log "elaborate.log"
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Breakpoint File Version 1.0
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_36(char*, char *);
IKI_DLLESPEC extern void execute_37(char*, char *);
IKI_DLLESPEC extern void execute_38(char*, char *);
IKI_DLLESPEC extern void execute_39(char*, char *);
IKI_DLLESPEC extern void execute_34(char*, char *);
IKI_DLLESPEC extern void execute_35(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_3(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[9] = {(funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_39, (funcp)execute_34, (funcp)execute_35, (funcp)transaction_0, (funcp)transaction_3, (funcp)vhdl_transfunc_eventcallback};
const int NumRelocateId= 9;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc", (void **)funcTab, 9);
iki_vhdl_file_variable_register(dp + 534752);
iki_vhdl_file_variable_register(dp + 534808);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/project_tb_timing_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/project_tb_timing_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/project_tb_timing_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/project_tb_timing_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}
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{
crc : 6692423544243212696 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_timing_behav xil_defaultlib.project_tb_timing" ,
buildDate : "Nov 14 2025" ,
buildTime : "12:36:23" ,
linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/project_tb_timing_behav/xsimk\" \"xsim.dir/project_tb_timing_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/project_tb_timing_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" ,
aggregate_nets :
[
]
}
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[General]
ARRAY_DISPLAY_LIMIT=512
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=2147483647
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=168
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=202
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=91
OBJECT_NAME_COLUMN_WIDTH=191
OBJECT_VALUE_COLUMN_WIDTH=5823
OBJECT_DATA_TYPE_COLUMN_WIDTH=96
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=75
LOCAL_NAME_COLUMN_WIDTH=75
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
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Running: xsim.dir/project_tb_timing_behav/xsimk -simmode gui -wdb project_tb_timing_behav.wdb -simrunnum 0 -socket 42147
Design successfully loaded
Design Loading Memory Usage: 198300 KB (Peak: 198300 KB)
Design Loading CPU Usage: 700 ms
Simulation completed
Simulation Memory Usage: 291488 KB (Peak: 337568 KB)
Simulation CPU Usage: 720 ms
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0.7
2020.2
Nov 14 2025
12:36:23
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_timing.vhd,1781181949,vhdl,,,,project_tb_timing,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/tb2526.vhd,1771761503,vhdl,,,,project_tb,,,,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd,1781272532,vhdl,,,,project_reti_logiche,,,,,,,,