Aleandro/Progetto-reti-logiche
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aleandro
2026-06-12 20:37:03 +02:00
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progetto_reti_logiche.sim/sim_1/behav/xsim/elaborate.sh
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#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename : elaborate.sh
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Fri Jun 12 15:55:44 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: elaborate.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0
# catch pipeline exit status
set -Eeuo pipefail
# elaborate design
echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log"
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log