Initial commit

2026-06-12 20:37:03 +02:00
commit 259f6d5803
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+Vivado Simulator v2025.2
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+Running: /opt/Xilinx/2025.2/Vivado/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot project_tb_edge_behav xil_defaultlib.project_tb_edge -log elaborate.log 
+Using 8 slave threads.
+Starting static elaboration
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture fsm of entity xil_defaultlib.project_reti_logiche [project_reti_logiche_default]
+Compiling architecture project_tb_edge_arch of entity xil_defaultlib.project_tb_edge
+Built simulation snapshot project_tb_edge_behav