Aleandro/Progetto-reti-logiche
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aleandro
2026-06-12 20:37:03 +02:00
commit 259f6d5803
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progetto_reti_logiche.runs/synth_1/gen_run.xml
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a200tfbg484-1" LaunchTime="1781268754" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/project_reti_logiche.dcp">
<File Type="RDS-DCP" Name="project_reti_logiche.dcp"/>
<File Type="RDS-RDS" Name="project_reti_logiche.vds"/>
<File Type="REPORTS-TCL" Name="project_reti_logiche_reports.tcl"/>
<File Type="PA-TCL" Name="project_reti_logiche.tcl"/>
<File Type="RDS-UTIL" Name="project_reti_logiche_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="project_reti_logiche_utilization_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/progetto_reti_logiche.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="project_reti_logiche"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/project_reti_logiche.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>