Initial commit
This commit is contained in:
@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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<Process Command="vivado" Owner="aleandro" Host="cachyos-x8664" Pid="33434" HostCore="20" HostMemory="16115628">
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</Process>
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</ProcessHandle>
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+270
@@ -0,0 +1,270 @@
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//
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// Vivado(TM)
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||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
//
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||||
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||||
// GLOBAL VARIABLES
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||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
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var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
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||||
var ISERunDir = "";
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var ISELogFile = "runme.log";
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var ISELogFileStr = null;
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var ISELogEcho = true;
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var ISEOldVersionWSH = false;
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||||
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||||
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||||
// BOOTSTRAP
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ISEInit();
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//
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// ISE FUNCTIONS
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||||
//
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function ISEInit() {
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// 1. RUN DIR setup
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var ISEScrFP = WScript.ScriptFullName;
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var ISEScrN = WScript.ScriptName;
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ISERunDir =
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ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
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// 2. LOG file setup
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ISELogFileStr = ISEOpenFile( ISELogFile );
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// 3. LOG echo?
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var ISEScriptArgs = WScript.Arguments;
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for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
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if ( ISEScriptArgs(loopi) == "-quiet" ) {
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ISELogEcho = false;
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break;
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}
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}
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// 4. WSH version check
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var ISEOptimalVersionWSH = 5.6;
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var ISECurrentVersionWSH = WScript.Version;
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if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
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ISEStdErr( "" );
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ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
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ISEOptimalVersionWSH + " or higher. Downloads" );
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ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
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ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
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ISEStdErr( "" );
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ISEOldVersionWSH = true;
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}
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}
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function ISEStep( ISEProg, ISEArgs ) {
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// CHECK for a STOP FILE
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if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
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ISEStdErr( "" );
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ISEStdErr( "*** Halting run - EA reset detected ***" );
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ISEStdErr( "" );
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WScript.Quit( 1 );
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}
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// WRITE STEP HEADER to LOG
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ISEStdOut( "" );
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ISEStdOut( "*** Running " + ISEProg );
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ISEStdOut( " with args " + ISEArgs );
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ISEStdOut( "" );
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// LAUNCH!
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var ISEExitCode = ISEExec( ISEProg, ISEArgs );
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if ( ISEExitCode != 0 ) {
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WScript.Quit( ISEExitCode );
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}
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||||
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}
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||||
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||||
function ISEExec( ISEProg, ISEArgs ) {
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||||
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||||
var ISEStep = ISEProg;
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if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
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ISEProg += ".bat";
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}
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var ISECmdLine = ISEProg + " " + ISEArgs;
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var ISEExitCode = 1;
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if ( ISEOldVersionWSH ) { // WSH 5.1
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// BEGIN file creation
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ISETouchFile( ISEStep, "begin" );
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// LAUNCH!
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ISELogFileStr.Close();
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ISECmdLine =
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"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
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ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
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ISELogFileStr = ISEOpenFile( ISELogFile );
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} else { // WSH 5.6
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// LAUNCH!
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||||
ISEShell.CurrentDirectory = ISERunDir;
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// Redirect STDERR to STDOUT
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ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
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var ISEProcess = ISEShell.Exec( ISECmdLine );
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// BEGIN file creation
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||||
var wbemFlagReturnImmediately = 0x10;
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var wbemFlagForwardOnly = 0x20;
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var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
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var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
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var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
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||||
var NOC = 0;
|
||||
var NOLP = 0;
|
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var TPM = 0;
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var cpuInfos = new Enumerator(processor);
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for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
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var cpuInfo = cpuInfos.item();
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NOC += cpuInfo.NumberOfCores;
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NOLP += cpuInfo.NumberOfLogicalProcessors;
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}
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var csInfos = new Enumerator(computerSystem);
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for(;!csInfos.atEnd(); csInfos.moveNext()) {
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var csInfo = csInfos.item();
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TPM += csInfo.TotalPhysicalMemory;
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}
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var ISEHOSTCORE = NOLP
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var ISEMEMTOTAL = TPM
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var ISENetwork = WScript.CreateObject( "WScript.Network" );
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var ISEHost = ISENetwork.ComputerName;
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var ISEUser = ISENetwork.UserName;
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var ISEPid = ISEProcess.ProcessID;
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var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
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ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
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ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
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ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
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"\" Owner=\"" + ISEUser +
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"\" Host=\"" + ISEHost +
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"\" Pid=\"" + ISEPid +
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"\" HostCore=\"" + ISEHOSTCORE +
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"\" HostMemory=\"" + ISEMEMTOTAL +
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"\">" );
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ISEBeginFile.WriteLine( " </Process>" );
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ISEBeginFile.WriteLine( "</ProcessHandle>" );
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ISEBeginFile.Close();
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var ISEOutStr = ISEProcess.StdOut;
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var ISEErrStr = ISEProcess.StdErr;
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// WAIT for ISEStep to finish
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||||
while ( ISEProcess.Status == 0 ) {
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||||
// dump stdout then stderr - feels a little arbitrary
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while ( !ISEOutStr.AtEndOfStream ) {
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ISEStdOut( ISEOutStr.ReadLine() );
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}
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||||
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||||
WScript.Sleep( 100 );
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||||
}
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||||
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ISEExitCode = ISEProcess.ExitCode;
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||||
}
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||||
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ISELogFileStr.Close();
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||||
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||||
// END/ERROR file creation
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||||
if ( ISEExitCode != 0 ) {
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||||
ISETouchFile( ISEStep, "error" );
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||||
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||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
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||||
}
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||||
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||||
return ISEExitCode;
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||||
}
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||||
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||||
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||||
//
|
||||
// UTILITIES
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||||
//
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||||
function ISEStdOut( ISELine ) {
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||||
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||||
ISELogFileStr.WriteLine( ISELine );
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||||
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||||
if ( ISELogEcho ) {
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||||
WScript.StdOut.WriteLine( ISELine );
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||||
}
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||||
}
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||||
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||||
function ISEStdErr( ISELine ) {
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||||
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ISELogFileStr.WriteLine( ISELine );
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||||
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||||
if ( ISELogEcho ) {
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||||
WScript.StdErr.WriteLine( ISELine );
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||||
}
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||||
}
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||||
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||||
function ISETouchFile( ISERoot, ISEStatus ) {
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var ISETFile =
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ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
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||||
ISETFile.Close();
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}
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||||
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function ISEOpenFile( ISEFilename ) {
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// This function has been updated to deal with a problem seen in CR #870871.
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// In that case the user runs a script that runs impl_1, and then turns around
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// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
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// the same directory, which means we may hit some of the same files, and in
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// particular, we will open the runme.log file. Even though this script closes
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// the file (now), we see cases where a subsequent attempt to open the file
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||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
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// play? In any case, we try to work around this by first waiting if the file
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// is already there for an arbitrary 5 seconds. Then we use a try-catch block
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// and try to open the file 10 times with a one second delay after each attempt.
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||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
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||||
// If there is an unrecognized exception when trying to open the file, we output
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// an error message and write details to an exception.log file.
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||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
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||||
if (ISEFileSys.FileExists(ISEFullPath)) {
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||||
// File is already there. This could be a problem. Wait in case it is still in use.
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WScript.Sleep(5000);
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||||
}
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||||
var i;
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for (i = 0; i < 10; ++i) {
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||||
try {
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return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
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||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
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||||
if (error_code == 52) { // 52 is bad file name or number.
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||||
// Wait a second and try again.
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||||
WScript.Sleep(1000);
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||||
continue;
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||||
} else {
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||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
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||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
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||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
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||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
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||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
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||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
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||||
+85
@@ -0,0 +1,85 @@
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||||
#!/bin/bash
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||||
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||||
#
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||||
# Vivado(TM)
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||||
# ISEWrap.sh: Vivado Runs Script for UNIX
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||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
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||||
shift
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||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
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||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
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||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
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||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7a200tfbg484-1" LaunchTime="1781268754" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/project_reti_logiche.dcp">
|
||||
<File Type="RDS-DCP" Name="project_reti_logiche.dcp"/>
|
||||
<File Type="RDS-RDS" Name="project_reti_logiche.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="project_reti_logiche_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="project_reti_logiche.tcl"/>
|
||||
<File Type="RDS-UTIL" Name="project_reti_logiche_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="project_reti_logiche_utilization_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/progetto_reti_logiche.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="project_reti_logiche"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/project_reti_logiche.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
||||
@@ -0,0 +1 @@
|
||||
 6No compile time benefit to using incremental synthesis
|
||||
@@ -0,0 +1,31 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:333536:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3630353136636534303563393461656261623931373435306630653133333835:506172656e742050412070726f6a656374204944:00
|
||||
eof:2983737119
|
||||
Binary file not shown.
@@ -0,0 +1,107 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
OPTRACE "synth_1" START { ROLLUP_AUTO }
|
||||
set_param general.usePosixSpawnForFork 1
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7a200tfbg484-1
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/wt [current_project]
|
||||
set_property parent.project_path /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_vhdl -library xil_defaultlib /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top project_reti_logiche -part xc7a200tfbg484-1
|
||||
OPTRACE "synth_design" END { }
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef project_reti_logiche.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
generate_parallel_reports -reports { "report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb" }
|
||||
OPTRACE "synth reports" END { }
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "synth_1" END { }
|
||||
@@ -0,0 +1,257 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2025.2 (64-bit)
|
||||
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
||||
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
|
||||
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
|
||||
# Start of session at: Fri Jun 12 14:52:36 2026
|
||||
# Process ID : 33507
|
||||
# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1
|
||||
# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
||||
# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds
|
||||
# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou
|
||||
# Running On : cachyos-x8664
|
||||
# Platform : cachyos
|
||||
# Operating System : CachyOS
|
||||
# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F
|
||||
# CPU Frequency : 4313.234 MHz
|
||||
# CPU Physical cores : 12
|
||||
# CPU Logical cores : 20
|
||||
# Host memory : 16502 MB
|
||||
# Swap memory : 16501 MB
|
||||
# Total Virtual : 33003 MB
|
||||
# Available Virtual : 19387 MB
|
||||
#-----------------------------------------------------------
|
||||
source project_reti_logiche.tcl -notrace
|
||||
Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp
|
||||
INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis
|
||||
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
||||
Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
|
||||
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 33546
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
||||
INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151]
|
||||
INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a200tfbg484-1
|
||||
INFO: [Device 21-403] Loading part xc7a200tfbg484-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche'
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
s_reset | 000000000000000000000001 | 00001
|
||||
s_done | 000000000000000000000010 | 00010
|
||||
s_idle | 000000000000000000000100 | 00000
|
||||
s_00_read | 000000000000000000001000 | 00011
|
||||
s_00_wait | 000000000000000000010000 | 00100
|
||||
s_00_check | 000000000000000000100000 | 00101
|
||||
s_00_go_next | 000000000000000001000000 | 00110
|
||||
s_01_check_number | 000000000000000010000000 | 00111
|
||||
s_01_wait | 000000000000000100000000 | 01000
|
||||
s_01_write | 000000000000001000000000 | 01001
|
||||
s_01_check_end | 000000000000010000000000 | 01010
|
||||
s_01_wait_for_count | 000000000000100000000000 | 01101
|
||||
s_01_copy | 000000000001000000000000 | 01011
|
||||
s_01_go_next | 000000000010000000000000 | 01100
|
||||
s_10_place_at_start | 000000000100000000000000 | 01110
|
||||
s_10_wait_for_check | 000000001000000000000000 | 01111
|
||||
s_10_check_id | 000000010000000000000000 | 10000
|
||||
s_10_wait | 000000100000000000000000 | 10001
|
||||
s_10_compare | 000001000000000000000000 | 10010
|
||||
s_10_update_count | 000010000000000000000000 | 10100
|
||||
s_10_wait_for_count | 000100000000000000000000 | 10101
|
||||
s_10_go_next | 001000000000000000000000 | 10011
|
||||
s_11_update_count | 010000000000000000000000 | 10110
|
||||
s_11_wait_for_count | 100000000000000000000000 | 10111
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 16 Bit Adders := 4
|
||||
2 Input 9 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 3
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
6 Bit Registers := 2
|
||||
1 Bit Registers := 3
|
||||
+---Muxes :
|
||||
24 Input 24 Bit Muxes := 1
|
||||
4 Input 24 Bit Muxes := 1
|
||||
2 Input 24 Bit Muxes := 7
|
||||
2 Input 16 Bit Muxes := 3
|
||||
24 Input 16 Bit Muxes := 1
|
||||
2 Input 8 Bit Muxes := 4
|
||||
24 Input 8 Bit Muxes := 2
|
||||
2 Input 6 Bit Muxes := 1
|
||||
24 Input 6 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 1
|
||||
24 Input 1 Bit Muxes := 6
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 740 (col length:100)
|
||||
BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 18|
|
||||
|3 |LUT1 | 34|
|
||||
|4 |LUT2 | 16|
|
||||
|5 |LUT3 | 25|
|
||||
|6 |LUT4 | 44|
|
||||
|7 |LUT5 | 22|
|
||||
|8 |LUT6 | 78|
|
||||
|9 |FDCE | 25|
|
||||
|10 |FDPE | 2|
|
||||
|11 |FDRE | 44|
|
||||
|12 |IBUF | 21|
|
||||
|13 |OBUF | 33|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 363|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463
|
||||
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 3d7ece1d
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374
|
||||
INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated.
|
||||
INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026...
|
||||
Binary file not shown.
@@ -0,0 +1,188 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
|
||||
| Date : Fri Jun 12 14:52:50 2026
|
||||
| Host : cachyos-x8664 running 64-bit CachyOS
|
||||
| Command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb
|
||||
| Design : project_reti_logiche
|
||||
| Device : xc7a200tfbg484-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice LUTs* | 181 | 0 | 0 | 134600 | 0.13 |
|
||||
| LUT as Logic | 181 | 0 | 0 | 134600 | 0.13 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 46200 | 0.00 |
|
||||
| Slice Registers | 71 | 0 | 0 | 269200 | 0.03 |
|
||||
| Register as Flip Flop | 71 | 0 | 0 | 269200 | 0.03 |
|
||||
| Register as Latch | 0 | 0 | 0 | 269200 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 0 | 67300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 0 | 33650 | 0.00 |
|
||||
| Unique Control Sets | 6 | | 0 | 33650 | 0.02 |
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
Warning! LUT value is adjusted to account for LUT combining.
|
||||
Warning! For any ECO changes, please run place_design if there are unplaced instances
|
||||
** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 2 | Yes | - | Set |
|
||||
| 25 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 44 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 365 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 365 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 730 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 740 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 54 | 0 | 0 | 285 | 18.95 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 274 | 0.00 |
|
||||
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 285 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 285 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT6 | 78 | LUT |
|
||||
| LUT4 | 44 | LUT |
|
||||
| FDRE | 44 | Flop & Latch |
|
||||
| LUT1 | 34 | LUT |
|
||||
| OBUF | 33 | IO |
|
||||
| LUT3 | 25 | LUT |
|
||||
| FDCE | 25 | Flop & Latch |
|
||||
| LUT5 | 22 | LUT |
|
||||
| IBUF | 21 | IO |
|
||||
| CARRY4 | 18 | CarryLogic |
|
||||
| LUT2 | 16 | LUT |
|
||||
| FDPE | 2 | Flop & Latch |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;";
|
||||
} else {
|
||||
PathVal = "/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64;/opt/Xilinx/2025.2/Vivado/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,247 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
||||
|
||||
|
||||
****** Vivado v2025.2 (64-bit)
|
||||
**** SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
||||
**** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
|
||||
**** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
|
||||
**** Start of session at: Fri Jun 12 14:52:36 2026
|
||||
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
source project_reti_logiche.tcl -notrace
|
||||
Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp
|
||||
INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis
|
||||
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
||||
Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
|
||||
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
|
||||
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 33546
|
||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
||||
INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151]
|
||||
INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7a200tfbg484-1
|
||||
INFO: [Device 21-403] Loading part xc7a200tfbg484-1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche'
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
s_reset | 000000000000000000000001 | 00001
|
||||
s_done | 000000000000000000000010 | 00010
|
||||
s_idle | 000000000000000000000100 | 00000
|
||||
s_00_read | 000000000000000000001000 | 00011
|
||||
s_00_wait | 000000000000000000010000 | 00100
|
||||
s_00_check | 000000000000000000100000 | 00101
|
||||
s_00_go_next | 000000000000000001000000 | 00110
|
||||
s_01_check_number | 000000000000000010000000 | 00111
|
||||
s_01_wait | 000000000000000100000000 | 01000
|
||||
s_01_write | 000000000000001000000000 | 01001
|
||||
s_01_check_end | 000000000000010000000000 | 01010
|
||||
s_01_wait_for_count | 000000000000100000000000 | 01101
|
||||
s_01_copy | 000000000001000000000000 | 01011
|
||||
s_01_go_next | 000000000010000000000000 | 01100
|
||||
s_10_place_at_start | 000000000100000000000000 | 01110
|
||||
s_10_wait_for_check | 000000001000000000000000 | 01111
|
||||
s_10_check_id | 000000010000000000000000 | 10000
|
||||
s_10_wait | 000000100000000000000000 | 10001
|
||||
s_10_compare | 000001000000000000000000 | 10010
|
||||
s_10_update_count | 000010000000000000000000 | 10100
|
||||
s_10_wait_for_count | 000100000000000000000000 | 10101
|
||||
s_10_go_next | 001000000000000000000000 | 10011
|
||||
s_11_update_count | 010000000000000000000000 | 10110
|
||||
s_11_wait_for_count | 100000000000000000000000 | 10111
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 16 Bit Adders := 4
|
||||
2 Input 9 Bit Adders := 1
|
||||
2 Input 8 Bit Adders := 3
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
8 Bit Registers := 2
|
||||
6 Bit Registers := 2
|
||||
1 Bit Registers := 3
|
||||
+---Muxes :
|
||||
24 Input 24 Bit Muxes := 1
|
||||
4 Input 24 Bit Muxes := 1
|
||||
2 Input 24 Bit Muxes := 7
|
||||
2 Input 16 Bit Muxes := 3
|
||||
24 Input 16 Bit Muxes := 1
|
||||
2 Input 8 Bit Muxes := 4
|
||||
24 Input 8 Bit Muxes := 2
|
||||
2 Input 6 Bit Muxes := 1
|
||||
24 Input 6 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 1
|
||||
24 Input 1 Bit Muxes := 6
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 740 (col length:100)
|
||||
BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-------+------+
|
||||
| |Cell |Count |
|
||||
+------+-------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |CARRY4 | 18|
|
||||
|3 |LUT1 | 34|
|
||||
|4 |LUT2 | 16|
|
||||
|5 |LUT3 | 25|
|
||||
|6 |LUT4 | 44|
|
||||
|7 |LUT5 | 22|
|
||||
|8 |LUT6 | 78|
|
||||
|9 |FDCE | 25|
|
||||
|10 |FDPE | 2|
|
||||
|11 |FDRE | 44|
|
||||
|12 |IBUF | 21|
|
||||
|13 |OBUF | 33|
|
||||
+------+-------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 363|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463
|
||||
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Synth Design complete | Checksum: 3d7ece1d
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374
|
||||
INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated.
|
||||
INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026...
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/bash
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin
|
||||
else
|
||||
PATH=/opt/Xilinx/2025.2/Vitis/bin:/opt/Xilinx/2025.2/Vivado/ids_lite/ISE/bin/lin64:/opt/Xilinx/2025.2/Vivado/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log project_reti_logiche.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
||||
@@ -0,0 +1,24 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2025.2 (64-bit)
|
||||
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
||||
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
|
||||
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
|
||||
# Start of session at: Fri Jun 12 14:52:36 2026
|
||||
# Process ID : 33507
|
||||
# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1
|
||||
# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
||||
# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds
|
||||
# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou
|
||||
# Running On : cachyos-x8664
|
||||
# Platform : cachyos
|
||||
# Operating System : CachyOS
|
||||
# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F
|
||||
# CPU Frequency : 4313.234 MHz
|
||||
# CPU Physical cores : 12
|
||||
# CPU Logical cores : 20
|
||||
# Host memory : 16502 MB
|
||||
# Swap memory : 16501 MB
|
||||
# Total Virtual : 33003 MB
|
||||
# Available Virtual : 19387 MB
|
||||
#-----------------------------------------------------------
|
||||
source project_reti_logiche.tcl -notrace
|
||||
Binary file not shown.
Reference in New Issue
Block a user