Aleandro e4437ecdd8 Aggiunti file della relazione

2026-08-25 15:52:38 +02:00

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Aggiunti file della relazione

2026-08-25 15:52:38 +02:00

progetto_reti_logiche.cache

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.hw

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.ip_user_files

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.runs

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.sim/sim_1

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.srcs

Initial commit

2026-06-12 20:37:03 +02:00

progetto_reti_logiche.xpr

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_behav.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_behav1.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_behav.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

project_tb_edge_func_synth.wcfg

Initial commit

2026-06-12 20:37:03 +02:00

S

Description

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105 MiB

Languages

Verilog 45.1%

C 34.8%

VHDL 11.2%

TeX 3.3%

PureBasic 2.9%

Other 2.6%