Aleandro/Progetto-reti-logiche
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Aleandro b26f456e80 Initial commit
2026-06-12 20:42:36 +02:00
.vscode
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2026-06-12 20:42:36 +02:00
Kobo_dev
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2026-06-12 20:42:36 +02:00
KoboShare_client
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2026-06-12 20:42:36 +02:00
KoboShare_client.c
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2026-06-12 20:42:36 +02:00
KoboShare_server
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2026-06-12 20:42:36 +02:00
KoboShare_server.c
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2026-06-12 20:42:36 +02:00
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99 MiB
Languages
Verilog 46.2%
C 35.7%
VHDL 9.6%
PureBasic 3%
TeX 2.8%
Other 2.6%