Aleandro/Progetto-reti-logiche
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Progetto-reti-logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/xsim.dir
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Aleandro 259f6d5803 Initial commit
2026-06-12 20:37:03 +02:00
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project_tb_edge_func_synth
Initial commit
2026-06-12 20:37:03 +02:00
project_tb_func_synth
Initial commit
2026-06-12 20:37:03 +02:00
project_tb_timing_func_synth
Initial commit
2026-06-12 20:37:03 +02:00
xil_defaultlib
Initial commit
2026-06-12 20:37:03 +02:00
xsim.version
Initial commit
2026-06-12 20:37:03 +02:00