153 lines
17 KiB
Plaintext
153 lines
17 KiB
Plaintext
Time resolution is 1 ps
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Note: === GRUPPO 0: Reset ===
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Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.0 OK: reset base
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Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 0.1 OK: reset asincrono durante operazione
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Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 1: Inserimento ===
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Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.0 OK: insert in lista vuota
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Time: 3670100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.1 OK: insert con priorità massima in testa
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Time: 6010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.2 OK: insert con priorità minima in fondo
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Time: 8230100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali
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Time: 10450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo
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Time: 12950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 1.5 OK: insert con ID duplicato ignorato
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Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 2: Rimozione ===
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Time: 15330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0
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Time: 16990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto
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Time: 18930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato
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Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 3: Decremento priorità ===
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Time: 21430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.0 OK: decremento su lista vuota
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Time: 23130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.1 OK: saturazione a priorità 3
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Time: 25350100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica
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Time: 27870100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)
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Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 4: Svuota lista ===
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Time: 30730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 4.0 OK: svuota lista popolata
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Time: 33050100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 4.1 OK: svuota lista già vuota
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Time: 34730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0
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Time: 36690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto
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Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 5: Sequenze composite ===
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Time: 38690100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto
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Time: 41490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 5.1 OK: ordinamento completo con priorità miste
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Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 6: Rimozione multipla e ordinamento ===
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Time: 44730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota
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Time: 48310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1
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Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 7: Decremento ripetuto ===
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Time: 50750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3
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Time: 53430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente
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Time: 57010100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 7.1 OK: decremento su lista con un solo task
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Time: 59330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota
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Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 8: Insert dopo rimozione e casi limite ===
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Time: 61730100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto
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Time: 64950100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato
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Time: 67830100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato
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Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 9: o_task_id per OP diverso da 01 ===
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Time: 70710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1
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Time: 72490100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1
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Time: 74450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1
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Time: 76330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1
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Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 10: Protocollo, reset avanzato, stress ===
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Time: 77990100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset
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Time: 79750100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert)
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Time: 92030100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato
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Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 11: Insert con ID=0 ===
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Time: 94630100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato
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Time: 96290100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato
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Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 12: Capacita' massima 63 task ===
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Time: 98430100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata
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Time: 231450100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati
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Time: 235970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 12.2 OK: drain di 63 task nell'ordine atteso
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Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 13: Stale memory e duplicati ai bordi ===
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Time: 363310100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 13.0 OK: re-insert di ID appena rimosso
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Time: 365710100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 13.1 OK: duplicato in prima posizione ignorato
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Time: 368130100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 13.2 OK: duplicato in ultima posizione ignorato
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Time: 368250100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 13.3 OK: re-insert stesso ID dopo clear
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Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 14: Reset asincrono avanzato ===
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Time: 370330100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 14.0 OK: reset a meta' shift di OP=01
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Time: 373150100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 14.1 OK: reset durante la scrittura del count
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Time: 375930100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 14.2 OK: reset durante OP=00
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Time: 378470100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 14.3 OK: reset mentre DONE=1
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Time: 380550100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 14.4 OK: reset corto non allineato
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Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: === GRUPPO 15: START lento dopo DONE=1 ===
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Time: 382970100 ps Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 15.0 OK: nessun doppio pop con START lento
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Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 15.1 OK: nessun doppio age con START lento
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Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Note: Test 15.2 OK: insert con START tenuto 2 cicli extra
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Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Failure: ======================================
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Tutti i test edge case sono PASSATI
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======================================
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Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616
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Note: === GRUPPO 0: Reset ===
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Time: 389890 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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Failure: FAIL [0.0 reset-addr0] addr=0 expected=0x0 actual=0x1
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Time: 390040 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
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$finish called at time : 390040 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 420
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INFO: xsimkernel Simulation Memory Usage: 294496 KB (Peak: 343308 KB), Simulation CPU Usage: 890 ms
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