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Progetto-reti-logiche/progetto_reti_logiche.sim/sim_1/behav/xsim/simulate.log
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Aleandro 259f6d5803 Initial commit
2026-06-12 20:37:03 +02:00

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Time resolution is 1 ps
Note: === GRUPPO 0: Reset ===
Time: 50 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.0 OK: reset base
Time: 200 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.1 OK: reset asincrono durante operazione
Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 1: Inserimento ===
Time: 1900 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.0 OK: insert in lista vuota
Time: 3670 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.1 OK: insert con priorità massima in testa
Time: 6010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.2 OK: insert con priorità minima in fondo
Time: 8230 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.3 OK: insert stesso prio -> va in coda agli uguali
Time: 10450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.4 OK: insert con tutti uguale prio -> sempre in fondo
Time: 12950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.5 OK: insert con ID duplicato ignorato
Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 2: Rimozione ===
Time: 15330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.0 OK: rimozione da lista vuota -> o_task_id=0
Time: 16990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.1 OK: rimozione unico task -> lista vuota, task_id corretto
Time: 18930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 2.2 OK: rimozione con prio uguali -> FIFO rispettato
Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 3: Decremento priorità ===
Time: 21430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.0 OK: decremento su lista vuota
Time: 23130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.1 OK: saturazione a priorità 3
Time: 25350 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.2 OK: tutti a prio 3 -> nessuna modifica
Time: 27870 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 3.3 OK: ex-prio2 vengono prima di ex-prio3 (no riordino)
Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 4: Svuota lista ===
Time: 30730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.0 OK: svuota lista popolata
Time: 33050 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.1 OK: svuota lista già vuota
Time: 34730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.2 OK: svuota poi rimozione -> o_task_id=0
Time: 36690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 4.3 OK: svuota poi decrementa -> nessun effetto
Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 5: Sequenze composite ===
Time: 38690 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 5.0 OK: insert->dec->remove, ID estratto corretto
Time: 41490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 5.1 OK: ordinamento completo con priorità miste
Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 6: Rimozione multipla e ordinamento ===
Time: 44730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 6.0 OK: rimozioni multiple consecutive fino a lista vuota
Time: 48310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 6.1 OK: rimozione da lista con prio miste -> sempre posizione 1
Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 7: Decremento ripetuto ===
Time: 50750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.0 OK: saturazione progressiva 0->1->2->3->3->3
Time: 53430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.0b OK: decremento ripetuto su prio miste, saturazione indipendente
Time: 57010 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.1 OK: decremento su lista con un solo task
Time: 59330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 7.2 OK: decrementa -> svuota -> rimozione su vuota
Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 8: Insert dopo rimozione e casi limite ===
Time: 61730 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.0 OK: insert dopo rimozione parziale, ordinamento corretto
Time: 64950 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.1 OK: insert prio=0 in lista tutto-prio=0, FIFO rispettato
Time: 67830 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 8.2 OK: insert prio=3 in lista tutto-prio=3, FIFO rispettato
Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 9: o_task_id per OP diverso da 01 ===
Time: 70710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.0 OK: OP=10 -> o_task_id=0 quando DONE=1
Time: 72490 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.1 OK: OP=00 -> o_task_id=0 quando DONE=1
Time: 74450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.2 OK: OP=11 -> o_task_id=0 quando DONE=1
Time: 76330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 9.3 OK: OP=01 lista vuota -> o_task_id=0 quando DONE=1
Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 10: Protocollo, reset avanzato, stress ===
Time: 77990 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.0 OK: operazione immediata dopo DONE->0 post-reset
Time: 79750 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.1 OK: stress test completo (insert/dec/remove/re-insert)
Time: 92030 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 10.2 OK: reset dopo svuota, modulo correttamente reinizializzato
Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 11: Insert con ID=0 ===
Time: 94630 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 11.0 OK: insert ID=0 su lista vuota ignorato
Time: 96290 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 11.1 OK: insert ID=0 su lista popolata ignorato
Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 12: Capacita' massima 63 task ===
Time: 98430 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.0 OK: 63 task inseriti, memoria completa verificata
Time: 231450 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.1 OK: inserimenti oltre il 63esimo tutti ignorati
Time: 235970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 12.2 OK: drain di 63 task nell'ordine atteso
Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 13: Stale memory e duplicati ai bordi ===
Time: 363310 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.0 OK: re-insert di ID appena rimosso
Time: 365710 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.1 OK: duplicato in prima posizione ignorato
Time: 368130 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.2 OK: duplicato in ultima posizione ignorato
Time: 368250 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 13.3 OK: re-insert stesso ID dopo clear
Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 14: Reset asincrono avanzato ===
Time: 370330 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.0 OK: reset a meta' shift di OP=01
Time: 373150 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.1 OK: reset durante la scrittura del count
Time: 375930 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.2 OK: reset durante OP=00
Time: 378470 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.3 OK: reset mentre DONE=1
Time: 380550 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 14.4 OK: reset corto non allineato
Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 15: START lento dopo DONE=1 ===
Time: 382970 ns Iteration: 1 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.0 OK: nessun doppio pop con START lento
Time: 385480 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.1 OK: nessun doppio age con START lento
Time: 387740 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 15.2 OK: insert con START tenuto 2 cicli extra
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Failure: ======================================
Tutti i test edge case sono PASSATI
======================================
Time: 389840 ns Iteration: 0 Process: /project_tb_edge/main_test File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
$finish called at time : 389840 ns : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 1616
INFO: xsimkernel Simulation Memory Usage: 291592 KB (Peak: 337672 KB), Simulation CPU Usage: 710 ms
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