258 lines
19 KiB
Plaintext
258 lines
19 KiB
Plaintext
#-----------------------------------------------------------
|
|
# Vivado v2025.2 (64-bit)
|
|
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
|
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
|
|
# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
|
|
# Start of session at: Fri Jun 12 14:52:36 2026
|
|
# Process ID : 33507
|
|
# Current directory : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1
|
|
# Command line : vivado -log project_reti_logiche.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source project_reti_logiche.tcl
|
|
# Log file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.vds
|
|
# Journal file : /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/vivado.jou
|
|
# Running On : cachyos-x8664
|
|
# Platform : cachyos
|
|
# Operating System : CachyOS
|
|
# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12700F
|
|
# CPU Frequency : 4313.234 MHz
|
|
# CPU Physical cores : 12
|
|
# CPU Logical cores : 20
|
|
# Host memory : 16502 MB
|
|
# Swap memory : 16501 MB
|
|
# Total Virtual : 33003 MB
|
|
# Available Virtual : 19387 MB
|
|
#-----------------------------------------------------------
|
|
source project_reti_logiche.tcl -notrace
|
|
Command: read_checkpoint -auto_incremental -incremental /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp
|
|
INFO: [Vivado 12-5825] Read reference checkpoint from /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/utils_1/imports/synth_1/project_reti_logiche.dcp for incremental synthesis
|
|
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
|
|
Command: synth_design -top project_reti_logiche -part xc7a200tfbg484-1
|
|
Starting synth_design
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
|
|
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
|
|
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
|
|
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
|
|
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
|
INFO: [Synth 8-7075] Helper process launched with PID 33546
|
|
---------------------------------------------------------------------------------
|
|
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2025.719 ; gain = 449.828 ; free physical = 1656 ; free virtual = 17391
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-638] synthesizing module 'project_reti_logiche' [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
|
INFO: [Synth 8-226] default block is never used [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:151]
|
|
INFO: [Synth 8-256] done synthesizing module 'project_reti_logiche' (0#1) [/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd:51]
|
|
---------------------------------------------------------------------------------
|
|
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2111.688 ; gain = 535.797 ; free physical = 1586 ; free virtual = 17326
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Loading Part and Timing Information
|
|
---------------------------------------------------------------------------------
|
|
Loading part: xc7a200tfbg484-1
|
|
INFO: [Device 21-403] Loading part xc7a200tfbg484-1
|
|
---------------------------------------------------------------------------------
|
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2126.531 ; gain = 550.641 ; free physical = 1570 ; free virtual = 17310
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'project_reti_logiche'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
s_reset | 000000000000000000000001 | 00001
|
|
s_done | 000000000000000000000010 | 00010
|
|
s_idle | 000000000000000000000100 | 00000
|
|
s_00_read | 000000000000000000001000 | 00011
|
|
s_00_wait | 000000000000000000010000 | 00100
|
|
s_00_check | 000000000000000000100000 | 00101
|
|
s_00_go_next | 000000000000000001000000 | 00110
|
|
s_01_check_number | 000000000000000010000000 | 00111
|
|
s_01_wait | 000000000000000100000000 | 01000
|
|
s_01_write | 000000000000001000000000 | 01001
|
|
s_01_check_end | 000000000000010000000000 | 01010
|
|
s_01_wait_for_count | 000000000000100000000000 | 01101
|
|
s_01_copy | 000000000001000000000000 | 01011
|
|
s_01_go_next | 000000000010000000000000 | 01100
|
|
s_10_place_at_start | 000000000100000000000000 | 01110
|
|
s_10_wait_for_check | 000000001000000000000000 | 01111
|
|
s_10_check_id | 000000010000000000000000 | 10000
|
|
s_10_wait | 000000100000000000000000 | 10001
|
|
s_10_compare | 000001000000000000000000 | 10010
|
|
s_10_update_count | 000010000000000000000000 | 10100
|
|
s_10_wait_for_count | 000100000000000000000000 | 10101
|
|
s_10_go_next | 001000000000000000000000 | 10011
|
|
s_11_update_count | 010000000000000000000000 | 10110
|
|
s_11_wait_for_count | 100000000000000000000000 | 10111
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'project_reti_logiche'
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2142.547 ; gain = 566.656 ; free physical = 1579 ; free virtual = 17303
|
|
---------------------------------------------------------------------------------
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 16 Bit Adders := 4
|
|
2 Input 9 Bit Adders := 1
|
|
2 Input 8 Bit Adders := 3
|
|
+---Registers :
|
|
16 Bit Registers := 1
|
|
8 Bit Registers := 2
|
|
6 Bit Registers := 2
|
|
1 Bit Registers := 3
|
|
+---Muxes :
|
|
24 Input 24 Bit Muxes := 1
|
|
4 Input 24 Bit Muxes := 1
|
|
2 Input 24 Bit Muxes := 7
|
|
2 Input 16 Bit Muxes := 3
|
|
24 Input 16 Bit Muxes := 1
|
|
2 Input 8 Bit Muxes := 4
|
|
24 Input 8 Bit Muxes := 2
|
|
2 Input 6 Bit Muxes := 1
|
|
24 Input 6 Bit Muxes := 2
|
|
2 Input 1 Bit Muxes := 1
|
|
24 Input 1 Bit Muxes := 6
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 740 (col length:100)
|
|
BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2329.445 ; gain = 753.555 ; free physical = 1430 ; free virtual = 17108
|
|
---------------------------------------------------------------------------------
|
|
No constraint files found.
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2335.383 ; gain = 759.492 ; free physical = 1435 ; free virtual = 17103
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2343.391 ; gain = 767.500 ; free physical = 1433 ; free virtual = 17097
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17328
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17327
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17327
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1673 ; free virtual = 17326
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1674 ; free virtual = 17326
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17326
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+-+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+-+--------------+----------+
|
|
+-+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+-------+------+
|
|
| |Cell |Count |
|
|
+------+-------+------+
|
|
|1 |BUFG | 1|
|
|
|2 |CARRY4 | 18|
|
|
|3 |LUT1 | 34|
|
|
|4 |LUT2 | 16|
|
|
|5 |LUT3 | 25|
|
|
|6 |LUT4 | 44|
|
|
|7 |LUT5 | 22|
|
|
|8 |LUT6 | 78|
|
|
|9 |FDCE | 25|
|
|
|10 |FDPE | 2|
|
|
|11 |FDRE | 44|
|
|
|12 |IBUF | 21|
|
|
|13 |OBUF | 33|
|
|
+------+-------+------+
|
|
|
|
Report Instance Areas:
|
|
+------+---------+-------+------+
|
|
| |Instance |Module |Cells |
|
|
+------+---------+-------+------+
|
|
|1 |top | | 363|
|
|
+------+---------+-------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1675 ; free virtual = 17325
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.203 ; gain = 910.312 ; free physical = 1677 ; free virtual = 17323
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2486.211 ; gain = 910.312 ; free physical = 1669 ; free virtual = 17315
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2500.078 ; gain = 0.000 ; free physical = 1831 ; free virtual = 17463
|
|
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2645.660 ; gain = 0.000 ; free physical = 1835 ; free virtual = 17379
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
Synth Design complete | Checksum: 3d7ece1d
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 2645.695 ; gain = 1069.805 ; free physical = 1881 ; free virtual = 17374
|
|
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1976.781; main = 1976.781; forked = 0.000
|
|
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 2645.664; main = 2645.664; forked = 0.000
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2669.672 ; gain = 0.000 ; free physical = 1881 ; free virtual = 17374
|
|
INFO: [Common 17-1381] The checkpoint '/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.runs/synth_1/project_reti_logiche.dcp' has been generated.
|
|
INFO: [Vivado 12-24828] Executing command : report_utilization -file project_reti_logiche_utilization_synth.rpt -pb project_reti_logiche_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Fri Jun 12 14:52:50 2026...
|