Time resolution is 1 ps
Note: === GRUPPO 0: Reset ===
Time: 50 ns  Iteration: 0  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.0 OK: reset base
Time: 180 ns  Iteration: 0  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 0.1 OK: reset asincrono durante operazione
Time: 1860 ns  Iteration: 0  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: === GRUPPO 1: Inserimento ===
Time: 1860 ns  Iteration: 0  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Note: Test 1.0 OK: insert in lista vuota
Time: 3613737 ps  Iteration: 1  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
Failure: FAIL [1.1 count] addr=0 expected=0x3 actual=0x4
Time: 6013737 ps  Iteration: 1  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 465
Failure: FAIL [1.1 pos1] addr=1 expected=0x4 actual=0x0
Time: 6013737 ps  Iteration: 1  Process: /project_tb_edge/main_test  File: /home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd
$finish called at time : 6013737 ps : File "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" Line 466
INFO: xsimkernel Simulation Memory Usage: 296232 KB (Peak: 342096 KB), Simulation CPU Usage: 820 ms