INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module project_reti_logiche
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'project_tb_edge'
