0.7
2020.2
Nov 14 2025
12:36:23
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/timing/xsim/project_tb_edge_time_synth.v,1781182260,verilog,,,,glbl;project_reti_logiche,,,../../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sim_1/new/project_tb_edge.vhd,1781179764,vhdl,,,,project_tb_edge,,,,,,,,
