INFO: [VRFC 10-2263] Analyzing Verilog file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.sim/sim_1/synth/func/xsim/project_tb_edge_func_synth.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module project_reti_logiche
INFO: [VRFC 10-311] analyzing module glbl
