INFO: [VRFC 10-163] Analyzing VHDL file "/home/aleandro/Projects/progetto_reti_logiche/progetto_reti_logiche.srcs/sources_1/new/progetto_reti_logiche.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'project_reti_logiche'
