#!/bin/bash -f
# ****************************************************************************
# Vivado (TM) v2025.2 (64-bit)
#
# Filename    : compile.sh
# Simulator   : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Thu Jun 11 14:51:00 CEST 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
#
# usage: compile.sh
#
# ****************************************************************************
export SIM_VER_XSIM=2025.2
export GCC_VER_XSIM=9.3.0

# catch pipeline exit status
set -Eeuo pipefail
# compile Verilog/System Verilog design sources
echo "xvlog --incr --relax -prj project_tb_edge_vlog.prj"
xvlog --incr --relax -prj project_tb_edge_vlog.prj 2>&1 | tee compile.log

# compile VHDL design sources
echo "xvhdl --incr --relax -prj project_tb_edge_vhdl.prj"
xvhdl --incr --relax -prj project_tb_edge_vhdl.prj 2>&1 | tee -a compile.log

echo "Waiting for jobs to finish..."
echo "No pending jobs, compilation finished."
